diff options
| author | Harry Wentland <harry.wentland@amd.com> | 2019-02-22 18:19:04 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 02:59:34 +0300 |
| commit | 2d78b3a177fea66cf576a420d2ff83811643c021 (patch) | |
| tree | 022648f06a6c2c860dd24c1685dbb4965d8279ad /drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | |
| parent | fcee01b9f82d44a4f62791f710ede954731df1bf (diff) | |
| download | linux-2d78b3a177fea66cf576a420d2ff83811643c021.tar.xz | |
drm/amd/display: Add DCN2 OPTC
Add support for programming the DCN2 OPTC (Output Timing Controller)
HW Blocks:
+--------+
| OPTC |
+--------+
|
v
+--------+ +--------+
| DIO | | DCCG |
+--------+ +--------+
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h index 4c8e2c6fb6db..1ff6a841fdd2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h @@ -35,6 +35,9 @@ ******************************************************************************/ #define MAX_PIPES 6 +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +#define MAX_DWB_PIPES 1 +#endif struct gamma_curve { uint32_t offset; @@ -77,6 +80,37 @@ struct pwl_result_data { uint32_t delta_blue_reg; }; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +struct dc_rgb { + uint32_t red; + uint32_t green; + uint32_t blue; +}; + +struct tetrahedral_17x17x17 { + struct dc_rgb lut0[1229]; + struct dc_rgb lut1[1228]; + struct dc_rgb lut2[1228]; + struct dc_rgb lut3[1228]; +}; +struct tetrahedral_9x9x9 { + struct dc_rgb lut0[183]; + struct dc_rgb lut1[182]; + struct dc_rgb lut2[182]; + struct dc_rgb lut3[182]; +}; + +struct tetrahedral_params { + union { + struct tetrahedral_17x17x17 tetrahedral_17; + struct tetrahedral_9x9x9 tetrahedral_9; + }; + bool use_tetrahedral_9; + bool use_12bits; + +}; +#endif + /* arr_curve_points - regamma regions/segments specification * arr_points - beginning and end point specified separately (only one on DCE) * corner_points - beginning and end point for all 3 colors (DCN) @@ -160,6 +194,7 @@ enum opp_regamma { OPP_REGAMMA_USER }; + struct dc_bias_and_scale { uint16_t scale_red; uint16_t bias_red; @@ -181,7 +216,12 @@ enum test_pattern_mode { TEST_PATTERN_MODE_VERTICALBARS, TEST_PATTERN_MODE_HORIZONTALBARS, TEST_PATTERN_MODE_SINGLERAMP_RGB, +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + TEST_PATTERN_MODE_DUALRAMP_RGB, + TEST_PATTERN_MODE_XR_BIAS_RGB +#else TEST_PATTERN_MODE_DUALRAMP_RGB +#endif }; enum test_pattern_color_format { @@ -203,7 +243,8 @@ enum controller_dp_test_pattern { CONTROLLER_DP_TEST_PATTERN_RESERVED_8, CONTROLLER_DP_TEST_PATTERN_RESERVED_9, CONTROLLER_DP_TEST_PATTERN_RESERVED_A, - CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA + CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA, + CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR }; enum dc_lut_mode { |