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| author | Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> | 2023-11-09 08:04:36 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-02-05 23:14:26 +0300 |
| commit | 1c563c04509080b374af5adf8e1c45718e3f37bf (patch) | |
| tree | a2f4eef8027ed6974fd73978077b5b9e71883513 /drivers/gpu/drm/amd/display/dc | |
| parent | 1e0635bcda5b97a54da28fbb09758d560c0f970a (diff) | |
| download | linux-1c563c04509080b374af5adf8e1c45718e3f37bf.tar.xz | |
drm/amd/display: Fix tiled display misalignment
[ Upstream commit c4b8394e76adba4f50a3c2696c75b214a291e24a ]
[Why]
When otg workaround is applied during clock update, otgs of
tiled display went out of sync.
[How]
To call dc_trigger_sync() after clock update to sync otgs again.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8cdf380bf366..46b10ff8f6d4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1948,6 +1948,10 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c wait_for_no_pipes_pending(dc, context); /* pplib is notified if disp_num changed */ dc->hwss.optimize_bandwidth(dc, context); + /* Need to do otg sync again as otg could be out of sync due to otg + * workaround applied during clock update + */ + dc_trigger_sync(dc, context); } if (dc->hwss.update_dsc_pg) |