diff options
| author | Hansen <Hansen.Dsouza@amd.com> | 2021-09-09 22:12:32 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-28 21:26:16 +0300 |
| commit | 3137f792c5bd68c799a9c3762fd37e428bbcf152 (patch) | |
| tree | 1c5ba79f9185aeddff3eedfd43ec163cc3372ba0 /drivers/gpu/drm/amd/display/dmub/dmub_srv.h | |
| parent | a9a1ac44074ff8cab7d519277f93341e14557f83 (diff) | |
| download | linux-3137f792c5bd68c799a9c3762fd37e428bbcf152.tar.xz | |
drm/amd/display: Set phy_mux_sel bit in dmub scratch register
[Why]
B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or
PHYC/PHY D.
[How]
Based on chip internal hardware revision id determine it is B0 and set
DMUB scratch register so DMUBFW can connect the display pipe is
connected correctly to the dig.
Cc: Wayne Lin <wayne.lin@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Hansen <Hansen.Dsouza@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/dmub_srv.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index 365fbc4758e1..6c4f0ada163f 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -97,6 +97,7 @@ enum dmub_asic { DMUB_ASIC_DCN302, DMUB_ASIC_DCN303, DMUB_ASIC_DCN31, + DMUB_ASIC_DCN31B, DMUB_ASIC_MAX, }; |