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| author | Arnaldo Carvalho de Melo <acme@redhat.com> | 2020-08-06 14:15:47 +0300 |
|---|---|---|
| committer | Arnaldo Carvalho de Melo <acme@redhat.com> | 2020-08-06 14:15:47 +0300 |
| commit | 94fb1afb14c4f0ceb8c5508ddddac6819f662e95 (patch) | |
| tree | 4988e5769dc7482caa7f441475ae31f50bbd37ef /drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | |
| parent | c4735d990268399da9133b0ad445e488ece009ad (diff) | |
| parent | 47ec5303d73ea344e84f46660fff693c57641386 (diff) | |
| download | linux-94fb1afb14c4f0ceb8c5508ddddac6819f662e95.tar.xz | |
Mgerge remote-tracking branch 'torvalds/master' into perf/core
To sync headers, for instance, in this case tools/perf was ahead of
upstream till Linus merged tip/perf/core to get the
PERF_RECORD_TEXT_POKE changes:
Warning: Kernel ABI header at 'tools/include/uapi/linux/perf_event.h' differs from latest version at 'include/uapi/linux/perf_event.h'
diff -u tools/include/uapi/linux/perf_event.h include/uapi/linux/perf_event.h
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 34 |
1 files changed, 26 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c index edc73d6d7ba2..2c4a2fe9311d 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c @@ -215,11 +215,22 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, /* TODO: Move this to CW4. */ dmub_dcn20_translate_addr(&cw4->offset, fb_base, fb_offset, &offset); - REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); - REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); - REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, DMCUB_REGION4_TOP_ADDRESS, - cw4->region.top - cw4->region.base - 1, DMCUB_REGION4_ENABLE, - 1); + /* New firmware can support CW4. */ + if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) { + REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); + REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); + REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, + DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, + DMCUB_REGION3_CW4_ENABLE, 1); + } else { + REG_WRITE(DMCUB_REGION4_OFFSET, offset.u.low_part); + REG_WRITE(DMCUB_REGION4_OFFSET_HIGH, offset.u.high_part); + REG_SET_2(DMCUB_REGION4_TOP_ADDRESS, 0, + DMCUB_REGION4_TOP_ADDRESS, + cw4->region.top - cw4->region.base - 1, + DMCUB_REGION4_ENABLE, 1); + } dmub_dcn20_translate_addr(&cw5->offset, fb_base, fb_offset, &offset); @@ -243,9 +254,12 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub, void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1) { - /* TODO: Use CW4 instead of region 4. */ + /* New firmware can support CW4 for the inbox. */ + if (dmub->fw_version > DMUB_FW_VERSION(1, 0, 10)) + REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); + else + REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000); - REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, 0x80000000); REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); } @@ -261,7 +275,11 @@ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub) { - return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0; + uint32_t is_hw_init; + + REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); + + return is_hw_init != 0; } bool dmub_dcn20_is_supported(struct dmub_srv *dmub) |