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authorAnthony Koo <Anthony.Koo@amd.com>2023-03-25 16:55:13 +0300
committerAlex Deucher <alexander.deucher@amd.com>2023-04-12 01:03:43 +0300
commit9dce8c2a5f1bf5a304aae39342816f099247d7da (patch)
treedf13e93df28324eb5b7ff8febca31ad00287eeae /drivers/gpu/drm/amd/display/dmub
parent7727e7b60f82e8265a1061b81379f5a7bce0dba6 (diff)
downloadlinux-9dce8c2a5f1bf5a304aae39342816f099247d7da.tar.xz
drm/amd/display: [FW Promotion] Release 0.0.161.0
- Add command to idle opt. - Rename d3 entry event and add idle trigger param on notify event. - Add bit to fw boot status to notify status when hardware is powered up. Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub')
-rw-r--r--drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h28
1 files changed, 26 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 15d26222597a..598fa1de54ce 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -362,7 +362,7 @@ union dmub_fw_boot_status {
uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
uint32_t reserved : 1;
uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
-
+ uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
} bits; /**< status bits */
uint32_t all; /**< 32-bit access to status bits */
};
@@ -377,6 +377,7 @@ enum dmub_fw_boot_status_bit {
DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
+ DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
};
/* Register bit definition for SCRATCH5 */
@@ -1104,7 +1105,12 @@ enum dmub_cmd_idle_opt_type {
/**
* DCN hardware save.
*/
- DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1
+ DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
+
+ /**
+ * DCN hardware notify idle.
+ */
+ DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2
};
/**
@@ -1115,6 +1121,24 @@ struct dmub_rb_cmd_idle_opt_dcn_restore {
};
/**
+ * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
+ */
+struct dmub_dcn_notify_idle_cntl_data {
+ uint8_t driver_idle;
+ uint8_t d3_entry;
+ uint8_t trigger;
+ uint8_t pad[1];
+};
+
+/**
+ * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
+ */
+struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
+ struct dmub_cmd_header header; /**< header */
+ struct dmub_dcn_notify_idle_cntl_data cntl_data;
+};
+
+/**
* struct dmub_clocks - Clock update notification.
*/
struct dmub_clocks {