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| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2022-12-23 10:54:43 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-09 16:52:57 +0300 |
| commit | d90d90a1978af6530c7d8b201c4ab117d0506b1a (patch) | |
| tree | 2400e9ea1a00b6c9cea5b6d677d3780406d0d33f /drivers/gpu/drm/amd/include/asic_reg | |
| parent | e53a3250f76b8a0dd5b533bd0ce0dc821055e77d (diff) | |
| download | linux-d90d90a1978af6530c7d8b201c4ab117d0506b1a.tar.xz | |
drm/amdgpu: Add sdma v4_4_2 ras registers
SDMA_UE_ERR_STATUS_HI|LO are introduced in v4_4_2
to replace SDMA_EDC_COUNTER/COUNTER2 registers to
log SDMA RAS errors
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_offset.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h | 24 |
2 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_offset.h index 31bef0776ded..ead81aeffd67 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_offset.h @@ -211,6 +211,10 @@ #define regSDMA_RAS_STATUS_BASE_IDX 0 #define regSDMA_CLK_STATUS 0x0068 #define regSDMA_CLK_STATUS_BASE_IDX 0 +#define regSDMA_UE_ERR_STATUS_LO 0x0069 +#define regSDMA_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regSDMA_UE_ERR_STATUS_HI 0x006a +#define regSDMA_UE_ERR_STATUS_HI_BASE_IDX 0 #define regSDMA_POWER_CNTL 0x006b #define regSDMA_POWER_CNTL_BASE_IDX 0 #define regSDMA_CLK_CTRL 0x006c diff --git a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h index e46cb3339355..290953bdf1d6 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/sdma/sdma_4_4_2_sh_mask.h @@ -1171,6 +1171,30 @@ #define SDMA_CLK_STATUS__F32_CLK_MASK 0x00000008L #define SDMA_CLK_STATUS__CE_CLK_MASK 0x00000010L #define SDMA_CLK_STATUS__PERF_CLK_MASK 0x00000020L +//SDMA_UE_ERR_STATUS_LO +#define SDMA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define SDMA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define SDMA_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define SDMA_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define SDMA_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define SDMA_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define SDMA_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define SDMA_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//SDMA_UE_ERR_STATUS_HI +#define SDMA_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define SDMA_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define SDMA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define SDMA_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define SDMA_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define SDMA_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define SDMA_UE_ERR_STATUS_HI__RESERVED__SHIFT 0x1d +#define SDMA_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define SDMA_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define SDMA_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define SDMA_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define SDMA_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define SDMA_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define SDMA_UE_ERR_STATUS_HI__RESERVED_MASK 0xE0000000L //SDMA_POWER_CNTL #define SDMA_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 #define SDMA_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 |