diff options
| author | Evan Quan <evan.quan@amd.com> | 2022-04-28 11:51:04 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-06-08 18:43:00 +0300 |
| commit | 62f8f5c3bfc2968461b0a74f0e393325bec16c69 (patch) | |
| tree | 8630dc0dbf76718baa883d2cf1d5b9b387589991 /drivers/gpu/drm/amd/include | |
| parent | 6f73d6762694c3e91c49e6708077a0de2a75f2f5 (diff) | |
| download | linux-62f8f5c3bfc2968461b0a74f0e393325bec16c69.tar.xz | |
drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.0
Enable ASPM support for PCIE 7.4.0 and 7.6.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h index 53802d674e13..4b489d64deaa 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_offset.h @@ -6918,6 +6918,8 @@ #define regPSWUSCFG0_SSID_CAP 0x2880031 #define regPSWUSCFG0_SSID_CAP_BASE_IDX 5 +#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL 0x2890102 +#define regPCIE_LC_RXRECOVER_RXSTANDBY_CNTL_BASE_IDX 5 // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp // base address: 0x10100000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h index f3cda48bfaeb..d038fd915351 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_4_3_0_sh_mask.h @@ -82045,5 +82045,6 @@ #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__FLR_TIME_MASK 0x00000FFFL #define BIF_CFG_DEV0_EPF3_1_RTR_DATA2__D3HOTD0_TIME_MASK 0x00FFF000L +#define PCIE_LC_RXRECOVER_RXSTANDBY_CNTL__LC_RX_L0S_STANDBY_EN_MASK 0x00010000L #endif |