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| author | Liviu Dudau <Liviu.Dudau@arm.com> | 2017-03-29 19:42:34 +0300 |
|---|---|---|
| committer | Liviu Dudau <Liviu.Dudau@arm.com> | 2018-07-05 17:19:00 +0300 |
| commit | 846c87a068f4b72e200357b899ca4dcc92ef42c4 (patch) | |
| tree | 6832af07e5a6aaf66f8b3e44cdf40aea220dca74 /drivers/gpu/drm/arm/malidp_regs.h | |
| parent | f29135ee4e0d4e01911ed569f731bfdb841cea6d (diff) | |
| download | linux-846c87a068f4b72e200357b899ca4dcc92ef42c4.tar.xz | |
drm: mali-dp: Add support for writeback on DP550/DP650
Mali-DP display processors are able to write the composition result to a
memory buffer via the SE.
Add entry points in the HAL for enabling/disabling this feature, and
implement support for it on DP650 and DP550. DP500 acts differently and
so is omitted from this change.
Changes since v3:
- Fix missing vsync interrupt for DP550
Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Brian Starkey <brian.starkey@arm.com>
[rebased and fixed conflicts]
Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com>
Diffstat (limited to 'drivers/gpu/drm/arm/malidp_regs.h')
| -rw-r--r-- | drivers/gpu/drm/arm/malidp_regs.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/arm/malidp_regs.h b/drivers/gpu/drm/arm/malidp_regs.h index 149024fb4432..e2b2c496225e 100644 --- a/drivers/gpu/drm/arm/malidp_regs.h +++ b/drivers/gpu/drm/arm/malidp_regs.h @@ -66,6 +66,8 @@ #define MALIDP_DISP_FUNC_GAMMA (1 << 0) #define MALIDP_DISP_FUNC_CADJ (1 << 4) #define MALIDP_DISP_FUNC_ILACED (1 << 8) +#define MALIDP_SCALE_ENGINE_EN (1 << 16) +#define MALIDP_SE_MEMWRITE_EN (2 << 5) /* register offsets for IRQ management */ #define MALIDP_REG_STATUS 0x00000 @@ -153,6 +155,16 @@ (((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16) #define MALIDP_SE_ENH_COEFF0 0x04 + +/* register offsets relative to MALIDP5x0_SE_MEMWRITE_BASE */ +#define MALIDP_MW_FORMAT 0x00000 +#define MALIDP_MW_P1_STRIDE 0x00004 +#define MALIDP_MW_P2_STRIDE 0x00008 +#define MALIDP_MW_P1_PTR_LOW 0x0000c +#define MALIDP_MW_P1_PTR_HIGH 0x00010 +#define MALIDP_MW_P2_PTR_LOW 0x0002c +#define MALIDP_MW_P2_PTR_HIGH 0x00030 + /* register offsets and bits specific to DP500 */ #define MALIDP500_ADDR_SPACE_SIZE 0x01000 #define MALIDP500_DC_BASE 0x00000 @@ -217,6 +229,9 @@ #define MALIDP550_DE_PERF_BASE 0x00500 #define MALIDP550_SE_BASE 0x08000 #define MALIDP550_SE_CONTROL 0x08010 +#define MALIDP550_SE_MEMWRITE_ONESHOT (1 << 7) +#define MALIDP550_SE_MEMWRITE_OUT_SIZE 0x08030 +#define MALIDP550_SE_MEMWRITE_BASE 0x08100 #define MALIDP550_DC_BASE 0x0c000 #define MALIDP550_DC_CONTROL 0x0c010 #define MALIDP550_DC_CONFIG_REQ (1 << 16) |