diff options
| author | zain wang <wzz@rock-chips.com> | 2018-04-23 13:49:42 +0300 |
|---|---|---|
| committer | Andrzej Hajda <a.hajda@samsung.com> | 2018-04-24 09:34:34 +0300 |
| commit | d79acb593290e1faeec6d9032c08fc0ab38080e0 (patch) | |
| tree | b37191ec074a607cb470424a031003b6e358a588 /drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | |
| parent | 7f6414143a61f9eb369c90ef0550c9ef8e603d57 (diff) | |
| download | linux-d79acb593290e1faeec6d9032c08fc0ab38080e0.tar.xz | |
drm/bridge: analogix_dp: Set PD_INC_BG first when powering up edp phy
Following the correct power up sequence:
dp_pd=ff => dp_pd=7f => wait 10us => dp_pd=00
Cc: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: zain wang <wzz@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Escande <thierry.escande@collabora.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-7-enric.balletbo@collabora.com
Diffstat (limited to 'drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c')
| -rw-r--r-- | drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c index b47c5af43560..bb72f8b0e603 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c @@ -321,10 +321,16 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, break; case POWER_ALL: if (enable) { - reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | - CH1_PD | CH0_PD; + reg = DP_ALL_PD; writel(reg, dp->reg_base + phy_pd_addr); } else { + reg = DP_ALL_PD; + writel(reg, dp->reg_base + phy_pd_addr); + usleep_range(10, 15); + reg &= ~DP_INC_BG; + writel(reg, dp->reg_base + phy_pd_addr); + usleep_range(10, 15); + writel(0x00, dp->reg_base + phy_pd_addr); } break; |