diff options
| author | Yakir Yang <ykk@rock-chips.com> | 2016-06-29 12:15:18 +0300 |
|---|---|---|
| committer | Yakir Yang <ykk@rock-chips.com> | 2016-07-05 04:16:40 +0300 |
| commit | 7bdc072086939093238a970f054e8e63d531253d (patch) | |
| tree | 196452ddb8620fedcebafb39e672d922b94d0875 /drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | |
| parent | cb5571fcf809860c455f6b62bb5252f277b52e83 (diff) | |
| download | linux-7bdc072086939093238a970f054e8e63d531253d.tar.xz | |
drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
As vendor document indicate, when REF_CLK bit set 0, then DP
phy's REF_CLK should switch to 24M source clock.
But due to IC PHY layout mistaken, some chips need to flip this
bit(like RK3288), and unfortunately they didn't indicate in the
DP version register. That's why we have to make this little hack.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h')
| -rw-r--r-- | drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h index 88d56ad5c010..cdcc6c5add5e 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h @@ -165,6 +165,7 @@ /* ANALOGIX_DP_PLL_REG_1 */ #define REF_CLK_24M (0x1 << 0) #define REF_CLK_27M (0x0 << 0) +#define REF_CLK_MASK (0x1 << 0) /* ANALOGIX_DP_LANE_MAP */ #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) |