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author | Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | 2020-12-15 13:05:43 +0300 |
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committer | Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | 2020-12-15 13:05:43 +0300 |
commit | ae75a0431f822273ce5d3a574863c67503db5775 (patch) | |
tree | 1361bf5e24d1d38f993c08583f42eda4fb28b42e /drivers/gpu/drm/etnaviv | |
parent | 91def3cce986238db7c06af083b8e9e30372a895 (diff) | |
parent | 5fbd41d3bf123af6a135bdea564087ec0f563eb0 (diff) | |
download | linux-ae75a0431f822273ce5d3a574863c67503db5775.tar.xz |
Merge drm/drm-next into drm-misc-next
Required backmerge since we will be based on top of v5.11, and there
has been a request to backmerge already to upstream some features.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/etnaviv')
-rw-r--r-- | drivers/gpu/drm/etnaviv/etnaviv_drv.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/etnaviv/etnaviv_drv.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/etnaviv/etnaviv_mmu.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/etnaviv/etnaviv_perfmon.c | 78 |
4 files changed, 59 insertions, 27 deletions
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c index 7604e3c07973..f0a07278ad04 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c @@ -522,7 +522,6 @@ static int etnaviv_bind(struct device *dev) } drm->dev_private = priv; - dev->dma_parms = &priv->dma_parms; dma_set_max_seg_size(dev, SZ_2G); mutex_init(&priv->gem_lock); @@ -572,8 +571,6 @@ static void etnaviv_unbind(struct device *dev) component_unbind_all(dev, drm); - dev->dma_parms = NULL; - etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc); drm->dev_private = NULL; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h b/drivers/gpu/drm/etnaviv/etnaviv_drv.h index f5be627e1de0..003288ebd896 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h @@ -33,7 +33,6 @@ struct etnaviv_file_private { struct etnaviv_drm_private { int num_gpus; - struct device_dma_parameters dma_parms; struct etnaviv_gpu *gpu[ETNA_MAX_PIPES]; gfp_t shm_gfp_mask; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c index 15d9fa3879e5..dab1b58006d8 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_mmu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_mmu.c @@ -124,6 +124,8 @@ static void etnaviv_iommu_remove_mapping(struct etnaviv_iommu_context *context, { struct etnaviv_gem_object *etnaviv_obj = mapping->object; + lockdep_assert_held(&context->lock); + etnaviv_iommu_unmap(context, mapping->vram_node.start, etnaviv_obj->sgt, etnaviv_obj->base.size); drm_mm_remove_node(&mapping->vram_node); @@ -216,6 +218,8 @@ static int etnaviv_iommu_find_iova(struct etnaviv_iommu_context *context, static int etnaviv_iommu_insert_exact(struct etnaviv_iommu_context *context, struct drm_mm_node *node, size_t size, u64 va) { + lockdep_assert_held(&context->lock); + return drm_mm_insert_node_in_range(&context->mm, node, size, 0, 0, va, va + size, DRM_MM_INSERT_LOWEST); } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c index 75f9db8f7bec..bafdfe49c1d8 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_perfmon.c @@ -46,6 +46,33 @@ static u32 perf_reg_read(struct etnaviv_gpu *gpu, return gpu_read(gpu, domain->profile_read); } +static inline void pipe_select(struct etnaviv_gpu *gpu, u32 clock, unsigned pipe) +{ + clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); + clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(pipe); + + gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); +} + +static u32 pipe_perf_reg_read(struct etnaviv_gpu *gpu, + const struct etnaviv_pm_domain *domain, + const struct etnaviv_pm_signal *signal) +{ + u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); + u32 value = 0; + unsigned i; + + for (i = 0; i < gpu->identity.pixel_pipes; i++) { + pipe_select(gpu, clock, i); + value += perf_reg_read(gpu, domain, signal); + } + + /* switch back to pixel pipe 0 to prevent GPU hang */ + pipe_select(gpu, clock, 0); + + return value; +} + static u32 pipe_reg_read(struct etnaviv_gpu *gpu, const struct etnaviv_pm_domain *domain, const struct etnaviv_pm_signal *signal) @@ -55,17 +82,12 @@ static u32 pipe_reg_read(struct etnaviv_gpu *gpu, unsigned i; for (i = 0; i < gpu->identity.pixel_pipes; i++) { - clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); - clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(i); - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); - gpu_write(gpu, domain->profile_config, signal->data); - value += gpu_read(gpu, domain->profile_read); + pipe_select(gpu, clock, i); + value += gpu_read(gpu, signal->data); } /* switch back to pixel pipe 0 to prevent GPU hang */ - clock &= ~(VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK); - clock |= VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(0); - gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); + pipe_select(gpu, clock, 0); return value; } @@ -103,9 +125,19 @@ static const struct etnaviv_pm_domain doms_3d[] = { .name = "HI", .profile_read = VIVS_MC_PROFILE_HI_READ, .profile_config = VIVS_MC_PROFILE_CONFIG2, - .nr_signals = 5, + .nr_signals = 7, .signal = (const struct etnaviv_pm_signal[]) { { + "TOTAL_READ_BYTES8", + VIVS_HI_PROFILE_READ_BYTES8, + &pipe_reg_read, + }, + { + "TOTAL_WRITE_BYTES8", + VIVS_HI_PROFILE_WRITE_BYTES8, + &pipe_reg_read, + }, + { "TOTAL_CYCLES", 0, &hi_total_cycle_read @@ -141,22 +173,22 @@ static const struct etnaviv_pm_domain doms_3d[] = { { "PIXEL_COUNT_KILLED_BY_COLOR_PIPE", VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE, - &pipe_reg_read + &pipe_perf_reg_read }, { "PIXEL_COUNT_KILLED_BY_DEPTH_PIPE", VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE, - &pipe_reg_read + &pipe_perf_reg_read }, { "PIXEL_COUNT_DRAWN_BY_COLOR_PIPE", VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE, - &pipe_reg_read + &pipe_perf_reg_read }, { "PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE", VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE, - &pipe_reg_read + &pipe_perf_reg_read } } }, @@ -184,32 +216,32 @@ static const struct etnaviv_pm_domain doms_3d[] = { { "VS_INST_COUNTER", VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read }, { "RENDERED_VERTICE_COUNTER", VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read }, { "VTX_BRANCH_INST_COUNTER", VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read }, { "VTX_TEXLD_INST_COUNTER", VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read }, { "PXL_BRANCH_INST_COUNTER", VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read }, { "PXL_TEXLD_INST_COUNTER", VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read } } }, @@ -237,17 +269,17 @@ static const struct etnaviv_pm_domain doms_3d[] = { { "DEPTH_CLIPPED_COUNTER", VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read }, { "TRIVIAL_REJECTED_COUNTER", VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read }, { "CULLED_COUNTER", VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER, - &pipe_reg_read + &pipe_perf_reg_read } } }, @@ -400,7 +432,7 @@ static const struct etnaviv_pm_domain doms_2d[] = { { "PIXELS_RENDERED_2D", VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D, - &pipe_reg_read + &pipe_perf_reg_read } } } |