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| author | Stefan Agner <stefan@agner.ch> | 2016-03-23 01:45:29 +0300 |
|---|---|---|
| committer | Stefan Agner <stefan@agner.ch> | 2016-04-26 06:27:18 +0300 |
| commit | f93500f430733178dfd8f9c80e52b13d0f273dd3 (patch) | |
| tree | 8bedc70a345953ae14aeb90647790df7b7cab5b0 /drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | |
| parent | 73fa30337a936695eeebecfa2c48ff567361c793 (diff) | |
| download | linux-f93500f430733178dfd8f9c80e52b13d0f273dd3.tar.xz | |
drm/fsl-dcu: add extra clock for pixel clock
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible for old device trees.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Diffstat (limited to 'drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index 4ed7798533f9..87d85faaac6a 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -71,7 +71,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) unsigned long dcuclk; index = drm_crtc_index(crtc); - dcuclk = clk_get_rate(fsl_dev->clk); + dcuclk = clk_get_rate(fsl_dev->pix_clk); div = dcuclk / mode->clock / 1000; /* Configure timings: */ |