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authorAlan Cox <alan@linux.intel.com>2012-04-25 17:36:34 +0400
committerDave Airlie <airlied@redhat.com>2012-04-27 12:23:10 +0400
commit642c52fcc98aa441bda8c7d8252e8b9b563b370b (patch)
treeae82b0608f97abf08bbbe9a2a72574be8640cea6 /drivers/gpu/drm/gma500/psb_drv.h
parent1896344b181549cea0ab38a810f4f8efcd6ecafb (diff)
downloadlinux-642c52fcc98aa441bda8c7d8252e8b9b563b370b.tar.xz
gma500: read the PLL bits
We need to pull more stuff from the VBT in order to configure the clocking correctly in all cases. Add the relevant bits from the other CDV driver work. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/gma500/psb_drv.h')
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 40ce2c9bc2e4..4c50969fd193 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -669,6 +669,8 @@ struct drm_psb_private {
u32 dspcntr[3];
int mdfld_panel_id;
+
+ bool dplla_96mhz; /* DPLL data from the VBT */
};