diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-14 01:52:55 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2023-02-18 00:40:56 +0300 |
| commit | 050db7d70c3c6cf72d11dde8961f953f990b9c6e (patch) | |
| tree | 73e4ecb14311f2dfff38a9fc83213f30b4d99f57 /drivers/gpu/drm/i915/display/icl_dsi.c | |
| parent | 9c0cd4bb9a2da8c69cd9331ba1824bca027d6090 (diff) | |
| download | linux-050db7d70c3c6cf72d11dde8961f953f990b9c6e.tar.xz | |
drm/i915: Define transcoder timing register bitmasks
Define the contents of the transcoder timing registers using
REG_GENMASK() & co. For ease of maintenance let's just define
the bitmasks with the full 16bit width (also used by the
current hand rolled stuff) even though not all bits are actually
used. None of the unsued bits have ever contained anything.
Jani spotted that the CRT load detection code did use narrower
bitmasks, so that is now going to change. But that is fine
since any garbage in the high bits would have been caught by
the state checker that always used the full 16bit masks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230213225258.2127-10-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/icl_dsi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/icl_dsi.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 07897d6f9c53..def3aff4d717 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -888,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans), - (hactive - 1) | ((htotal - 1) << 16)); + HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); } /* TRANS_HSYNC register to be programmed only for video mode */ @@ -911,7 +911,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans), - (hsync_start - 1) | ((hsync_end - 1) << 16)); + HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); } } @@ -925,7 +925,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, * For interlace mode: program required pixel minus 2 */ intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans), - (vactive - 1) | ((vtotal - 1) << 16)); + VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); } if (vsync_end < vsync_start || vsync_end > vtotal) @@ -939,7 +939,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans), - (vsync_start - 1) | ((vsync_end - 1) << 16)); + VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); } } @@ -962,7 +962,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans), - (vactive - 1) | ((vtotal - 1) << 16)); + VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); } } } |