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| author | Dave Airlie <airlied@redhat.com> | 2022-06-24 05:07:36 +0300 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2022-06-24 05:07:47 +0300 |
| commit | 805ada63ba0567b15d10d40419bcc5e6f0b461e6 (patch) | |
| tree | 1c19fac5272414fb3804e3c37c71182e8b21b73d /drivers/gpu/drm/i915/display/intel_opregion.c | |
| parent | 0936de1e96d6cbcd3d0ede8f31b1c3e6570dad2e (diff) | |
| parent | 6434cf630086eea2d091f122f5802582a05d9d1c (diff) | |
| download | linux-805ada63ba0567b15d10d40419bcc5e6f0b461e6.tar.xz | |
Merge tag 'drm-intel-next-2022-06-22' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- General driver clean-up (Jani, Ville, Julia)
- DG2 enabling (Anusha, Vandita)
- Fix sparse warnings (Imre, Jani)
- DMC MMIO range checks (Anusha)
- Audio related fixes (Jani)
- Runtime PM fixes (Anshuman)
- PSR fixes (Jouni, Jose)
- Media freq factor and per-gt enhancements (Ashutosh, Dale)
- DSI fixes for ICL+ (Jani)
- Disable DMC flip queue handlers (Imre)
- ADL_P voltage swing updates (Balasubramani)
- Use more the VBT for panel information (Ville, Animesh)
- Fix on Type-C ports with TBT mode (Vivek)
- Improve fastset and allow seamless M/N changes (Ville)
- Accept more fixed modes with VRR/DMRRS panels (Ville)
- FBC fix (Jose)
- Remove noise logs (Luca)
- Disable connector polling for a headless SKU (Jouni)
- Sanitize display underrun reporting (Ville)
- ADL-S display PLL w/a (Ville)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YrNzP2WTf3WBvpvd@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_opregion.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_opregion.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index 3aea4e42d55e..1c0c745c142d 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -55,6 +55,8 @@ #define MBOX_ASLE_EXT BIT(4) /* Mailbox #5 */ #define MBOX_BACKLIGHT BIT(5) /* Mailbox #2 (valid from v3.x) */ +#define PCON_HEADLESS_SKU BIT(13) + struct opregion_header { u8 signature[16]; u32 size; @@ -1137,6 +1139,18 @@ struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector) return new_edid; } +bool intel_opregion_headless_sku(struct drm_i915_private *i915) +{ + struct intel_opregion *opregion = &i915->opregion; + struct opregion_header *header = opregion->header; + + if (!header || header->over.major < 2 || + (header->over.major == 2 && header->over.minor < 3)) + return false; + + return opregion->header->pcon & PCON_HEADLESS_SKU; +} + void intel_opregion_register(struct drm_i915_private *i915) { struct intel_opregion *opregion = &i915->opregion; |