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| author | Jouni Högander <jouni.hogander@intel.com> | 2023-03-29 18:07:01 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2023-03-31 08:43:18 +0300 |
| commit | f389e7ac8d8a9a17bf59507d02ffb756c19b4af5 (patch) | |
| tree | 48df6f0a804b3c9a930fa14e6590f3a81a7c6614 /drivers/gpu/drm/i915/display/intel_psr.c | |
| parent | cdb015a61190060094152ff8ff6c6f34b616c13c (diff) | |
| download | linux-f389e7ac8d8a9a17bf59507d02ffb756c19b4af5.tar.xz | |
drm/i915/psr: Add helpers for block count number handling
Add helpers to make it more clear how PSR2_CTL[Block Count Number]
is configured.
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230329150703.432072-5-jouni.hogander@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 98f48eb10c44..07b0c016e78a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -519,6 +519,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) return val; } +static int psr2_block_count_lines(struct intel_dp *intel_dp) +{ + return intel_dp->psr.io_wake_lines < 9 && + intel_dp->psr.fast_wake_lines < 9 ? 8 : 12; +} + +static int psr2_block_count(struct intel_dp *intel_dp) +{ + return psr2_block_count_lines(intel_dp) / 4; +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -536,11 +547,10 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= intel_psr2_get_tp_time(intel_dp); if (DISPLAY_VER(dev_priv) >= 12) { - if (intel_dp->psr.io_wake_lines < 9 && - intel_dp->psr.fast_wake_lines < 9) - val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; - else + if (psr2_block_count(intel_dp) > 2) val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; + else + val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2; } /* Wa_22012278275:adl-p */ |