diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-12-01 18:25:47 +0300 |
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committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-01-20 20:35:01 +0300 |
commit | 27535f1d94318f34fd6d41fd01bfa4a970e73bd9 (patch) | |
tree | ea202b7016e92329519dde2219520a92e8a06765 /drivers/gpu/drm/i915/display/intel_sprite.c | |
parent | c26962803d044a7668e9ea4d5313117ac5b878c8 (diff) | |
download | linux-27535f1d94318f34fd6d41fd01bfa4a970e73bd9.tar.xz |
drm/i915: Clean up vlv/chv sprite plane registers
Use REG_BIT() & co. to polish the vlv/chv sprite plane registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211201152552.7821-10-ville.syrjala@linux.intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_sprite.c')
-rw-r--r-- | drivers/gpu/drm/i915/display/intel_sprite.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 9c231567bd91..7ffca5669ab9 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -313,7 +313,7 @@ static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) u32 sprctl = 0; if (crtc_state->gamma_enable) - sprctl |= SP_GAMMA_ENABLE; + sprctl |= SP_PIPE_GAMMA_ENABLE; return sprctl; } @@ -436,9 +436,9 @@ vlv_sprite_update_noarm(struct intel_plane *plane, intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), plane_state->view.color_plane[0].mapping_stride); intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), - (crtc_y << 16) | crtc_x); + SP_POS_Y(crtc_y) | SP_POS_X(crtc_x)); intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), - ((crtc_h - 1) << 16) | (crtc_w - 1)); + SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1)); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -479,7 +479,8 @@ vlv_sprite_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); - intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), + SP_OFFSET_Y(y) | SP_OFFSET_X(x)); /* * The control register self-arms if the plane was previously |