diff options
| author | Jani Nikula <jani.nikula@intel.com> | 2023-09-05 20:11:27 +0300 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2023-09-11 18:35:16 +0300 |
| commit | 30c220a6fdd8883d4167fb09e18aa448f23ae62a (patch) | |
| tree | 6d4de846b68586ed7a65e12399975680ff9bf603 /drivers/gpu/drm/i915/display/intel_vdsc_regs.h | |
| parent | 051da77ed577d117b329bb62467f09700aedf998 (diff) | |
| download | linux-30c220a6fdd8883d4167fb09e18aa448f23ae62a.tar.xz | |
drm/i915/dsc: use REG_BIT, REG_GENMASK, and friends for PPS0 and PPS1
Use the register helper macros for PPS0 and PPS1 register contents.
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/0dfebe37a391a5ceb8bfae8e16383f1e5aef815d.1693933849.git.jani.nikula@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_vdsc_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 92782de2b309..64f440fdc22b 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -73,22 +73,25 @@ #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) /* PPS 0 */ -#define DSC_PPS0_NATIVE_422_ENABLE BIT(23) -#define DSC_PPS0_NATIVE_420_ENABLE BIT(22) -#define DSC_PPS0_ALT_ICH_SEL (1 << 20) -#define DSC_PPS0_VBR_ENABLE (1 << 19) -#define DSC_PPS0_422_ENABLE (1 << 18) -#define DSC_PPS0_COLOR_SPACE_CONVERSION (1 << 17) -#define DSC_PPS0_BLOCK_PREDICTION (1 << 16) -#define DSC_PPS0_LINE_BUF_DEPTH_SHIFT 12 +#define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23) +#define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22) +#define DSC_PPS0_ALT_ICH_SEL REG_BIT(20) +#define DSC_PPS0_VBR_ENABLE REG_BIT(19) +#define DSC_PPS0_422_ENABLE REG_BIT(18) +#define DSC_PPS0_COLOR_SPACE_CONVERSION REG_BIT(17) +#define DSC_PPS0_BLOCK_PREDICTION REG_BIT(16) #define DSC_PPS0_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) -#define DSC_PPS0_BPC_SHIFT 8 +#define DSC_PPS0_LINE_BUF_DEPTH(depth) REG_FIELD_PREP(DSC_PPS0_LINE_BUF_DEPTH_MASK, depth) #define DSC_PPS0_BPC_MASK REG_GENMASK(11, 8) -#define DSC_PPS0_VER_MIN_SHIFT 4 -#define DSC_PPS0_VER_MAJ (0x1 << 0) +#define DSC_PPS0_BPC(bpc) REG_FIELD_PREP(DSC_PPS0_BPC_MASK, bpc) +#define DSC_PPS0_VER_MINOR_MASK REG_GENMASK(7, 4) +#define DSC_PPS0_VER_MINOR(minor) REG_FIELD_PREP(DSC_PPS0_VER_MINOR_MASK, minor) +#define DSC_PPS0_VER_MAJOR_MASK REG_GENMASK(3, 0) +#define DSC_PPS0_VER_MAJOR(major) REG_FIELD_PREP(DSC_PPS0_VER_MAJOR_MASK, major) /* PPS 1 */ -#define DSC_PPS1_BPP(bpp) ((bpp) << 0) +#define DSC_PPS1_BPP_MASK REG_GENMASK(9, 0) +#define DSC_PPS1_BPP(bpp) REG_FIELD_PREP(DSC_PPS1_BPP_MASK, bpp) /* PPS 2 */ #define DSC_PPS2_PIC_WIDTH_MASK REG_GENMASK(31, 16) |