diff options
| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2023-08-28 08:43:00 +0300 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2023-09-05 12:17:01 +0300 |
| commit | 8b70b569170407cd7a145b1801120560247e3ccf (patch) | |
| tree | 3da25b826e63f182b3a57001526ea417bebd2758 /drivers/gpu/drm/i915/display/intel_vdsc_regs.h | |
| parent | 961e11ab9f82e7eb0bc2536e3b19f64e4a874d9e (diff) | |
| download | linux-8b70b569170407cd7a145b1801120560247e3ccf.tar.xz | |
drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
We have setup both the read and write functions so we can
move ahead and fill in all the readout state from PPS register
into the crtc_state so we can send it for comparision.
--v2
-Shorten comment to just PPSX rather than having the whole
"Readout PPSX register" [Jani]
-Remove pps_temp reinitialization as its being initialized in
the read function [Jani]
-Use REG_FIELD_GET to readout certain fields of dsc registers
[Jani]
--v9
-Place the masks at a more appropriate place [Ankit]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230828054300.560559-8-suraj.kandpal@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_vdsc_regs.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 4c9a51df4775..5cbcbd9db7b1 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -81,7 +81,9 @@ #define DSC_COLOR_SPACE_CONVERSION (1 << 17) #define DSC_BLOCK_PREDICTION (1 << 16) #define DSC_LINE_BUF_DEPTH_SHIFT 12 +#define DSC_LINE_BUF_DEPTH_MASK REG_GENMASK(15, 12) #define DSC_BPC_SHIFT 8 +#define DSC_BPC_MASK REG_GENMASK(11, 8) #define DSC_VER_MIN_SHIFT 4 #define DSC_VER_MAJ (0x1 << 0) |