diff options
| author | Takashi Iwai <tiwai@suse.de> | 2020-04-24 09:22:16 +0300 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2020-04-24 09:22:55 +0300 |
| commit | 36dbae9945322e660795e73ffc8ed8ae4f25d13d (patch) | |
| tree | 9e444e68380061dccfaa453d1f02cf21c5c986ef /drivers/gpu/drm/i915/display | |
| parent | 14ff6c5546e7d98f8326d9ee7a75b79de9874efb (diff) | |
| parent | 0d283287a42027e8a618bcdf17b79578041ebabd (diff) | |
| download | linux-36dbae9945322e660795e73ffc8ed8ae4f25d13d.tar.xz | |
Merge branch 'topic/nhlt' into for-next
Merge NHLT init cleanup.
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'drivers/gpu/drm/i915/display')
74 files changed, 13114 insertions, 7548 deletions
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index f8e882101396..17cee6f80d8b 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -39,14 +39,14 @@ static inline int header_credits_available(struct drm_i915_private *dev_priv, enum transcoder dsi_trans) { - return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) + return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) >> FREE_HEADER_CREDIT_SHIFT; } static inline int payload_credits_available(struct drm_i915_private *dev_priv, enum transcoder dsi_trans) { - return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) + return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) >> FREE_PLOAD_CREDIT_SHIFT; } @@ -55,7 +55,7 @@ static void wait_for_header_credits(struct drm_i915_private *dev_priv, { if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= MAX_HEADER_CREDIT, 100)) - DRM_ERROR("DSI header credits not released\n"); + drm_err(&dev_priv->drm, "DSI header credits not released\n"); } static void wait_for_payload_credits(struct drm_i915_private *dev_priv, @@ -63,7 +63,7 @@ static void wait_for_payload_credits(struct drm_i915_private *dev_priv, { if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= MAX_PLOAD_CREDIT, 100)) - DRM_ERROR("DSI payload credits not released\n"); + drm_err(&dev_priv->drm, "DSI payload credits not released\n"); } static enum transcoder dsi_port_to_transcoder(enum port port) @@ -97,7 +97,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) dsi->channel = 0; ret = mipi_dsi_dcs_nop(dsi); if (ret < 0) - DRM_ERROR("error sending DCS NOP command\n"); + drm_err(&dev_priv->drm, + "error sending DCS NOP command\n"); } /* wait for header credits to be released */ @@ -109,9 +110,9 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) /* wait for LP TX in progress bit to be cleared */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) & + if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & LPTX_IN_PROGRESS), 20)) - DRM_ERROR("LPTX bit not cleared\n"); + drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); } } @@ -129,14 +130,15 @@ static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, free_credits = payload_credits_available(dev_priv, dsi_trans); if (free_credits < 1) { - DRM_ERROR("Payload credit not available\n"); + drm_err(&dev_priv->drm, + "Payload credit not available\n"); return false; } for (j = 0; j < min_t(u32, len - i, 4); j++) tmp |= *data++ << 8 * j; - I915_WRITE(DSI_CMD_TXPYLD(dsi_trans), tmp); + intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); } return true; @@ -154,11 +156,12 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host, /* check if header credit available */ free_credits = header_credits_available(dev_priv, dsi_trans); if (free_credits < 1) { - DRM_ERROR("send pkt header failed, not enough hdr credits\n"); + drm_err(&dev_priv->drm, + "send pkt header failed, not enough hdr credits\n"); return -1; } - tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans)); + tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); if (pkt.payload) tmp |= PAYLOAD_PRESENT; @@ -175,7 +178,7 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host, tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); - I915_WRITE(DSI_CMD_TXHDR(dsi_trans), tmp); + intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); return 0; } @@ -212,53 +215,55 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) * Program voltage swing and pre-emphasis level values as per * table in BSPEC under DDI buffer programing */ - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); tmp |= SCALING_MODE_SEL(0x2); tmp |= TAP2_DISABLE | TAP3_DISABLE; tmp |= RTERM_SELECT(0x6); - I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); tmp |= SCALING_MODE_SEL(0x2); tmp |= TAP2_DISABLE | TAP3_DISABLE; tmp |= RTERM_SELECT(0x6); - I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); tmp |= SWING_SEL_UPPER(0x2); tmp |= SWING_SEL_LOWER(0x2); tmp |= RCOMP_SCALAR(0x98); - I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); tmp |= SWING_SEL_UPPER(0x2); tmp |= SWING_SEL_LOWER(0x2); tmp |= RCOMP_SCALAR(0x98); - I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); tmp |= POST_CURSOR_1(0x0); tmp |= POST_CURSOR_2(0x0); tmp |= CURSOR_COEFF(0x3f); - I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); for (lane = 0; lane <= 3; lane++) { /* Bspec: must not use GRP register for write */ - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); + tmp = intel_de_read(dev_priv, + ICL_PORT_TX_DW4_LN(lane, phy)); tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); tmp |= POST_CURSOR_1(0x0); tmp |= POST_CURSOR_2(0x0); tmp |= CURSOR_COEFF(0x3f); - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); + intel_de_write(dev_priv, + ICL_PORT_TX_DW4_LN(lane, phy), tmp); } } } @@ -270,7 +275,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); u32 dss_ctl1; - dss_ctl1 = I915_READ(DSS_CTL1); + dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); dss_ctl1 |= SPLITTER_ENABLE; dss_ctl1 &= ~OVERLAP_PIXELS_MASK; dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); @@ -286,20 +291,21 @@ static void configure_dual_link_mode(struct intel_encoder *encoder, dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) - DRM_ERROR("DL buffer depth exceed max value\n"); + drm_err(&dev_priv->drm, + "DL buffer depth exceed max value\n"); dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); - dss_ctl2 = I915_READ(DSS_CTL2); + dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); - I915_WRITE(DSS_CTL2, dss_ctl2); + intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); } else { /* Interleave */ dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; } - I915_WRITE(DSS_CTL1, dss_ctl1); + intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); } /* aka DSI 8X clock */ @@ -330,15 +336,15 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(ICL_DSI_ESC_CLK_DIV(port), - esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); - POSTING_READ(ICL_DSI_ESC_CLK_DIV(port)); + intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), + esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); + intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); } for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port), - esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); - POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port)); + intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), + esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); + intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); } } @@ -348,7 +354,7 @@ static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, enum port port; for_each_dsi_port(port, intel_dsi->ports) { - WARN_ON(intel_dsi->io_wakeref[port]); + drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); intel_dsi->io_wakeref[port] = intel_display_power_get(dev_priv, port == PORT_A ? @@ -365,9 +371,9 @@ static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) u32 tmp; for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); + tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); tmp |= COMBO_PHY_MODE_DSI; - I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); + intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); } get_dsi_io_power_domains(dev_priv, intel_dsi); @@ -394,40 +400,46 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) /* Step 4b(i) set loadgen select for transmit and aux lanes */ for_each_dsi_phy(phy, intel_dsi->phys) { - tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); tmp &= ~LOADGEN_SELECT; - I915_WRITE(ICL_PORT_TX_DW4_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); for (lane = 0; lane <= 3; lane++) { - tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); + tmp = intel_de_read(dev_priv, + ICL_PORT_TX_DW4_LN(lane, phy)); tmp &= ~LOADGEN_SELECT; if (lane != 2) tmp |= LOADGEN_SELECT; - I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); + intel_de_write(dev_priv, + ICL_PORT_TX_DW4_LN(lane, phy), tmp); } } /* Step 4b(ii) set latency optimization for transmit and aux lanes */ for_each_dsi_phy(phy, intel_dsi->phys) { - tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); tmp &= ~FRC_LATENCY_OPTIM_MASK; tmp |= FRC_LATENCY_OPTIM_VAL(0x5); - I915_WRITE(ICL_PORT_TX_DW2_AUX(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); + intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); tmp &= ~FRC_LATENCY_OPTIM_MASK; tmp |= FRC_LATENCY_OPTIM_VAL(0x5); - I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); + tmp = intel_de_read(dev_priv, + ICL_PORT_PCS_DW1_AUX(phy)); tmp &= ~LATENCY_OPTIM_MASK; tmp |= LATENCY_OPTIM_VAL(0); - I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), + tmp); - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); + tmp = intel_de_read(dev_priv, + ICL_PORT_PCS_DW1_LN0(phy)); tmp &= ~LATENCY_OPTIM_MASK; tmp |= LATENCY_OPTIM_VAL(0x1); - I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), + tmp); } } @@ -442,12 +454,12 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) /* clear common keeper enable bit */ for_each_dsi_phy(phy, intel_dsi->phys) { - tmp = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); tmp &= ~COMMON_KEEPER_EN; - I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), tmp); - tmp = I915_READ(ICL_PORT_PCS_DW1_AUX(phy)); + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); + tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); tmp &= ~COMMON_KEEPER_EN; - I915_WRITE(ICL_PORT_PCS_DW1_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); } /* @@ -456,19 +468,19 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) * as part of lane phy sequence configuration */ for_each_dsi_phy(phy, intel_dsi->phys) { - tmp = I915_READ(ICL_PORT_CL_DW5(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); tmp |= SUS_CLOCK_CONFIG; - I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); } /* Clear training enable to change swing values */ for_each_dsi_phy(phy, intel_dsi->phys) { - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); tmp &= ~TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); tmp &= ~TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); } /* Program swing and de-emphasis */ @@ -476,12 +488,12 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) /* Set training enable to trigger update */ for_each_dsi_phy(phy, intel_dsi->phys) { - tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); tmp |= TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), tmp); - tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy)); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); + tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); tmp |= TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_AUX(phy), tmp); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); } } @@ -493,14 +505,15 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) enum port port; for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(DDI_BUF_CTL(port)); + tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); tmp |= DDI_BUF_CTL_ENABLE; - I915_WRITE(DDI_BUF_CTL(port), tmp); + intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); - if (wait_for_us(!(I915_READ(DDI_BUF_CTL(port)) & + if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 500)) - DRM_ERROR("DDI port:%c buffer idle\n", port_name(port)); + drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", + port_name(port)); } } @@ -516,28 +529,30 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, /* Program T-INIT master registers */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_DSI_T_INIT_MASTER(port)); + tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); tmp &= ~MASTER_INIT_TIMER_MASK; tmp |= intel_dsi->init_count; - I915_WRITE(ICL_DSI_T_INIT_MASTER(port), tmp); + intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); } /* Program DPHY clock lanes timings */ for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(DPHY_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg); + intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), + intel_dsi->dphy_reg); /* shadow register inside display core */ - I915_WRITE(DSI_CLK_TIMING_PARAM(port), intel_dsi->dphy_reg); + intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), + intel_dsi->dphy_reg); } /* Program DPHY data lanes timings */ for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(DPHY_DATA_TIMING_PARAM(port), - intel_dsi->dphy_data_lane_reg); + intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), + intel_dsi->dphy_data_lane_reg); /* shadow register inside display core */ - I915_WRITE(DSI_DATA_TIMING_PARAM(port), - intel_dsi->dphy_data_lane_reg); + intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), + intel_dsi->dphy_data_lane_reg); } /* @@ -549,25 +564,30 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, if (IS_GEN(dev_priv, 11)) { if (afe_clk(encoder, crtc_state) <= 800000) { for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(DPHY_TA_TIMING_PARAM(port)); + tmp = intel_de_read(dev_priv, + DPHY_TA_TIMING_PARAM(port)); tmp &= ~TA_SURE_MASK; tmp |= TA_SURE_OVERRIDE | TA_SURE(0); - I915_WRITE(DPHY_TA_TIMING_PARAM(port), tmp); + intel_de_write(dev_priv, + DPHY_TA_TIMING_PARAM(port), + tmp); /* shadow register inside display core */ - tmp = I915_READ(DSI_TA_TIMING_PARAM(port)); + tmp = intel_de_read(dev_priv, + DSI_TA_TIMING_PARAM(port)); tmp &= ~TA_SURE_MASK; tmp |= TA_SURE_OVERRIDE | TA_SURE(0); - I915_WRITE(DSI_TA_TIMING_PARAM(port), tmp); + intel_de_write(dev_priv, + DSI_TA_TIMING_PARAM(port), tmp); } } } if (IS_ELKHARTLAKE(dev_priv)) { for_each_dsi_phy(phy, intel_dsi->phys) { - tmp = I915_READ(ICL_DPHY_CHKN(phy)); + tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; - I915_WRITE(ICL_DPHY_CHKN(phy), tmp); + intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); } } } @@ -579,13 +599,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) u32 tmp; enum phy phy; - mutex_lock(&dev_priv->dpll_lock); - tmp = I915_READ(ICL_DPCLKA_CFGCR0); + mutex_lock(&dev_priv->dpll.lock); + tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); for_each_dsi_phy(phy, intel_dsi->phys) tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); - mutex_unlock(&dev_priv->dpll_lock); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); + mutex_unlock(&dev_priv->dpll.lock); } static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) @@ -595,13 +615,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) u32 tmp; enum phy phy; - mutex_lock(&dev_priv->dpll_lock); - tmp = I915_READ(ICL_DPCLKA_CFGCR0); + mutex_lock(&dev_priv->dpll.lock); + tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); for_each_dsi_phy(phy, intel_dsi->phys) tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); - I915_WRITE(ICL_DPCLKA_CFGCR0, tmp); - mutex_unlock(&dev_priv->dpll_lock); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); + mutex_unlock(&dev_priv->dpll.lock); } static void gen11_dsi_map_pll(struct intel_encoder *encoder, @@ -613,14 +633,14 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, enum phy phy; u32 val; - mutex_lock(&dev_priv->dpll_lock); + mutex_lock(&dev_priv->dpll.lock); - val = I915_READ(ICL_DPCLKA_CFGCR0); + val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); for_each_dsi_phy(phy, intel_dsi->phys) { val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); } - I915_WRITE(ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); for_each_dsi_phy(phy, intel_dsi->phys) { if (INTEL_GEN(dev_priv) >= 12) @@ -628,11 +648,11 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, else val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); } - I915_WRITE(ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); - POSTING_READ(ICL_DPCLKA_CFGCR0); + intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); - mutex_unlock(&dev_priv->dpll_lock); + mutex_unlock(&dev_priv->dpll.lock); } static void @@ -649,7 +669,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)); + tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); if (intel_dsi->eotp_pkt) tmp &= ~EOTP_DISABLED; @@ -726,16 +746,18 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, } } - I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp); + intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); } /* enable port sync mode if dual link */ if (intel_dsi->dual_link) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL2(dsi_trans)); tmp |= PORT_SYNC_MODE_ENABLE; - I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); } /* configure stream splitting */ @@ -746,7 +768,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, dsi_trans = dsi_port_to_transcoder(port); /* select data lane width */ - tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); + tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); tmp &= ~DDI_PORT_WIDTH_MASK; tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); @@ -772,15 +794,15 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, /* enable DDI buffer */ tmp |= TRANS_DDI_FUNC_ENABLE; - I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); } /* wait for link ready */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) & - LINK_READY), 2500)) - DRM_ERROR("DSI link not ready\n"); + if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & + LINK_READY), 2500)) + drm_err(&dev_priv->drm, "DSI link not ready\n"); } } @@ -836,17 +858,18 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, /* minimum hactive as per bspec: 256 pixels */ if (adjusted_mode->crtc_hdisplay < 256) - DRM_ERROR("hactive is less then 256 pixels\n"); + drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); /* if RGB666 format, then hactive must be multiple of 4 pixels */ if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) - DRM_ERROR("hactive pixels are not multiple of 4\n"); + drm_err(&dev_priv->drm, + "hactive pixels are not multiple of 4\n"); /* program TRANS_HTOTAL register */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - I915_WRITE(HTOTAL(dsi_trans), - (hactive - 1) | ((htotal - 1) << 16)); + intel_de_write(dev_priv, HTOTAL(dsi_trans), + (hactive - 1) | ((htotal - 1) << 16)); } /* TRANS_HSYNC register to be programmed only for video mode */ @@ -855,11 +878,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { /* BSPEC: hsync size should be atleast 16 pixels */ if (hsync_size < 16) - DRM_ERROR("hsync size < 16 pixels\n"); + drm_err(&dev_priv->drm, + "hsync size < 16 pixels\n"); } if (hback_porch < 16) - DRM_ERROR("hback porch < 16 pixels\n"); + drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); if (intel_dsi->dual_link) { hsync_start /= 2; @@ -868,8 +892,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - I915_WRITE(HSYNC(dsi_trans), - (hsync_start - 1) | ((hsync_end - 1) << 16)); + intel_de_write(dev_priv, HSYNC(dsi_trans), + (hsync_start - 1) | ((hsync_end - 1) << 16)); } } @@ -882,21 +906,21 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, * struct drm_display_mode. * For interlace mode: program required pixel minus 2 */ - I915_WRITE(VTOTAL(dsi_trans), - (vactive - 1) | ((vtotal - 1) << 16)); + intel_de_write(dev_priv, VTOTAL(dsi_trans), + (vactive - 1) | ((vtotal - 1) << 16)); } if (vsync_end < vsync_start || vsync_end > vtotal) - DRM_ERROR("Invalid vsync_end value\n"); + drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); if (vsync_start < vactive) - DRM_ERROR("vsync_start less than vactive\n"); + drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); /* program TRANS_VSYNC register */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - I915_WRITE(VSYNC(dsi_trans), - (vsync_start - 1) | ((vsync_end - 1) << 16)); + intel_de_write(dev_priv, VSYNC(dsi_trans), + (vsync_start - 1) | ((vsync_end - 1) << 16)); } /* @@ -907,15 +931,15 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - I915_WRITE(VSYNCSHIFT(dsi_trans), vsync_shift); + intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), vsync_shift); } /* program TRANS_VBLANK register, should be same as vtotal programmed */ if (INTEL_GEN(dev_priv) >= 12) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - I915_WRITE(VBLANK(dsi_trans), - (vactive - 1) | ((vtotal - 1) << 16)); + intel_de_write(dev_priv, VBLANK(dsi_trans), + (vactive - 1) | ((vtotal - 1) << 16)); } } } @@ -930,14 +954,15 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = I915_READ(PIPECONF(dsi_trans)); + tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); tmp |= PIPECONF_ENABLE; - I915_WRITE(PIPECONF(dsi_trans), tmp); + intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); /* wait for transcoder to be enabled */ if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), I965_PIPECONF_ACTIVE, 10)) - DRM_ERROR("DSI transcoder not enabled\n"); + drm_err(&dev_priv->drm, + "DSI transcoder not enabled\n"); } } @@ -968,26 +993,26 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, dsi_trans = dsi_port_to_transcoder(port); /* program hst_tx_timeout */ - tmp = I915_READ(DSI_HSTX_TO(dsi_trans)); + tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); tmp &= ~HSTX_TIMEOUT_VALUE_MASK; tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); - I915_WRITE(DSI_HSTX_TO(dsi_trans), tmp); + intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); /* FIXME: DSI_CALIB_TO */ /* program lp_rx_host timeout */ - tmp = I915_READ(DSI_LPRX_HOST_TO(dsi_trans)); + tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); tmp &= ~LPRX_TIMEOUT_VALUE_MASK; tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); - I915_WRITE(DSI_LPRX_HOST_TO(dsi_trans), tmp); + intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); /* FIXME: DSI_PWAIT_TO */ /* program turn around timeout */ - tmp = I915_READ(DSI_TA_TO(dsi_trans)); + tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); tmp &= ~TA_TIMEOUT_VALUE_MASK; tmp |= TA_TIMEOUT_VALUE(ta_timeout); - I915_WRITE(DSI_TA_TO(dsi_trans), tmp); + intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); } } @@ -1041,14 +1066,15 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) * FIXME: This uses the number of DW's currently in the payload * receive queue. This is probably not what we want here. */ - tmp = I915_READ(DSI_CMD_RXCTL(dsi_trans)); + tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); tmp &= NUMBER_RX_PLOAD_DW_MASK; /* multiply "Number Rx Payload DW" by 4 to get max value */ tmp = tmp * 4; dsi = intel_dsi->dsi_hosts[port]->device; ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); if (ret < 0) - DRM_ERROR("error setting max return pkt size%d\n", tmp); + drm_err(&dev_priv->drm, + "error setting max return pkt size%d\n", tmp); } /* panel power on related mipi dsi vbt sequences */ @@ -1077,8 +1103,6 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config, const struct drm_connector_state *conn_state) { - struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - /* step3b */ gen11_dsi_map_pll(encoder, pipe_config); @@ -1092,13 +1116,24 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder, /* step6c: configure transcoder timings */ gen11_dsi_set_transcoder_timings(encoder, pipe_config); +} + +static void gen11_dsi_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); + + WARN_ON(crtc_state->has_pch_encoder); /* step6d: enable dsi transcoder */ gen11_dsi_enable_transcoder(encoder); /* step7: enable backlight */ - intel_panel_enable_backlight(pipe_config, conn_state); + intel_panel_enable_backlight(crtc_state, conn_state); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); + + intel_crtc_vblank_on(crtc_state); } static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) @@ -1113,14 +1148,15 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) dsi_trans = dsi_port_to_transcoder(port); /* disable transcoder */ - tmp = I915_READ(PIPECONF(dsi_trans)); + tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); tmp &= ~PIPECONF_ENABLE; - I915_WRITE(PIPECONF(dsi_trans), tmp); + intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); /* wait for transcoder to be disabled */ if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), I965_PIPECONF_ACTIVE, 50)) - DRM_ERROR("DSI trancoder not disabled\n"); + drm_err(&dev_priv->drm, + "DSI trancoder not disabled\n"); } } @@ -1147,32 +1183,34 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) /* put dsi link in ULPS */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = I915_READ(DSI_LP_MSG(dsi_trans)); + tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); tmp |= LINK_ENTER_ULPS; tmp &= ~LINK_ULPS_TYPE_LP11; - I915_WRITE(DSI_LP_MSG(dsi_trans), tmp); + intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); - if (wait_for_us((I915_READ(DSI_LP_MSG(dsi_trans)) & - LINK_IN_ULPS), + if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & + LINK_IN_ULPS), 10)) - DRM_ERROR("DSI link not in ULPS\n"); + drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); } /* disable ddi function */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); + tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); tmp &= ~TRANS_DDI_FUNC_ENABLE; - I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); } /* disable port sync mode if dual link */ if (intel_dsi->dual_link) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL2(dsi_trans)); tmp &= ~PORT_SYNC_MODE_ENABLE; - I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); } } } @@ -1186,15 +1224,16 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder) gen11_dsi_ungate_clocks(encoder); for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(DDI_BUF_CTL(port)); + tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); tmp &= ~DDI_BUF_CTL_ENABLE; - I915_WRITE(DDI_BUF_CTL(port), tmp); + intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); - if (wait_for_us((I915_READ(DDI_BUF_CTL(port)) & + if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), 8)) - DRM_ERROR("DDI port:%c buffer not idle\n", - port_name(port)); + drm_err(&dev_priv->drm, + "DDI port:%c buffer not idle\n", + port_name(port)); } gen11_dsi_gate_clocks(encoder); } @@ -1219,9 +1258,9 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) /* set mode to DDI */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(ICL_DSI_IO_MODECTL(port)); + tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); tmp &= ~COMBO_PHY_MODE_DSI; - I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp); + intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); } } @@ -1311,15 +1350,15 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder, static void gen11_dsi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); intel_dsc_get_config(encoder, pipe_config); /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ - pipe_config->port_clock = - cnl_calc_wrpll_link(dev_priv, &pipe_config->dpll_hw_state); + pipe_config->port_clock = intel_dpll_get_freq(i915, + pipe_config->shared_dpll); pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; if (intel_dsi->dual_link) @@ -1357,11 +1396,13 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, return ret; /* DSI specific sanity checks on the common code */ - WARN_ON(vdsc_cfg->vbr_enable); - WARN_ON(vdsc_cfg->simple_422); - WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width); - WARN_ON(vdsc_cfg->slice_height < 8); - WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height); + drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); + drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); + drm_WARN_ON(&dev_priv->drm, + vdsc_cfg->pic_width % vdsc_cfg->slice_width); + drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); + drm_WARN_ON(&dev_priv->drm, + vdsc_cfg->pic_height % vdsc_cfg->slice_height); ret = drm_dsc_compute_rc_parameters(vdsc_cfg); if (ret) @@ -1443,7 +1484,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans)); + tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { case TRANS_DDI_EDP_INPUT_A_ON: *pipe = PIPE_A; @@ -1458,11 +1499,11 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, *pipe = PIPE_D; break; default: - DRM_ERROR("Invalid PIPE input\n"); + drm_err(&dev_priv->drm, "Invalid PIPE input\n"); goto out; } - tmp = I915_READ(PIPECONF(dsi_trans)); + tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); ret = tmp & PIPECONF_ENABLE; } out: @@ -1582,7 +1623,8 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) */ prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); if (prepare_cnt > ICL_PREPARE_CNT_MAX) { - DRM_DEBUG_KMS("prepare_cnt out of range (%d)\n", prepare_cnt); + drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", + prepare_cnt); prepare_cnt = ICL_PREPARE_CNT_MAX; } @@ -1590,28 +1632,33 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - ths_prepare_ns, tlpx_ns); if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("clk_zero_cnt out of range (%d)\n", clk_zero_cnt); + drm_dbg_kms(&dev_priv->drm, + "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; } /* trail cnt in escape clocks*/ trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); if (trail_cnt > ICL_TRAIL_CNT_MAX) { - DRM_DEBUG_KMS("trail_cnt out of range (%d)\n", trail_cnt); + drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", + trail_cnt); trail_cnt = ICL_TRAIL_CNT_MAX; } /* tclk pre count in escape clocks */ tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { - DRM_DEBUG_KMS("tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); + drm_dbg_kms(&dev_priv->drm, + "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; } /* tclk post count in escape clocks */ tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { - DRM_DEBUG_KMS("tclk_post_cnt out of range (%d)\n", tclk_post_cnt); + drm_dbg_kms(&dev_priv->drm, + "tclk_post_cnt out of range (%d)\n", + tclk_post_cnt); tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; } @@ -1619,14 +1666,17 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi) hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - ths_prepare_ns, tlpx_ns); if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("hs_zero_cnt out of range (%d)\n", hs_zero_cnt); + drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", + hs_zero_cnt); hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; } /* hs exit zero cnt in escape clocks */ exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("exit_zero_cnt out of range (%d)\n", exit_zero_cnt); + drm_dbg_kms(&dev_priv->drm, + "exit_zero_cnt out of range (%d)\n", + exit_zero_cnt); exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; } @@ -1668,9 +1718,8 @@ static void icl_dsi_add_properties(struct intel_connector *connector) connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; - connector->base.display_info.panel_orientation = - intel_dsi_get_panel_orientation(connector); - drm_connector_init_panel_orientation_property(&connector->base, + drm_connector_set_panel_orientation_with_quirk(&connector->base, + intel_dsi_get_panel_orientation(connector), connector->panel.fixed_mode->hdisplay, connector->panel.fixed_mode->vdisplay); } @@ -1708,6 +1757,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; encoder->pre_enable = gen11_dsi_pre_enable; + encoder->enable = gen11_dsi_enable; encoder->disable = gen11_dsi_disable; encoder->post_disable = gen11_dsi_post_disable; encoder->port = port; @@ -1738,7 +1788,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) mutex_unlock(&dev->mode_config.mutex); if (!fixed_mode) { - DRM_ERROR("DSI fixed mode info missing\n"); + drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); goto err; } @@ -1764,7 +1814,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) } if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { - DRM_DEBUG_KMS("no device found\n"); + drm_dbg_kms(&dev_priv->drm, "no device found\n"); goto err; } diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index 3456d33feb46..e21fb14d5e07 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -10,6 +10,7 @@ #include "i915_drv.h" #include "intel_acpi.h" +#include "intel_display_types.h" #define INTEL_DSM_REVISION_ID 1 /* For Calpella anyway... */ #define INTEL_DSM_FN_PLATFORM_MUX_INFO 1 /* No args */ @@ -156,3 +157,91 @@ void intel_register_dsm_handler(void) void intel_unregister_dsm_handler(void) { } + +/* + * ACPI Specification, Revision 5.0, Appendix B.3.2 _DOD (Enumerate All Devices + * Attached to the Display Adapter). + */ +#define ACPI_DISPLAY_INDEX_SHIFT 0 +#define ACPI_DISPLAY_INDEX_MASK (0xf << 0) +#define ACPI_DISPLAY_PORT_ATTACHMENT_SHIFT 4 +#define ACPI_DISPLAY_PORT_ATTACHMENT_MASK (0xf << 4) +#define ACPI_DISPLAY_TYPE_SHIFT 8 +#define ACPI_DISPLAY_TYPE_MASK (0xf << 8) +#define ACPI_DISPLAY_TYPE_OTHER (0 << 8) +#define ACPI_DISPLAY_TYPE_VGA (1 << 8) +#define ACPI_DISPLAY_TYPE_TV (2 << 8) +#define ACPI_DISPLAY_TYPE_EXTERNAL_DIGITAL (3 << 8) +#define ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL (4 << 8) +#define ACPI_VENDOR_SPECIFIC_SHIFT 12 +#define ACPI_VENDOR_SPECIFIC_MASK (0xf << 12) +#define ACPI_BIOS_CAN_DETECT (1 << 16) +#define ACPI_DEPENDS_ON_VGA (1 << 17) +#define ACPI_PIPE_ID_SHIFT 18 +#define ACPI_PIPE_ID_MASK (7 << 18) +#define ACPI_DEVICE_ID_SCHEME (1ULL << 31) + +static u32 acpi_display_type(struct intel_connector *connector) +{ + u32 display_type; + + switch (connector->base.connector_type) { + case DRM_MODE_CONNECTOR_VGA: + case DRM_MODE_CONNECTOR_DVIA: + display_type = ACPI_DISPLAY_TYPE_VGA; + break; + case DRM_MODE_CONNECTOR_Composite: + case DRM_MODE_CONNECTOR_SVIDEO: + case DRM_MODE_CONNECTOR_Component: + case DRM_MODE_CONNECTOR_9PinDIN: + case DRM_MODE_CONNECTOR_TV: + display_type = ACPI_DISPLAY_TYPE_TV; + break; + case DRM_MODE_CONNECTOR_DVII: + case DRM_MODE_CONNECTOR_DVID: + case DRM_MODE_CONNECTOR_DisplayPort: + case DRM_MODE_CONNECTOR_HDMIA: + case DRM_MODE_CONNECTOR_HDMIB: + display_type = ACPI_DISPLAY_TYPE_EXTERNAL_DIGITAL; + break; + case DRM_MODE_CONNECTOR_LVDS: + case DRM_MODE_CONNECTOR_eDP: + case DRM_MODE_CONNECTOR_DSI: + display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL; + break; + case DRM_MODE_CONNECTOR_Unknown: + case DRM_MODE_CONNECTOR_VIRTUAL: + display_type = ACPI_DISPLAY_TYPE_OTHER; + break; + default: + MISSING_CASE(connector->base.connector_type); + display_type = ACPI_DISPLAY_TYPE_OTHER; + break; + } + + return display_type; +} + +void intel_acpi_device_id_update(struct drm_i915_private *dev_priv) +{ + struct drm_device *drm_dev = &dev_priv->drm; + struct intel_connector *connector; + struct drm_connector_list_iter conn_iter; + u8 display_index[16] = {}; + + /* Populate the ACPI IDs for all connectors for a given drm_device */ + drm_connector_list_iter_begin(drm_dev, &conn_iter); + for_each_intel_connector_iter(connector, &conn_iter) { + u32 device_id, type; + + device_id = acpi_display_type(connector); + + /* Use display type specific display index. */ + type = (device_id & ACPI_DISPLAY_TYPE_MASK) + >> ACPI_DISPLAY_TYPE_SHIFT; + device_id |= display_index[type]++ << ACPI_DISPLAY_INDEX_SHIFT; + + connector->acpi_device_id = device_id; + } + drm_connector_list_iter_end(&conn_iter); +} diff --git a/drivers/gpu/drm/i915/display/intel_acpi.h b/drivers/gpu/drm/i915/display/intel_acpi.h index 1c576b3fb712..e8b068661d22 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.h +++ b/drivers/gpu/drm/i915/display/intel_acpi.h @@ -6,12 +6,17 @@ #ifndef __INTEL_ACPI_H__ #define __INTEL_ACPI_H__ +struct drm_i915_private; + #ifdef CONFIG_ACPI void intel_register_dsm_handler(void); void intel_unregister_dsm_handler(void); +void intel_acpi_device_id_update(struct drm_i915_private *i915); #else static inline void intel_register_dsm_handler(void) { return; } static inline void intel_unregister_dsm_handler(void) { return; } +static inline +void intel_acpi_device_id_update(struct drm_i915_private *i915) { return; } #endif /* CONFIG_ACPI */ #endif /* __INTEL_ACPI_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index c362eecdd414..d043057d2fa0 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -35,7 +35,9 @@ #include <drm/drm_plane_helper.h> #include "intel_atomic.h" +#include "intel_cdclk.h" #include "intel_display_types.h" +#include "intel_global_state.h" #include "intel_hdcp.h" #include "intel_psr.h" #include "intel_sprite.h" @@ -64,8 +66,9 @@ int intel_digital_connector_atomic_get_property(struct drm_connector *connector, else if (property == dev_priv->broadcast_rgb_property) *val = intel_conn_state->broadcast_rgb; else { - DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n", - property->base.id, property->name); + drm_dbg_atomic(&dev_priv->drm, + "Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); return -EINVAL; } @@ -101,8 +104,8 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector, return 0; } - DRM_DEBUG_ATOMIC("Unknown property [PROP:%d:%s]\n", - property->base.id, property->name); + drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n", + property->base.id, property->name); return -EINVAL; } @@ -178,6 +181,8 @@ intel_digital_connector_duplicate_state(struct drm_connector *connector) /** * intel_connector_needs_modeset - check if connector needs a modeset + * @state: the atomic state corresponding to this modeset + * @connector: the connector */ bool intel_connector_needs_modeset(struct intel_atomic_state *state, @@ -314,7 +319,8 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta } } - if (WARN(*scaler_id < 0, "Cannot find scaler for %s:%d\n", name, idx)) + if (drm_WARN(&dev_priv->drm, *scaler_id < 0, + "Cannot find scaler for %s:%d\n", name, idx)) return; /* set scaler mode */ @@ -357,8 +363,8 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta mode = SKL_PS_SCALER_MODE_DYN; } - DRM_DEBUG_KMS("Attached scaler id %u.%u to %s:%d\n", - intel_crtc->pipe, *scaler_id, name, idx); + drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n", + intel_crtc->pipe, *scaler_id, name, idx); scaler_state->scalers[*scaler_id].mode = mode; } @@ -409,8 +415,9 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, /* fail if required scalers > available scalers */ if (num_scalers_need > intel_crtc->num_scalers){ - DRM_DEBUG_KMS("Too many scaling requests %d > %d\n", - num_scalers_need, intel_crtc->num_scalers); + drm_dbg_kms(&dev_priv->drm, + "Too many scaling requests %d > %d\n", + num_scalers_need, intel_crtc->num_scalers); return -EINVAL; } @@ -455,8 +462,9 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, plane = drm_plane_from_index(&dev_priv->drm, i); state = drm_atomic_get_plane_state(drm_state, plane); if (IS_ERR(state)) { - DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n", - plane->base.id); + drm_dbg_kms(&dev_priv->drm, + "Failed to add [PLANE:%d] to drm_state\n", + plane->base.id); return PTR_ERR(state); } } @@ -465,7 +473,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, idx = plane->base.id; /* plane on different crtc cannot be a scaler user of this crtc */ - if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) + if (drm_WARN_ON(&dev_priv->drm, + intel_plane->pipe != intel_crtc->pipe)) continue; plane_state = intel_atomic_get_new_plane_state(intel_state, @@ -494,18 +503,28 @@ intel_atomic_state_alloc(struct drm_device *dev) return &state->base; } +void intel_atomic_state_free(struct drm_atomic_state *_state) +{ + struct intel_atomic_state *state = to_intel_atomic_state(_state); + + drm_atomic_state_default_release(&state->base); + kfree(state->global_objs); + + i915_sw_fence_fini(&state->commit_ready); + + kfree(state); +} + void intel_atomic_state_clear(struct drm_atomic_state *s) { struct intel_atomic_state *state = to_intel_atomic_state(s); + drm_atomic_state_default_clear(&state->base); + intel_atomic_clear_global_state(state); + state->dpll_set = state->modeset = false; state->global_state_changed = false; state->active_pipes = 0; - memset(&state->min_cdclk, 0, sizeof(state->min_cdclk)); - memset(&state->min_voltage_level, 0, sizeof(state->min_voltage_level)); - memset(&state->cdclk.logical, 0, sizeof(state->cdclk.logical)); - memset(&state->cdclk.actual, 0, sizeof(state->cdclk.actual)); - state->cdclk.pipe = INVALID_PIPE; } struct intel_crtc_state * @@ -520,7 +539,7 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state, return to_intel_crtc_state(crtc_state); } -int intel_atomic_lock_global_state(struct intel_atomic_state *state) +int _intel_atomic_lock_global_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; @@ -539,7 +558,7 @@ int intel_atomic_lock_global_state(struct intel_atomic_state *state) return 0; } -int intel_atomic_serialize_global_state(struct intel_atomic_state *state) +int _intel_atomic_serialize_global_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h index 74c749dbfb4f..11146292b06f 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.h +++ b/drivers/gpu/drm/i915/display/intel_atomic.h @@ -45,6 +45,7 @@ void intel_crtc_destroy_state(struct drm_crtc *crtc, void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state); void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state); struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev); +void intel_atomic_state_free(struct drm_atomic_state *state); void intel_atomic_state_clear(struct drm_atomic_state *state); struct intel_crtc_state * @@ -55,8 +56,8 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv, struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state); -int intel_atomic_lock_global_state(struct intel_atomic_state *state); +int _intel_atomic_lock_global_state(struct intel_atomic_state *state); -int intel_atomic_serialize_global_state(struct intel_atomic_state *state); +int _intel_atomic_serialize_global_state(struct intel_atomic_state *state); #endif /* __INTEL_ATOMIC_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 3e97af682b1b..457b258683d3 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -37,6 +37,7 @@ #include "i915_trace.h" #include "intel_atomic_plane.h" +#include "intel_cdclk.h" #include "intel_display_types.h" #include "intel_pm.h" #include "intel_sprite.h" @@ -132,15 +133,37 @@ intel_plane_destroy_state(struct drm_plane *plane, kfree(plane_state); } +unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state) +{ + unsigned int src_w, src_h, dst_w, dst_h; + unsigned int pixel_rate = crtc_state->pixel_rate; + + src_w = drm_rect_width(&plane_state->uapi.src) >> 16; + src_h = drm_rect_height(&plane_state->uapi.src) >> 16; + dst_w = drm_rect_width(&plane_state->uapi.dst); + dst_h = drm_rect_height(&plane_state->uapi.dst); + + /* Downscaling limits the maximum pixel rate */ + dst_w = min(src_w, dst_w); + dst_h = min(src_h, dst_h); + + return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, src_w * src_h), + dst_w * dst_h); +} + unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int cpp; + unsigned int pixel_rate; if (!plane_state->uapi.visible) return 0; + pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); + cpp = fb->format->cpp[0]; /* @@ -152,45 +175,67 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, if (fb->format->is_yuv && fb->format->num_planes > 1) cpp *= 4; - return cpp * crtc_state->pixel_rate; + return pixel_rate * cpp; } -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state, - struct intel_plane *plane) +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state, + struct intel_plane *plane, + bool *need_cdclk_calc) { struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct intel_plane_state *plane_state = intel_atomic_get_new_plane_state(state, plane); struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); - struct intel_crtc_state *crtc_state; + const struct intel_cdclk_state *cdclk_state; + const struct intel_crtc_state *old_crtc_state; + struct intel_crtc_state *new_crtc_state; if (!plane_state->uapi.visible || !plane->min_cdclk) - return false; + return 0; + + old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); + new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + + new_crtc_state->min_cdclk[plane->id] = + plane->min_cdclk(new_crtc_state, plane_state); - crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + /* + * No need to check against the cdclk state if + * the min cdclk for the plane doesn't increase. + * + * Ie. we only ever increase the cdclk due to plane + * requirements. This can reduce back and forth + * display blinking due to constant cdclk changes. + */ + if (new_crtc_state->min_cdclk[plane->id] <= + old_crtc_state->min_cdclk[plane->id]) + return 0; - crtc_state->min_cdclk[plane->id] = - plane->min_cdclk(crtc_state, plane_state); + cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(cdclk_state)) + return PTR_ERR(cdclk_state); /* - * Does the cdclk need to be bumbed up? + * No need to recalculate the cdclk state if + * the min cdclk for the pipe doesn't increase. * - * Note: we obviously need to be called before the new - * cdclk frequency is calculated so state->cdclk.logical - * hasn't been populated yet. Hence we look at the old - * cdclk state under dev_priv->cdclk.logical. This is - * safe as long we hold at least one crtc mutex (which - * must be true since we have crtc_state). + * Ie. we only ever increase the cdclk due to plane + * requirements. This can reduce back and forth + * display blinking due to constant cdclk changes. */ - if (crtc_state->min_cdclk[plane->id] > dev_priv->cdclk.logical.cdclk) { - DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n", - plane->base.base.id, plane->base.name, - crtc_state->min_cdclk[plane->id], - dev_priv->cdclk.logical.cdclk); - return true; - } + if (new_crtc_state->min_cdclk[plane->id] <= + cdclk_state->min_cdclk[crtc->pipe]) + return 0; + + drm_dbg_kms(&dev_priv->drm, + "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", + plane->base.base.id, plane->base.name, + new_crtc_state->min_cdclk[plane->id], + crtc->base.base.id, crtc->base.name, + cdclk_state->min_cdclk[crtc->pipe]); + *need_cdclk_calc = true; - return false; + return 0; } static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state) @@ -225,12 +270,9 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ struct intel_plane_state *new_plane_state) { struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); - const struct drm_framebuffer *fb; + const struct drm_framebuffer *fb = new_plane_state->hw.fb; int ret; - intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state); - fb = new_plane_state->hw.fb; - new_crtc_state->active_planes &= ~BIT(plane->id); new_crtc_state->nv12_planes &= ~BIT(plane->id); new_crtc_state->c8_planes &= ~BIT(plane->id); @@ -292,6 +334,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, const struct intel_crtc_state *old_crtc_state; struct intel_crtc_state *new_crtc_state; + intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state); new_plane_state->uapi.visible = false; if (!crtc) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 5cedafdddb55..a6bbf42bae1f 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -18,6 +18,9 @@ struct intel_plane_state; extern const struct drm_plane_helper_funcs intel_plane_helper_funcs; +unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state); + unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state); void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, @@ -46,7 +49,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat struct intel_crtc_state *crtc_state, const struct intel_plane_state *old_plane_state, struct intel_plane_state *plane_state); -bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state, - struct intel_plane *plane); +int intel_plane_calc_min_cdclk(struct intel_atomic_state *state, + struct intel_plane *plane, + bool *need_cdclk_calc); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index b18040793d9e..62f234f641de 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -30,6 +30,7 @@ #include "i915_drv.h" #include "intel_atomic.h" #include "intel_audio.h" +#include "intel_cdclk.h" #include "intel_display_types.h" #include "intel_lpe_audio.h" @@ -148,6 +149,10 @@ static const struct { { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, + { 296703, AUD_CONFIG_PIXEL_CLOCK_HDMI_296703 }, + { 297000, AUD_CONFIG_PIXEL_CLOCK_HDMI_297000 }, + { 593407, AUD_CONFIG_PIXEL_CLOCK_HDMI_593407 }, + { 594000, AUD_CONFIG_PIXEL_CLOCK_HDMI_594000 }, }; /* HDMI N/CTS table */ @@ -233,6 +238,7 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) { + struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int i; @@ -242,6 +248,9 @@ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_sta break; } + if (INTEL_GEN(dev_priv) < 12 && adjusted_mode->crtc_clock > 148500) + i = ARRAY_SIZE(hdmi_audio_clock); + if (i == ARRAY_SIZE(hdmi_audio_clock)) { DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", adjusted_mode->crtc_clock); @@ -291,18 +300,18 @@ static bool intel_eld_uptodate(struct drm_connector *connector, u32 tmp; int i; - tmp = I915_READ(reg_eldv); + tmp = intel_de_read(dev_priv, reg_eldv); tmp &= bits_eldv; if (!tmp) return false; - tmp = I915_READ(reg_elda); + tmp = intel_de_read(dev_priv, reg_elda); tmp &= ~bits_elda; - I915_WRITE(reg_elda, tmp); + intel_de_write(dev_priv, reg_elda, tmp); for (i = 0; i < drm_eld_size(eld) / 4; i++) - if (I915_READ(reg_edid) != *((const u32 *)eld + i)) + if (intel_de_read(dev_priv, reg_edid) != *((const u32 *)eld + i)) return false; return true; @@ -315,18 +324,18 @@ static void g4x_audio_codec_disable(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 eldv, tmp; - DRM_DEBUG_KMS("Disable audio codec\n"); + drm_dbg_kms(&dev_priv->drm, "Disable audio codec\n"); - tmp = I915_READ(G4X_AUD_VID_DID); + tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) eldv = G4X_ELDV_DEVCL_DEVBLC; else eldv = G4X_ELDV_DEVCTG; /* Invalidate ELD */ - tmp = I915_READ(G4X_AUD_CNTL_ST); + tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); tmp &= ~eldv; - I915_WRITE(G4X_AUD_CNTL_ST, tmp); + intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); } static void g4x_audio_codec_enable(struct intel_encoder *encoder, @@ -340,9 +349,10 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, u32 tmp; int len, i; - DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld)); + drm_dbg_kms(&dev_priv->drm, "Enable audio codec, %u bytes ELD\n", + drm_eld_size(eld)); - tmp = I915_READ(G4X_AUD_VID_DID); + tmp = intel_de_read(dev_priv, G4X_AUD_VID_DID); if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) eldv = G4X_ELDV_DEVCL_DEVBLC; else @@ -354,19 +364,20 @@ static void g4x_audio_codec_enable(struct intel_encoder *encoder, G4X_HDMIW_HDMIEDID)) return; - tmp = I915_READ(G4X_AUD_CNTL_ST); + tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); tmp &= ~(eldv | G4X_ELD_ADDR_MASK); len = (tmp >> 9) & 0x1f; /* ELD buffer size */ - I915_WRITE(G4X_AUD_CNTL_ST, tmp); + intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); len = min(drm_eld_size(eld) / 4, len); - DRM_DEBUG_DRIVER("ELD size %d\n", len); + drm_dbg(&dev_priv->drm, "ELD size %d\n", len); for (i = 0; i < len; i++) - I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i)); + intel_de_write(dev_priv, G4X_HDMIW_HDMIEDID, + *((const u32 *)eld + i)); - tmp = I915_READ(G4X_AUD_CNTL_ST); + tmp = intel_de_read(dev_priv, G4X_AUD_CNTL_ST); tmp |= eldv; - I915_WRITE(G4X_AUD_CNTL_ST, tmp); + intel_de_write(dev_priv, G4X_AUD_CNTL_ST, tmp); } static void @@ -384,11 +395,12 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder, rate = acomp ? acomp->aud_sample_rate[port] : 0; nm = audio_config_dp_get_n_m(crtc_state, rate); if (nm) - DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n); + drm_dbg_kms(&dev_priv->drm, "using Maud %u, Naud %u\n", nm->m, + nm->n); else - DRM_DEBUG_KMS("using automatic Maud, Naud\n"); + drm_dbg_kms(&dev_priv->drm, "using automatic Maud, Naud\n"); - tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); tmp &= ~AUD_CONFIG_N_VALUE_INDEX; tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; tmp &= ~AUD_CONFIG_N_PROG_ENABLE; @@ -400,9 +412,9 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder, tmp |= AUD_CONFIG_N_PROG_ENABLE; } - I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); + intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); - tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); tmp &= ~AUD_CONFIG_M_MASK; tmp &= ~AUD_M_CTS_M_VALUE_INDEX; tmp &= ~AUD_M_CTS_M_PROG_ENABLE; @@ -413,7 +425,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder, tmp |= AUD_M_CTS_M_PROG_ENABLE; } - I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); + intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); } static void @@ -429,7 +441,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder, rate = acomp ? acomp->aud_sample_rate[port] : 0; - tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); tmp &= ~AUD_CONFIG_N_VALUE_INDEX; tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; tmp &= ~AUD_CONFIG_N_PROG_ENABLE; @@ -437,25 +449,25 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder, n = audio_config_hdmi_get_n(crtc_state, rate); if (n != 0) { - DRM_DEBUG_KMS("using N %d\n", n); + drm_dbg_kms(&dev_priv->drm, "using N %d\n", n); tmp &= ~AUD_CONFIG_N_MASK; tmp |= AUD_CONFIG_N(n); tmp |= AUD_CONFIG_N_PROG_ENABLE; } else { - DRM_DEBUG_KMS("using automatic N\n"); + drm_dbg_kms(&dev_priv->drm, "using automatic N\n"); } - I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); + intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); /* * Let's disable "Enable CTS or M Prog bit" * and let HW calculate the value */ - tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); tmp &= ~AUD_M_CTS_M_PROG_ENABLE; tmp &= ~AUD_M_CTS_M_VALUE_INDEX; - I915_WRITE(HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); + intel_de_write(dev_priv, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); } static void @@ -476,26 +488,26 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder, enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; u32 tmp; - DRM_DEBUG_KMS("Disable audio codec on transcoder %s\n", - transcoder_name(cpu_transcoder)); + drm_dbg_kms(&dev_priv->drm, "Disable audio codec on transcoder %s\n", + transcoder_name(cpu_transcoder)); mutex_lock(&dev_priv->av_mutex); /* Disable timestamps */ - tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder)); tmp &= ~AUD_CONFIG_N_VALUE_INDEX; tmp |= AUD_CONFIG_N_PROG_ENABLE; tmp &= ~AUD_CONFIG_UPPER_N_MASK; tmp &= ~AUD_CONFIG_LOWER_N_MASK; if (intel_crtc_has_dp_encoder(old_crtc_state)) tmp |= AUD_CONFIG_N_VALUE_INDEX; - I915_WRITE(HSW_AUD_CFG(cpu_transcoder), tmp); + intel_de_write(dev_priv, HSW_AUD_CFG(cpu_transcoder), tmp); /* Invalidate ELD */ - tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); + tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder); - I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); + intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); mutex_unlock(&dev_priv->av_mutex); } @@ -511,16 +523,17 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, u32 tmp; int len, i; - DRM_DEBUG_KMS("Enable audio codec on transcoder %s, %u bytes ELD\n", - transcoder_name(cpu_transcoder), drm_eld_size(eld)); + drm_dbg_kms(&dev_priv->drm, + "Enable audio codec on transcoder %s, %u bytes ELD\n", + transcoder_name(cpu_transcoder), drm_eld_size(eld)); mutex_lock(&dev_priv->av_mutex); /* Enable audio presence detect, invalidate ELD */ - tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); + tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); tmp |= AUDIO_OUTPUT_ENABLE(cpu_transcoder); tmp &= ~AUDIO_ELD_VALID(cpu_transcoder); - I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); + intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); /* * FIXME: We're supposed to wait for vblank here, but we have vblanks @@ -530,19 +543,20 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, */ /* Reset ELD write address */ - tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder)); tmp &= ~IBX_ELD_ADDRESS_MASK; - I915_WRITE(HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); + intel_de_write(dev_priv, HSW_AUD_DIP_ELD_CTRL(cpu_transcoder), tmp); /* Up to 84 bytes of hw ELD buffer */ len = min(drm_eld_size(eld), 84); for (i = 0; i < len / 4; i++) - I915_WRITE(HSW_AUD_EDID_DATA(cpu_transcoder), *((const u32 *)eld + i)); + intel_de_write(dev_priv, HSW_AUD_EDID_DATA(cpu_transcoder), + *((const u32 *)eld + i)); /* ELD valid */ - tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); + tmp = intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD); tmp |= AUDIO_ELD_VALID(cpu_transcoder); - I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); + intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp); /* Enable timestamps */ hsw_audio_config_update(encoder, crtc_state); @@ -561,11 +575,12 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder, u32 tmp, eldv; i915_reg_t aud_config, aud_cntrl_st2; - DRM_DEBUG_KMS("Disable audio codec on [ENCODER:%d:%s], pipe %c\n", - encoder->base.base.id, encoder->base.name, - pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, + "Disable audio codec on [ENCODER:%d:%s], pipe %c\n", + encoder->base.base.id, encoder->base.name, + pipe_name(pipe)); - if (WARN_ON(port == PORT_A)) + if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) return; if (HAS_PCH_IBX(dev_priv)) { @@ -580,21 +595,21 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder, } /* Disable timestamps */ - tmp = I915_READ(aud_config); + tmp = intel_de_read(dev_priv, aud_config); tmp &= ~AUD_CONFIG_N_VALUE_INDEX; tmp |= AUD_CONFIG_N_PROG_ENABLE; tmp &= ~AUD_CONFIG_UPPER_N_MASK; tmp &= ~AUD_CONFIG_LOWER_N_MASK; if (intel_crtc_has_dp_encoder(old_crtc_state)) tmp |= AUD_CONFIG_N_VALUE_INDEX; - I915_WRITE(aud_config, tmp); + intel_de_write(dev_priv, aud_config, tmp); eldv = IBX_ELD_VALID(port); /* Invalidate ELD */ - tmp = I915_READ(aud_cntrl_st2); + tmp = intel_de_read(dev_priv, aud_cntrl_st2); tmp &= ~eldv; - I915_WRITE(aud_cntrl_st2, tmp); + intel_de_write(dev_priv, aud_cntrl_st2, tmp); } static void ilk_audio_codec_enable(struct intel_encoder *encoder, @@ -611,11 +626,12 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder, int len, i; i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; - DRM_DEBUG_KMS("Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n", - encoder->base.base.id, encoder->base.name, - pipe_name(pipe), drm_eld_size(eld)); + drm_dbg_kms(&dev_priv->drm, + "Enable audio codec on [ENCODER:%d:%s], pipe %c, %u bytes ELD\n", + encoder->base.base.id, encoder->base.name, + pipe_name(pipe), drm_eld_size(eld)); - if (WARN_ON(port == PORT_A)) + if (drm_WARN_ON(&dev_priv->drm, port == PORT_A)) return; /* @@ -646,27 +662,28 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder, eldv = IBX_ELD_VALID(port); /* Invalidate ELD */ - tmp = I915_READ(aud_cntrl_st2); + tmp = intel_de_read(dev_priv, aud_cntrl_st2); tmp &= ~eldv; - I915_WRITE(aud_cntrl_st2, tmp); + intel_de_write(dev_priv, aud_cntrl_st2, tmp); /* Reset ELD write address */ - tmp = I915_READ(aud_cntl_st); + tmp = intel_de_read(dev_priv, aud_cntl_st); tmp &= ~IBX_ELD_ADDRESS_MASK; - I915_WRITE(aud_cntl_st, tmp); + intel_de_write(dev_priv, aud_cntl_st, tmp); /* Up to 84 bytes of hw ELD buffer */ len = min(drm_eld_size(eld), 84); for (i = 0; i < len / 4; i++) - I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i)); + intel_de_write(dev_priv, hdmiw_hdmiedid, + *((const u32 *)eld + i)); /* ELD valid */ - tmp = I915_READ(aud_cntrl_st2); + tmp = intel_de_read(dev_priv, aud_cntrl_st2); tmp |= eldv; - I915_WRITE(aud_cntrl_st2, tmp); + intel_de_write(dev_priv, aud_cntrl_st2, tmp); /* Enable timestamps */ - tmp = I915_READ(aud_config); + tmp = intel_de_read(dev_priv, aud_config); tmp &= ~AUD_CONFIG_N_VALUE_INDEX; tmp &= ~AUD_CONFIG_N_PROG_ENABLE; tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; @@ -674,7 +691,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder, tmp |= AUD_CONFIG_N_VALUE_INDEX; else tmp |= audio_config_hdmi_pixel_clock(crtc_state); - I915_WRITE(aud_config, tmp); + intel_de_write(dev_priv, aud_config, tmp); } /** @@ -701,14 +718,15 @@ void intel_audio_codec_enable(struct intel_encoder *encoder, /* FIXME precompute the ELD in .compute_config() */ if (!connector->eld[0]) - DRM_DEBUG_KMS("Bogus ELD on [CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + drm_dbg_kms(&dev_priv->drm, + "Bogus ELD on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); - DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", - connector->base.id, - connector->name, - encoder->base.base.id, - encoder->base.name); + drm_dbg(&dev_priv->drm, "ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", + connector->base.id, + connector->name, + encoder->base.base.id, + encoder->base.name); connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; @@ -800,37 +818,61 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv) } } +static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state, + struct intel_crtc *crtc, + bool enable) +{ + struct intel_cdclk_state *cdclk_state; + int ret; + + /* need to hold at least one crtc lock for the global state */ + ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx); + if (ret) + return ret; + + cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(cdclk_state)) + return PTR_ERR(cdclk_state); + + cdclk_state->force_min_cdclk_changed = true; + cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0; + + ret = intel_atomic_lock_global_state(&cdclk_state->base); + if (ret) + return ret; + + return drm_atomic_commit(&state->base); +} + static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv, bool enable) { struct drm_modeset_acquire_ctx ctx; struct drm_atomic_state *state; + struct intel_crtc *crtc; int ret; + crtc = intel_get_first_crtc(dev_priv); + if (!crtc) + return; + drm_modeset_acquire_init(&ctx, 0); state = drm_atomic_state_alloc(&dev_priv->drm); - if (WARN_ON(!state)) + if (drm_WARN_ON(&dev_priv->drm, !state)) return; state->acquire_ctx = &ctx; retry: - to_intel_atomic_state(state)->cdclk.force_min_cdclk_changed = true; - to_intel_atomic_state(state)->cdclk.force_min_cdclk = - enable ? 2 * 96000 : 0; - - /* Protects dev_priv->cdclk.force_min_cdclk */ - ret = intel_atomic_lock_global_state(to_intel_atomic_state(state)); - if (!ret) - ret = drm_atomic_commit(state); - + ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), crtc, + enable); if (ret == -EDEADLK) { drm_atomic_state_clear(state); drm_modeset_backoff(&ctx); goto retry; } - WARN_ON(ret); + drm_WARN_ON(&dev_priv->drm, ret); drm_atomic_state_put(state); @@ -850,9 +892,11 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) if (dev_priv->audio_power_refcount++ == 0) { if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { - I915_WRITE(AUD_FREQ_CNTRL, dev_priv->audio_freq_cntrl); - DRM_DEBUG_KMS("restored AUD_FREQ_CNTRL to 0x%x\n", - dev_priv->audio_freq_cntrl); + intel_de_write(dev_priv, AUD_FREQ_CNTRL, + dev_priv->audio_freq_cntrl); + drm_dbg_kms(&dev_priv->drm, + "restored AUD_FREQ_CNTRL to 0x%x\n", + dev_priv->audio_freq_cntrl); } /* Force CDCLK to 2*BCLK as long as we need audio powered. */ @@ -860,9 +904,8 @@ static unsigned long i915_audio_component_get_power(struct device *kdev) glk_force_audio_cdclk(dev_priv, true); if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) - I915_WRITE(AUD_PIN_BUF_CTL, - (I915_READ(AUD_PIN_BUF_CTL) | - AUD_PIN_BUF_ENABLE)); + intel_de_write(dev_priv, AUD_PIN_BUF_CTL, + (intel_de_read(dev_priv, AUD_PIN_BUF_CTL) | AUD_PIN_BUF_ENABLE)); } return ret; @@ -897,15 +940,15 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, * Enable/disable generating the codec wake signal, overriding the * internal logic to generate the codec wake to controller. */ - tmp = I915_READ(HSW_AUD_CHICKENBIT); + tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; - I915_WRITE(HSW_AUD_CHICKENBIT, tmp); + intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); usleep_range(1000, 1500); if (enable) { - tmp = I915_READ(HSW_AUD_CHICKENBIT); + tmp = intel_de_read(dev_priv, HSW_AUD_CHICKENBIT); tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; - I915_WRITE(HSW_AUD_CHICKENBIT, tmp); + intel_de_write(dev_priv, HSW_AUD_CHICKENBIT, tmp); usleep_range(1000, 1500); } @@ -917,7 +960,7 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev) { struct drm_i915_private *dev_priv = kdev_to_i915(kdev); - if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv))) return -ENODEV; return dev_priv->cdclk.hw.cdclk; @@ -940,7 +983,8 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv, /* MST */ if (pipe >= 0) { - if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) + if (drm_WARN_ON(&dev_priv->drm, + pipe >= ARRAY_SIZE(dev_priv->av_enc_map))) return NULL; encoder = dev_priv->av_enc_map[pipe]; @@ -992,7 +1036,8 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port, /* 1. get the pipe */ encoder = get_saved_enc(dev_priv, port, pipe); if (!encoder || !encoder->base.crtc) { - DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); + drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", + port_name(port)); err = -ENODEV; goto unlock; } @@ -1023,7 +1068,8 @@ static int i915_audio_component_get_eld(struct device *kdev, int port, intel_encoder = get_saved_enc(dev_priv, port, pipe); if (!intel_encoder) { - DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port)); + drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n", + port_name(port)); mutex_unlock(&dev_priv->av_mutex); return ret; } @@ -1057,10 +1103,12 @@ static int i915_audio_component_bind(struct device *i915_kdev, struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); int i; - if (WARN_ON(acomp->base.ops || acomp->base.dev)) + if (drm_WARN_ON(&dev_priv->drm, acomp->base.ops || acomp->base.dev)) return -EEXIST; - if (WARN_ON(!device_link_add(hda_kdev, i915_kdev, DL_FLAG_STATELESS))) + if (drm_WARN_ON(&dev_priv->drm, + !device_link_add(hda_kdev, i915_kdev, + DL_FLAG_STATELESS))) return -ENOMEM; drm_modeset_lock_all(&dev_priv->drm); @@ -1119,15 +1167,18 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv) &i915_audio_component_bind_ops, I915_COMPONENT_AUDIO); if (ret < 0) { - DRM_ERROR("failed to add audio component (%d)\n", ret); + drm_err(&dev_priv->drm, + "failed to add audio component (%d)\n", ret); /* continue with reduced functionality */ return; } if (IS_TIGERLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { - dev_priv->audio_freq_cntrl = I915_READ(AUD_FREQ_CNTRL); - DRM_DEBUG_KMS("init value of AUD_FREQ_CNTRL of 0x%x\n", - dev_priv->audio_freq_cntrl); + dev_priv->audio_freq_cntrl = intel_de_read(dev_priv, + AUD_FREQ_CNTRL); + drm_dbg_kms(&dev_priv->drm, + "init value of AUD_FREQ_CNTRL of 0x%x\n", + dev_priv->audio_freq_cntrl); } dev_priv->audio_component_registered = true; diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index ef4017a1baba..839124647202 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -26,7 +26,6 @@ */ #include <drm/drm_dp_helper.h> -#include <drm/i915_drm.h> #include "display/intel_display.h" #include "display/intel_display_types.h" @@ -228,17 +227,20 @@ parse_panel_options(struct drm_i915_private *dev_priv, ret = intel_opregion_get_panel_type(dev_priv); if (ret >= 0) { - WARN_ON(ret > 0xf); + drm_WARN_ON(&dev_priv->drm, ret > 0xf); panel_type = ret; - DRM_DEBUG_KMS("Panel type: %d (OpRegion)\n", panel_type); + drm_dbg_kms(&dev_priv->drm, "Panel type: %d (OpRegion)\n", + panel_type); } else { if (lvds_options->panel_type > 0xf) { - DRM_DEBUG_KMS("Invalid VBT panel type 0x%x\n", - lvds_options->panel_type); + drm_dbg_kms(&dev_priv->drm, + "Invalid VBT panel type 0x%x\n", + lvds_options->panel_type); return; } panel_type = lvds_options->panel_type; - DRM_DEBUG_KMS("Panel type: %d (VBT)\n", panel_type); + drm_dbg_kms(&dev_priv->drm, "Panel type: %d (VBT)\n", + panel_type); } dev_priv->vbt.panel_type = panel_type; @@ -253,15 +255,17 @@ parse_panel_options(struct drm_i915_private *dev_priv, switch (drrs_mode) { case 0: dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; - DRM_DEBUG_KMS("DRRS supported mode is static\n"); + drm_dbg_kms(&dev_priv->drm, "DRRS supported mode is static\n"); break; case 2: dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; - DRM_DEBUG_KMS("DRRS supported mode is seamless\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS supported mode is seamless\n"); break; default: dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; - DRM_DEBUG_KMS("DRRS not supported (VBT input)\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS not supported (VBT input)\n"); break; } } @@ -298,7 +302,8 @@ parse_lfp_panel_dtd(struct drm_i915_private *dev_priv, dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; - DRM_DEBUG_KMS("Found panel mode in BIOS VBT legacy lfp table:\n"); + drm_dbg_kms(&dev_priv->drm, + "Found panel mode in BIOS VBT legacy lfp table:\n"); drm_mode_debug_printmodeline(panel_fixed_mode); fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, @@ -309,8 +314,9 @@ parse_lfp_panel_dtd(struct drm_i915_private *dev_priv, if (fp_timing->x_res == panel_fixed_mode->hdisplay && fp_timing->y_res == panel_fixed_mode->vdisplay) { dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; - DRM_DEBUG_KMS("VBT initial LVDS value %x\n", - dev_priv->vbt.bios_lvds_val); + drm_dbg_kms(&dev_priv->drm, + "VBT initial LVDS value %x\n", + dev_priv->vbt.bios_lvds_val); } } } @@ -329,20 +335,22 @@ parse_generic_dtd(struct drm_i915_private *dev_priv, return; if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) { - DRM_ERROR("GDTD size %u is too small.\n", - generic_dtd->gdtd_size); + drm_err(&dev_priv->drm, "GDTD size %u is too small.\n", + generic_dtd->gdtd_size); return; } else if (generic_dtd->gdtd_size != sizeof(struct generic_dtd_entry)) { - DRM_ERROR("Unexpected GDTD size %u\n", generic_dtd->gdtd_size); + drm_err(&dev_priv->drm, "Unexpected GDTD size %u\n", + generic_dtd->gdtd_size); /* DTD has unknown fields, but keep going */ } num_dtd = (get_blocksize(generic_dtd) - sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size; if (dev_priv->vbt.panel_type >= num_dtd) { - DRM_ERROR("Panel type %d not found in table of %d DTD's\n", - dev_priv->vbt.panel_type, num_dtd); + drm_err(&dev_priv->drm, + "Panel type %d not found in table of %d DTD's\n", + dev_priv->vbt.panel_type, num_dtd); return; } @@ -385,7 +393,8 @@ parse_generic_dtd(struct drm_i915_private *dev_priv, else panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; - DRM_DEBUG_KMS("Found panel mode in BIOS VBT generic dtd table:\n"); + drm_dbg_kms(&dev_priv->drm, + "Found panel mode in BIOS VBT generic dtd table:\n"); drm_mode_debug_printmodeline(panel_fixed_mode); dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; @@ -422,8 +431,9 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv, return; if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { - DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n", - backlight_data->entry_size); + drm_dbg_kms(&dev_priv->drm, + "Unsupported backlight data entry size %u\n", + backlight_data->entry_size); return; } @@ -431,8 +441,9 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv, dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; if (!dev_priv->vbt.backlight.present) { - DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n", - entry->type); + drm_dbg_kms(&dev_priv->drm, + "PWM backlight not present in VBT (type %u)\n", + entry->type); return; } @@ -449,13 +460,14 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv, dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm; dev_priv->vbt.backlight.min_brightness = entry->min_brightness; - DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, " - "active %s, min brightness %u, level %u, controller %u\n", - dev_priv->vbt.backlight.pwm_freq_hz, - dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", - dev_priv->vbt.backlight.min_brightness, - backlight_data->level[panel_type], - dev_priv->vbt.backlight.controller); + drm_dbg_kms(&dev_priv->drm, + "VBT backlight PWM modulation frequency %u Hz, " + "active %s, min brightness %u, level %u, controller %u\n", + dev_priv->vbt.backlight.pwm_freq_hz, + dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", + dev_priv->vbt.backlight.min_brightness, + backlight_data->level[panel_type], + dev_priv->vbt.backlight.controller); } /* Try to find sdvo panel data */ @@ -469,7 +481,8 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv, index = i915_modparams.vbt_sdvo_panel_type; if (index == -2) { - DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n"); + drm_dbg_kms(&dev_priv->drm, + "Ignore SDVO panel mode from BIOS VBT tables.\n"); return; } @@ -495,7 +508,8 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv, dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; - DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n"); + drm_dbg_kms(&dev_priv->drm, + "Found SDVO panel mode in BIOS VBT tables:\n"); drm_mode_debug_printmodeline(panel_fixed_mode); } @@ -540,13 +554,14 @@ parse_general_features(struct drm_i915_private *dev_priv, } else { dev_priv->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; } - DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", - dev_priv->vbt.int_tv_support, - dev_priv->vbt.int_crt_support, - dev_priv->vbt.lvds_use_ssc, - dev_priv->vbt.lvds_ssc_freq, - dev_priv->vbt.display_clock_mode, - dev_priv->vbt.fdi_rx_polarity_inverted); + drm_dbg_kms(&dev_priv->drm, + "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", + dev_priv->vbt.int_tv_support, + dev_priv->vbt.int_crt_support, + dev_priv->vbt.lvds_use_ssc, + dev_priv->vbt.lvds_ssc_freq, + dev_priv->vbt.display_clock_mode, + dev_priv->vbt.fdi_rx_polarity_inverted); } static const struct child_device_config * @@ -568,7 +583,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) * accurate and doesn't have to be, as long as it's not too strict. */ if (!IS_GEN_RANGE(dev_priv, 3, 7)) { - DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); + drm_dbg_kms(&dev_priv->drm, "Skipping SDVO device mapping\n"); return; } @@ -586,14 +601,16 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) if (child->dvo_port != DEVICE_PORT_DVOB && child->dvo_port != DEVICE_PORT_DVOC) { /* skip the incorrect SDVO port */ - DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n"); + drm_dbg_kms(&dev_priv->drm, + "Incorrect SDVO port. Skip it\n"); continue; } - DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on" - " %s port\n", - child->slave_addr, - (child->dvo_port == DEVICE_PORT_DVOB) ? - "SDVOB" : "SDVOC"); + drm_dbg_kms(&dev_priv->drm, + "the SDVO device with slave addr %2x is found on" + " %s port\n", + child->slave_addr, + (child->dvo_port == DEVICE_PORT_DVOB) ? + "SDVOB" : "SDVOC"); mapping = &dev_priv->vbt.sdvo_mappings[child->dvo_port - 1]; if (!mapping->initialized) { mapping->dvo_port = child->dvo_port; @@ -602,28 +619,30 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) mapping->ddc_pin = child->ddc_pin; mapping->i2c_pin = child->i2c_pin; mapping->initialized = 1; - DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", - mapping->dvo_port, - mapping->slave_addr, - mapping->dvo_wiring, - mapping->ddc_pin, - mapping->i2c_pin); + drm_dbg_kms(&dev_priv->drm, + "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", + mapping->dvo_port, mapping->slave_addr, + mapping->dvo_wiring, mapping->ddc_pin, + mapping->i2c_pin); } else { - DRM_DEBUG_KMS("Maybe one SDVO port is shared by " - "two SDVO device.\n"); + drm_dbg_kms(&dev_priv->drm, + "Maybe one SDVO port is shared by " + "two SDVO device.\n"); } if (child->slave2_addr) { /* Maybe this is a SDVO device with multiple inputs */ /* And the mapping info is not added */ - DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this" - " is a SDVO device with multiple inputs.\n"); + drm_dbg_kms(&dev_priv->drm, + "there exists the slave2_addr. Maybe this" + " is a SDVO device with multiple inputs.\n"); } count++; } if (!count) { /* No SDVO device info is found */ - DRM_DEBUG_KMS("No SDVO device info is found in VBT\n"); + drm_dbg_kms(&dev_priv->drm, + "No SDVO device info is found in VBT\n"); } } @@ -664,7 +683,8 @@ parse_driver_features(struct drm_i915_private *dev_priv, } if (bdb->version < 228) { - DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled); + drm_dbg_kms(&dev_priv->drm, "DRRS State Enabled:%d\n", + driver->drrs_enabled); /* * If DRRS is not supported, drrs_type has to be set to 0. * This is because, VBT is configured in such a way that @@ -688,7 +708,7 @@ parse_power_conservation_features(struct drm_i915_private *dev_priv, if (bdb->version < 228) return; - power = find_section(bdb, BDB_LVDS_POWER); + power = find_section(bdb, BDB_LFP_POWER); if (!power) return; @@ -742,8 +762,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv->vbt.edp.rate = DP_LINK_BW_2_7; break; default: - DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n", - edp_link_params->rate); + drm_dbg_kms(&dev_priv->drm, + "VBT has unknown eDP link rate value %u\n", + edp_link_params->rate); break; } @@ -758,8 +779,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv->vbt.edp.lanes = 4; break; default: - DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n", - edp_link_params->lanes); + drm_dbg_kms(&dev_priv->drm, + "VBT has unknown eDP lane count value %u\n", + edp_link_params->lanes); break; } @@ -777,8 +799,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; break; default: - DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", - edp_link_params->preemphasis); + drm_dbg_kms(&dev_priv->drm, + "VBT has unknown eDP pre-emphasis value %u\n", + edp_link_params->preemphasis); break; } @@ -796,8 +819,9 @@ parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; break; default: - DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", - edp_link_params->vswing); + drm_dbg_kms(&dev_priv->drm, + "VBT has unknown eDP voltage swing value %u\n", + edp_link_params->vswing); break; } @@ -824,7 +848,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) psr = find_section(bdb, BDB_PSR); if (!psr) { - DRM_DEBUG_KMS("No PSR BDB found.\n"); + drm_dbg_kms(&dev_priv->drm, "No PSR BDB found.\n"); return; } @@ -851,8 +875,9 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; break; default: - DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n", - psr_table->lines_to_wait); + drm_dbg_kms(&dev_priv->drm, + "VBT has unknown PSR lines to wait %u\n", + psr_table->lines_to_wait); break; } @@ -874,8 +899,9 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv->vbt.psr.tp1_wakeup_time_us = 0; break; default: - DRM_DEBUG_KMS("VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", - psr_table->tp1_wakeup_time); + drm_dbg_kms(&dev_priv->drm, + "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", + psr_table->tp1_wakeup_time); /* fallthrough */ case 2: dev_priv->vbt.psr.tp1_wakeup_time_us = 2500; @@ -893,8 +919,9 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 0; break; default: - DRM_DEBUG_KMS("VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", - psr_table->tp2_tp3_wakeup_time); + drm_dbg_kms(&dev_priv->drm, + "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", + psr_table->tp2_tp3_wakeup_time); /* fallthrough */ case 2: dev_priv->vbt.psr.tp2_tp3_wakeup_time_us = 2500; @@ -1000,12 +1027,12 @@ parse_mipi_config(struct drm_i915_private *dev_priv, */ start = find_section(bdb, BDB_MIPI_CONFIG); if (!start) { - DRM_DEBUG_KMS("No MIPI config BDB found"); + drm_dbg_kms(&dev_priv->drm, "No MIPI config BDB found"); return; } - DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n", - panel_type); + drm_dbg(&dev_priv->drm, "Found MIPI Config block, panel index = %d\n", + panel_type); /* * get hold of the correct configuration block and pps data as per @@ -1220,7 +1247,8 @@ static int get_init_otp_deassert_fragment_len(struct drm_i915_private *dev_priv) const u8 *data = dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; int index, len; - if (WARN_ON(!data || dev_priv->vbt.dsi.seq_version != 1)) + if (drm_WARN_ON(&dev_priv->drm, + !data || dev_priv->vbt.dsi.seq_version != 1)) return 0; /* index = 1 to skip sequence byte */ @@ -1273,7 +1301,8 @@ static void fixup_mipi_sequences(struct drm_i915_private *dev_priv) if (!len) return; - DRM_DEBUG_KMS("Using init OTP fragment to deassert reset\n"); + drm_dbg_kms(&dev_priv->drm, + "Using init OTP fragment to deassert reset\n"); /* Copy the fragment, update seq byte and terminate it */ init_otp = (u8 *)dev_priv->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; @@ -1308,18 +1337,21 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv, sequence = find_section(bdb, BDB_MIPI_SEQUENCE); if (!sequence) { - DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n"); + drm_dbg_kms(&dev_priv->drm, + "No MIPI Sequence found, parsing complete\n"); return; } /* Fail gracefully for forward incompatible sequence block. */ if (sequence->version >= 4) { - DRM_ERROR("Unable to parse MIPI Sequence Block v%u\n", - sequence->version); + drm_err(&dev_priv->drm, + "Unable to parse MIPI Sequence Block v%u\n", + sequence->version); return; } - DRM_DEBUG_DRIVER("Found MIPI sequence block v%u\n", sequence->version); + drm_dbg(&dev_priv->drm, "Found MIPI sequence block v%u\n", + sequence->version); seq_data = find_panel_sequence_block(sequence, panel_type, &seq_size); if (!seq_data) @@ -1336,13 +1368,15 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv, break; if (seq_id >= MIPI_SEQ_MAX) { - DRM_ERROR("Unknown sequence %u\n", seq_id); + drm_err(&dev_priv->drm, "Unknown sequence %u\n", + seq_id); goto err; } /* Log about presence of sequences we won't run. */ if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) - DRM_DEBUG_KMS("Unsupported sequence %u\n", seq_id); + drm_dbg_kms(&dev_priv->drm, + "Unsupported sequence %u\n", seq_id); dev_priv->vbt.dsi.sequence[seq_id] = data + index; @@ -1351,7 +1385,8 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv, else index = goto_next_sequence(data, index, seq_size); if (!index) { - DRM_ERROR("Invalid sequence %u\n", seq_id); + drm_err(&dev_priv->drm, "Invalid sequence %u\n", + seq_id); goto err; } } @@ -1362,7 +1397,7 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv, fixup_mipi_sequences(dev_priv); - DRM_DEBUG_DRIVER("MIPI related VBT parsing complete\n"); + drm_dbg(&dev_priv->drm, "MIPI related VBT parsing complete\n"); return; err: @@ -1387,13 +1422,15 @@ parse_compression_parameters(struct drm_i915_private *i915, if (params) { /* Sanity checks */ if (params->entry_size != sizeof(params->data[0])) { - DRM_DEBUG_KMS("VBT: unsupported compression param entry size\n"); + drm_dbg_kms(&i915->drm, + "VBT: unsupported compression param entry size\n"); return; } block_size = get_blocksize(params); if (block_size < sizeof(*params)) { - DRM_DEBUG_KMS("VBT: expected 16 compression param entries\n"); + drm_dbg_kms(&i915->drm, + "VBT: expected 16 compression param entries\n"); return; } } @@ -1405,12 +1442,14 @@ parse_compression_parameters(struct drm_i915_private *i915, continue; if (!params) { - DRM_DEBUG_KMS("VBT: compression params not available\n"); + drm_dbg_kms(&i915->drm, + "VBT: compression params not available\n"); continue; } if (child->compression_method_cps) { - DRM_DEBUG_KMS("VBT: CPS compression not supported\n"); + drm_dbg_kms(&i915->drm, + "VBT: CPS compression not supported\n"); continue; } @@ -1458,10 +1497,11 @@ static void sanitize_ddc_pin(struct drm_i915_private *dev_priv, p = get_port_by_ddc_pin(dev_priv, info->alternate_ddc_pin); if (p != PORT_NONE) { - DRM_DEBUG_KMS("port %c trying to use the same DDC pin (0x%x) as port %c, " - "disabling port %c DVI/HDMI support\n", - port_name(port), info->alternate_ddc_pin, - port_name(p), port_name(p)); + drm_dbg_kms(&dev_priv->drm, + "port %c trying to use the same DDC pin (0x%x) as port %c, " + "disabling port %c DVI/HDMI support\n", + port_name(port), info->alternate_ddc_pin, + port_name(p), port_name(p)); /* * If we have multiple ports supposedly sharing the @@ -1509,10 +1549,11 @@ static void sanitize_aux_ch(struct drm_i915_private *dev_priv, p = get_port_by_aux_ch(dev_priv, info->alternate_aux_channel); if (p != PORT_NONE) { - DRM_DEBUG_KMS("port %c trying to use the same AUX CH (0x%x) as port %c, " - "disabling port %c DP support\n", - port_name(port), info->alternate_aux_channel, - port_name(p), port_name(p)); + drm_dbg_kms(&dev_priv->drm, + "port %c trying to use the same AUX CH (0x%x) as port %c, " + "disabling port %c DP support\n", + port_name(port), info->alternate_aux_channel, + port_name(p), port_name(p)); /* * If we have multiple ports supposedlt sharing the @@ -1572,8 +1613,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) if (vbt_pin < n_entries && ddc_pin_map[vbt_pin] != 0) return ddc_pin_map[vbt_pin]; - DRM_DEBUG_KMS("Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", - vbt_pin); + drm_dbg_kms(&dev_priv->drm, + "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", + vbt_pin); return 0; } @@ -1624,8 +1666,9 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, info = &dev_priv->vbt.ddi_port_info[port]; if (info->child) { - DRM_DEBUG_KMS("More than one child device for port %c in VBT, using the first.\n", - port_name(port)); + drm_dbg_kms(&dev_priv->drm, + "More than one child device for port %c in VBT, using the first.\n", + port_name(port)); return; } @@ -1636,8 +1679,9 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, is_edp = is_dp && (child->device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); if (port == PORT_A && is_dvi && INTEL_GEN(dev_priv) < 12) { - DRM_DEBUG_KMS("VBT claims port A supports DVI%s, ignoring\n", - is_hdmi ? "/HDMI" : ""); + drm_dbg_kms(&dev_priv->drm, + "VBT claims port A supports DVI%s, ignoring\n", + is_hdmi ? "/HDMI" : ""); is_dvi = false; is_hdmi = false; } @@ -1653,11 +1697,12 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, if (bdb_version >= 209) info->supports_tbt = child->tbt; - DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", - port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, - HAS_LSPCON(dev_priv) && child->lspcon, - info->supports_typec_usb, info->supports_tbt, - devdata->dsc != NULL); + drm_dbg_kms(&dev_priv->drm, + "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", + port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, + HAS_LSPCON(dev_priv) && child->lspcon, + info->supports_typec_usb, info->supports_tbt, + devdata->dsc != NULL); if (is_dvi) { u8 ddc_pin; @@ -1667,9 +1712,10 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, info->alternate_ddc_pin = ddc_pin; sanitize_ddc_pin(dev_priv, port); } else { - DRM_DEBUG_KMS("Port %c has invalid DDC pin %d, " - "sticking to defaults\n", - port_name(port), ddc_pin); + drm_dbg_kms(&dev_priv->drm, + "Port %c has invalid DDC pin %d, " + "sticking to defaults\n", + port_name(port), ddc_pin); } } @@ -1682,9 +1728,10 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, if (bdb_version >= 158) { /* The VBT HDMI level shift values match the table we have. */ u8 hdmi_level_shift = child->hdmi_level_shifter_value; - DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", - port_name(port), - hdmi_level_shift); + drm_dbg_kms(&dev_priv->drm, + "VBT HDMI level shift for port %c: %d\n", + port_name(port), + hdmi_level_shift); info->hdmi_level_shift = hdmi_level_shift; info->hdmi_level_shift_set = true; } @@ -1708,19 +1755,22 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, } if (max_tmds_clock) - DRM_DEBUG_KMS("VBT HDMI max TMDS clock for port %c: %d kHz\n", - port_name(port), max_tmds_clock); + drm_dbg_kms(&dev_priv->drm, + "VBT HDMI max TMDS clock for port %c: %d kHz\n", + port_name(port), max_tmds_clock); info->max_tmds_clock = max_tmds_clock; } /* Parse the I_boost config for SKL and above */ if (bdb_version >= 196 && child->iboost) { info->dp_boost_level = translate_iboost(child->dp_iboost_level); - DRM_DEBUG_KMS("VBT (e)DP boost level for port %c: %d\n", - port_name(port), info->dp_boost_level); + drm_dbg_kms(&dev_priv->drm, + "VBT (e)DP boost level for port %c: %d\n", + port_name(port), info->dp_boost_level); info->hdmi_boost_level = translate_iboost(child->hdmi_iboost_level); - DRM_DEBUG_KMS("VBT HDMI boost level for port %c: %d\n", - port_name(port), info->hdmi_boost_level); + drm_dbg_kms(&dev_priv->drm, + "VBT HDMI boost level for port %c: %d\n", + port_name(port), info->hdmi_boost_level); } /* DP max link rate for CNL+ */ @@ -1740,8 +1790,9 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv, info->dp_max_link_rate = 162000; break; } - DRM_DEBUG_KMS("VBT DP max link rate for port %c: %d\n", - port_name(port), info->dp_max_link_rate); + drm_dbg_kms(&dev_priv->drm, + "VBT DP max link rate for port %c: %d\n", + port_name(port), info->dp_max_link_rate); } info->child = child; @@ -1775,19 +1826,21 @@ parse_general_definitions(struct drm_i915_private *dev_priv, defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); if (!defs) { - DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); + drm_dbg_kms(&dev_priv->drm, + "No general definition block is found, no devices defined.\n"); return; } block_size = get_blocksize(defs); if (block_size < sizeof(*defs)) { - DRM_DEBUG_KMS("General definitions block too small (%u)\n", - block_size); + drm_dbg_kms(&dev_priv->drm, + "General definitions block too small (%u)\n", + block_size); return; } bus_pin = defs->crt_ddc_gmbus_pin; - DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin); + drm_dbg_kms(&dev_priv->drm, "crt_ddc_bus_pin: %d\n", bus_pin); if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) dev_priv->vbt.crt_ddc_pin = bus_pin; @@ -1806,19 +1859,22 @@ parse_general_definitions(struct drm_i915_private *dev_priv, } else { expected_size = sizeof(*child); BUILD_BUG_ON(sizeof(*child) < 39); - DRM_DEBUG_DRIVER("Expected child device config size for VBT version %u not known; assuming %u\n", - bdb->version, expected_size); + drm_dbg(&dev_priv->drm, + "Expected child device config size for VBT version %u not known; assuming %u\n", + bdb->version, expected_size); } /* Flag an error for unexpected size, but continue anyway. */ if (defs->child_dev_size != expected_size) - DRM_ERROR("Unexpected child device config size %u (expected %u for VBT version %u)\n", - defs->child_dev_size, expected_size, bdb->version); + drm_err(&dev_priv->drm, + "Unexpected child device config size %u (expected %u for VBT version %u)\n", + defs->child_dev_size, expected_size, bdb->version); /* The legacy sized child device config is the minimum we need. */ if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { - DRM_DEBUG_KMS("Child device config size %u is too small.\n", - defs->child_dev_size); + drm_dbg_kms(&dev_priv->drm, + "Child device config size %u is too small.\n", + defs->child_dev_size); return; } @@ -1830,8 +1886,9 @@ parse_general_definitions(struct drm_i915_private *dev_priv, if (!child->device_type) continue; - DRM_DEBUG_KMS("Found VBT child device with type 0x%x\n", - child->device_type); + drm_dbg_kms(&dev_priv->drm, + "Found VBT child device with type 0x%x\n", + child->device_type); devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); if (!devdata) @@ -1849,7 +1906,8 @@ parse_general_definitions(struct drm_i915_private *dev_priv, } if (list_empty(&dev_priv->vbt.display_devices)) - DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); + drm_dbg_kms(&dev_priv->drm, + "no child dev is parsed from VBT\n"); } /* Common defaults which may be overridden by VBT. */ @@ -1882,7 +1940,8 @@ init_vbt_defaults(struct drm_i915_private *dev_priv) */ dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev_priv, !HAS_PCH_SPLIT(dev_priv)); - DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq); + drm_dbg_kms(&dev_priv->drm, "Set default to SSC at %d kHz\n", + dev_priv->vbt.lvds_ssc_freq); } /* Defaults to initialize only if there is no VBT. */ @@ -1992,13 +2051,14 @@ static struct vbt_header *oprom_get_vbt(struct drm_i915_private *dev_priv) goto err_unmap_oprom; if (sizeof(struct vbt_header) > size) { - DRM_DEBUG_DRIVER("VBT header incomplete\n"); + drm_dbg(&dev_priv->drm, "VBT header incomplete\n"); goto err_unmap_oprom; } vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); if (vbt_size > size) { - DRM_DEBUG_DRIVER("VBT incomplete (vbt_size overflows)\n"); + drm_dbg(&dev_priv->drm, + "VBT incomplete (vbt_size overflows)\n"); goto err_unmap_oprom; } @@ -2041,7 +2101,8 @@ void intel_bios_init(struct drm_i915_private *dev_priv) INIT_LIST_HEAD(&dev_priv->vbt.display_devices); if (!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv)) { - DRM_DEBUG_KMS("Skipping VBT init due to disabled display.\n"); + drm_dbg_kms(&dev_priv->drm, + "Skipping VBT init due to disabled display.\n"); return; } @@ -2055,13 +2116,14 @@ void intel_bios_init(struct drm_i915_private *dev_priv) vbt = oprom_vbt; - DRM_DEBUG_KMS("Found valid VBT in PCI ROM\n"); + drm_dbg_kms(&dev_priv->drm, "Found valid VBT in PCI ROM\n"); } bdb = get_bdb_header(vbt); - DRM_DEBUG_KMS("VBT signature \"%.*s\", BDB version %d\n", - (int)sizeof(vbt->signature), vbt->signature, bdb->version); + drm_dbg_kms(&dev_priv->drm, + "VBT signature \"%.*s\", BDB version %d\n", + (int)sizeof(vbt->signature), vbt->signature, bdb->version); /* Grab useful general definitions */ parse_general_features(dev_priv, bdb); @@ -2086,7 +2148,8 @@ void intel_bios_init(struct drm_i915_private *dev_priv) out: if (!vbt) { - DRM_INFO("Failed to find VBIOS tables (VBT)\n"); + drm_info(&dev_priv->drm, + "Failed to find VBIOS tables (VBT)\n"); init_vbt_missing_defaults(dev_priv); } @@ -2238,13 +2301,12 @@ bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port por const struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port]; - return port_info->supports_dp || - port_info->supports_dvi || - port_info->supports_hdmi; + return port_info->child; } /* FIXME maybe deal with port A as well? */ - if (WARN_ON(port == PORT_A) || port >= ARRAY_SIZE(port_mapping)) + if (drm_WARN_ON(&dev_priv->drm, + port == PORT_A) || port >= ARRAY_SIZE(port_mapping)) return false; list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node) { @@ -2373,8 +2435,9 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, } else if (dvo_port == DVO_PORT_MIPIB || dvo_port == DVO_PORT_MIPIC || dvo_port == DVO_PORT_MIPID) { - DRM_DEBUG_KMS("VBT has unsupported DSI port %c\n", - port_name(dvo_port - DVO_PORT_MIPIA)); + drm_dbg_kms(&dev_priv->drm, + "VBT has unsupported DSI port %c\n", + port_name(dvo_port - DVO_PORT_MIPIA)); } } @@ -2493,7 +2556,7 @@ intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915, const struct child_device_config *child = i915->vbt.ddi_port_info[port].child; - if (WARN_ON_ONCE(!IS_GEN9_LP(i915))) + if (drm_WARN_ON_ONCE(&i915->drm, !IS_GEN9_LP(i915))) return false; return child && child->hpd_invert; @@ -2526,8 +2589,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, if (!info->alternate_aux_channel) { aux_ch = (enum aux_ch)port; - DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", - aux_ch_name(aux_ch), port_name(port)); + drm_dbg_kms(&dev_priv->drm, + "using AUX %c for port %c (platform default)\n", + aux_ch_name(aux_ch), port_name(port)); return aux_ch; } @@ -2559,8 +2623,78 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, break; } - DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", - aux_ch_name(aux_ch), port_name(port)); + drm_dbg_kms(&dev_priv->drm, "using AUX %c for port %c (VBT)\n", + aux_ch_name(aux_ch), port_name(port)); return aux_ch; } + +int intel_bios_max_tmds_clock(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + return i915->vbt.ddi_port_info[encoder->port].max_tmds_clock; +} + +int intel_bios_hdmi_level_shift(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct ddi_vbt_port_info *info = + &i915->vbt.ddi_port_info[encoder->port]; + + return info->hdmi_level_shift_set ? info->hdmi_level_shift : -1; +} + +int intel_bios_dp_boost_level(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + return i915->vbt.ddi_port_info[encoder->port].dp_boost_level; +} + +int intel_bios_hdmi_boost_level(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + return i915->vbt.ddi_port_info[encoder->port].hdmi_boost_level; +} + +int intel_bios_dp_max_link_rate(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + return i915->vbt.ddi_port_info[encoder->port].dp_max_link_rate; +} + +int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + return i915->vbt.ddi_port_info[encoder->port].alternate_ddc_pin; +} + +bool intel_bios_port_supports_dvi(struct drm_i915_private *i915, enum port port) +{ + return i915->vbt.ddi_port_info[port].supports_dvi; +} + +bool intel_bios_port_supports_hdmi(struct drm_i915_private *i915, enum port port) +{ + return i915->vbt.ddi_port_info[port].supports_hdmi; +} + +bool intel_bios_port_supports_dp(struct drm_i915_private *i915, enum port port) +{ + return i915->vbt.ddi_port_info[port].supports_dp; +} + +bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, + enum port port) +{ + return i915->vbt.ddi_port_info[port].supports_typec_usb; +} + +bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port) +{ + return i915->vbt.ddi_port_info[port].supports_tbt; +} diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h index d6a0c29d37ac..e29e79faa01b 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h @@ -32,8 +32,6 @@ #include <linux/types.h> -#include <drm/i915_drm.h> - struct drm_i915_private; struct intel_crtc_state; struct intel_encoder; @@ -247,5 +245,16 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port bool intel_bios_get_dsc_params(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, int dsc_max_bpc); +int intel_bios_max_tmds_clock(struct intel_encoder *encoder); +int intel_bios_hdmi_level_shift(struct intel_encoder *encoder); +int intel_bios_dp_boost_level(struct intel_encoder *encoder); +int intel_bios_hdmi_boost_level(struct intel_encoder *encoder); +int intel_bios_dp_max_link_rate(struct intel_encoder *encoder); +int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder); +bool intel_bios_port_supports_dvi(struct drm_i915_private *i915, enum port port); +bool intel_bios_port_supports_hdmi(struct drm_i915_private *i915, enum port port); +bool intel_bios_port_supports_dp(struct drm_i915_private *i915, enum port port); +bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port); +bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port); #endif /* _INTEL_BIOS_H_ */ diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index b228671d5a5d..58b264bc318d 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -122,7 +122,8 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, if (ret) return ret; - if (WARN_ON(qi->num_points > ARRAY_SIZE(qi->points))) + if (drm_WARN_ON(&dev_priv->drm, + qi->num_points > ARRAY_SIZE(qi->points))) qi->num_points = ARRAY_SIZE(qi->points); for (i = 0; i < qi->num_points; i++) { @@ -132,9 +133,10 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, if (ret) return ret; - DRM_DEBUG_KMS("QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", - i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras, - sp->t_rcd, sp->t_rc); + drm_dbg_kms(&dev_priv->drm, + "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", + i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras, + sp->t_rcd, sp->t_rc); } return 0; @@ -187,7 +189,8 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel ret = icl_get_qgv_points(dev_priv, &qi); if (ret) { - DRM_DEBUG_KMS("Failed to get memory subsystem information, ignoring bandwidth limits"); + drm_dbg_kms(&dev_priv->drm, + "Failed to get memory subsystem information, ignoring bandwidth limits"); return ret; } num_channels = qi.num_channels; @@ -228,8 +231,9 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel bi->deratedbw[j] = min(maxdebw, bw * 9 / 10); /* 90% */ - DRM_DEBUG_KMS("BW%d / QGV %d: num_planes=%d deratedbw=%u\n", - i, j, bi->num_planes, bi->deratedbw[j]); + drm_dbg_kms(&dev_priv->drm, + "BW%d / QGV %d: num_planes=%d deratedbw=%u\n", + i, j, bi->num_planes, bi->deratedbw[j]); } if (bi->num_planes == 1) @@ -374,10 +378,9 @@ static struct intel_bw_state * intel_atomic_get_bw_state(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct drm_private_state *bw_state; + struct intel_global_state *bw_state; - bw_state = drm_atomic_get_private_obj_state(&state->base, - &dev_priv->bw_obj); + bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj); if (IS_ERR(bw_state)) return ERR_CAST(bw_state); @@ -392,7 +395,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) unsigned int data_rate, max_data_rate; unsigned int num_active_planes; struct intel_crtc *crtc; - int i; + int i, ret; /* FIXME earlier gens need some checks too */ if (INTEL_GEN(dev_priv) < 11) @@ -424,15 +427,20 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) bw_state->data_rate[crtc->pipe] = new_data_rate; bw_state->num_active_planes[crtc->pipe] = new_active_planes; - DRM_DEBUG_KMS("pipe %c data rate %u num active planes %u\n", - pipe_name(crtc->pipe), - bw_state->data_rate[crtc->pipe], - bw_state->num_active_planes[crtc->pipe]); + drm_dbg_kms(&dev_priv->drm, + "pipe %c data rate %u num active planes %u\n", + pipe_name(crtc->pipe), + bw_state->data_rate[crtc->pipe], + bw_state->num_active_planes[crtc->pipe]); } if (!bw_state) return 0; + ret = intel_atomic_lock_global_state(&bw_state->base); + if (ret) + return ret; + data_rate = intel_bw_data_rate(dev_priv, bw_state); num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state); @@ -441,15 +449,17 @@ int intel_bw_atomic_check(struct intel_atomic_state *state) data_rate = DIV_ROUND_UP(data_rate, 1000); if (data_rate > max_data_rate) { - DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n", - data_rate, max_data_rate, num_active_planes); + drm_dbg_kms(&dev_priv->drm, + "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n", + data_rate, max_data_rate, num_active_planes); return -EINVAL; } return 0; } -static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj *obj) +static struct intel_global_state * +intel_bw_duplicate_state(struct intel_global_obj *obj) { struct intel_bw_state *state; @@ -457,18 +467,16 @@ static struct drm_private_state *intel_bw_duplicate_state(struct drm_private_obj if (!state) return NULL; - __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); - return &state->base; } -static void intel_bw_destroy_state(struct drm_private_obj *obj, - struct drm_private_state *state) +static void intel_bw_destroy_state(struct intel_global_obj *obj, + struct intel_global_state *state) { kfree(state); } -static const struct drm_private_state_funcs intel_bw_funcs = { +static const struct intel_global_state_funcs intel_bw_funcs = { .atomic_duplicate_state = intel_bw_duplicate_state, .atomic_destroy_state = intel_bw_destroy_state, }; @@ -481,13 +489,8 @@ int intel_bw_init(struct drm_i915_private *dev_priv) if (!state) return -ENOMEM; - drm_atomic_private_obj_init(&dev_priv->drm, &dev_priv->bw_obj, - &state->base, &intel_bw_funcs); + intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj, + &state->base, &intel_bw_funcs); return 0; } - -void intel_bw_cleanup(struct drm_i915_private *dev_priv) -{ - drm_atomic_private_obj_fini(&dev_priv->bw_obj); -} diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 20b9ad241802..a8aa7624c5aa 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -9,13 +9,14 @@ #include <drm/drm_atomic.h> #include "intel_display.h" +#include "intel_global_state.h" struct drm_i915_private; struct intel_atomic_state; struct intel_crtc_state; struct intel_bw_state { - struct drm_private_state base; + struct intel_global_state base; unsigned int data_rate[I915_MAX_PIPES]; u8 num_active_planes[I915_MAX_PIPES]; @@ -25,7 +26,6 @@ struct intel_bw_state { void intel_bw_init_hw(struct drm_i915_private *dev_priv); int intel_bw_init(struct drm_i915_private *dev_priv); -void intel_bw_cleanup(struct drm_i915_private *dev_priv); int intel_bw_atomic_check(struct intel_atomic_state *state); void intel_bw_crtc_update(struct intel_bw_state *bw_state, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 0ce5926006ca..979a0241fdcb 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -55,43 +55,43 @@ */ static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; } static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; } static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 266667; + cdclk_config->cdclk = 266667; } static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 333333; + cdclk_config->cdclk = 333333; } static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 400000; + cdclk_config->cdclk = 400000; } static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; } static void i85x_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 hpllcc = 0; @@ -102,7 +102,7 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv, * FIXME is this the right way to detect 852GM/852GMV? */ if (pdev->revision == 0x1) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; return; } @@ -116,24 +116,24 @@ static void i85x_get_cdclk(struct drm_i915_private *dev_priv, case GC_CLOCK_133_200: case GC_CLOCK_133_200_2: case GC_CLOCK_100_200: - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; break; case GC_CLOCK_166_250: - cdclk_state->cdclk = 250000; + cdclk_config->cdclk = 250000; break; case GC_CLOCK_100_133: - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; break; case GC_CLOCK_133_266: case GC_CLOCK_133_266_2: case GC_CLOCK_166_266: - cdclk_state->cdclk = 266667; + cdclk_config->cdclk = 266667; break; } } static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -141,23 +141,23 @@ static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, pci_read_config_word(pdev, GCFGC, &gcfgc); if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; return; } switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_333_320_MHZ: - cdclk_state->cdclk = 333333; + cdclk_config->cdclk = 333333; break; default: case GC_DISPLAY_CLOCK_190_200_MHZ: - cdclk_state->cdclk = 190000; + cdclk_config->cdclk = 190000; break; } } static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -165,17 +165,17 @@ static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, pci_read_config_word(pdev, GCFGC, &gcfgc); if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; return; } switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_333_320_MHZ: - cdclk_state->cdclk = 320000; + cdclk_config->cdclk = 320000; break; default: case GC_DISPLAY_CLOCK_190_200_MHZ: - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; break; } } @@ -237,20 +237,21 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) else return 0; - tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? - HPLLVCO_MOBILE : HPLLVCO); + tmp = intel_de_read(dev_priv, + IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); vco = vco_table[tmp & 0x7]; if (vco == 0) - DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); + drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", + tmp); else - DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); + drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); return vco; } static void g33_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 }; @@ -261,7 +262,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, unsigned int cdclk_sel; u16 tmp = 0; - cdclk_state->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(dev_priv); pci_read_config_word(pdev, GCFGC, &tmp); @@ -270,7 +271,7 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, if (cdclk_sel >= ARRAY_SIZE(div_3200)) goto fail; - switch (cdclk_state->vco) { + switch (cdclk_config->vco) { case 3200000: div_table = div_3200; break; @@ -287,18 +288,19 @@ static void g33_get_cdclk(struct drm_i915_private *dev_priv, goto fail; } - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, - div_table[cdclk_sel]); + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, + div_table[cdclk_sel]); return; fail: - DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", - cdclk_state->vco, tmp); - cdclk_state->cdclk = 190476; + drm_err(&dev_priv->drm, + "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", + cdclk_config->vco, tmp); + cdclk_config->cdclk = 190476; } static void pnv_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; u16 gcfgc = 0; @@ -307,31 +309,32 @@ static void pnv_get_cdclk(struct drm_i915_private *dev_priv, switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { case GC_DISPLAY_CLOCK_267_MHZ_PNV: - cdclk_state->cdclk = 266667; + cdclk_config->cdclk = 266667; break; case GC_DISPLAY_CLOCK_333_MHZ_PNV: - cdclk_state->cdclk = 333333; + cdclk_config->cdclk = 333333; break; case GC_DISPLAY_CLOCK_444_MHZ_PNV: - cdclk_state->cdclk = 444444; + cdclk_config->cdclk = 444444; break; case GC_DISPLAY_CLOCK_200_MHZ_PNV: - cdclk_state->cdclk = 200000; + cdclk_config->cdclk = 200000; break; default: - DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); + drm_err(&dev_priv->drm, + "Unknown pnv display core clock 0x%04x\n", gcfgc); /* fall through */ case GC_DISPLAY_CLOCK_133_MHZ_PNV: - cdclk_state->cdclk = 133333; + cdclk_config->cdclk = 133333; break; case GC_DISPLAY_CLOCK_167_MHZ_PNV: - cdclk_state->cdclk = 166667; + cdclk_config->cdclk = 166667; break; } } static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; static const u8 div_3200[] = { 16, 10, 8 }; @@ -341,7 +344,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, unsigned int cdclk_sel; u16 tmp = 0; - cdclk_state->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(dev_priv); pci_read_config_word(pdev, GCFGC, &tmp); @@ -350,7 +353,7 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, if (cdclk_sel >= ARRAY_SIZE(div_3200)) goto fail; - switch (cdclk_state->vco) { + switch (cdclk_config->vco) { case 3200000: div_table = div_3200; break; @@ -364,62 +367,64 @@ static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, goto fail; } - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, - div_table[cdclk_sel]); + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, + div_table[cdclk_sel]); return; fail: - DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", - cdclk_state->vco, tmp); - cdclk_state->cdclk = 200000; + drm_err(&dev_priv->drm, + "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", + cdclk_config->vco, tmp); + cdclk_config->cdclk = 200000; } static void gm45_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { struct pci_dev *pdev = dev_priv->drm.pdev; unsigned int cdclk_sel; u16 tmp = 0; - cdclk_state->vco = intel_hpll_vco(dev_priv); + cdclk_config->vco = intel_hpll_vco(dev_priv); pci_read_config_word(pdev, GCFGC, &tmp); cdclk_sel = (tmp >> 12) & 0x1; - switch (cdclk_state->vco) { + switch (cdclk_config->vco) { case 2666667: case 4000000: case 5333333: - cdclk_state->cdclk = cdclk_sel ? 333333 : 222222; + cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; break; case 3200000: - cdclk_state->cdclk = cdclk_sel ? 320000 : 228571; + cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; break; default: - DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", - cdclk_state->vco, tmp); - cdclk_state->cdclk = 222222; + drm_err(&dev_priv->drm, + "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", + cdclk_config->vco, tmp); + cdclk_config->cdclk = 222222; break; } } static void hsw_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - u32 lcpll = I915_READ(LCPLL_CTL); + u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; if (lcpll & LCPLL_CD_SOURCE_FCLK) - cdclk_state->cdclk = 800000; - else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 800000; + else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) + cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_450) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; else if (IS_HSW_ULT(dev_priv)) - cdclk_state->cdclk = 337500; + cdclk_config->cdclk = 337500; else - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; } static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) @@ -462,17 +467,17 @@ static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) } static void vlv_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 val; vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); - cdclk_state->vco = vlv_get_hpll_vco(dev_priv); - cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", - CCK_DISPLAY_CLOCK_CONTROL, - cdclk_state->vco); + cdclk_config->vco = vlv_get_hpll_vco(dev_priv); + cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", + CCK_DISPLAY_CLOCK_CONTROL, + cdclk_config->vco); val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); @@ -480,10 +485,10 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv, BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT)); if (IS_VALLEYVIEW(dev_priv)) - cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >> + cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> DSPFREQGUAR_SHIFT; else - cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> + cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> DSPFREQGUAR_SHIFT_CHV; } @@ -510,25 +515,26 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) * WA - write default credits before re-programming * FIXME: should we also set the resend bit here? */ - I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | - default_credits); + intel_de_write(dev_priv, GCI_CONTROL, + VGA_FAST_MODE_DISABLE | default_credits); - I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | - credits | PFI_CREDIT_RESEND); + intel_de_write(dev_priv, GCI_CONTROL, + VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND); /* * FIXME is this guaranteed to clear * immediately or should we poll for it? */ - WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); } static void vlv_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - u32 val, cmd = cdclk_state->voltage_level; + int cdclk = cdclk_config->cdclk; + u32 val, cmd = cdclk_config->voltage_level; intel_wakeref_t wakeref; switch (cdclk) { @@ -563,7 +569,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), 50)) { - DRM_ERROR("timed out waiting for CDclk change\n"); + drm_err(&dev_priv->drm, + "timed out waiting for CDclk change\n"); } if (cdclk == 400000) { @@ -581,7 +588,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), 50)) - DRM_ERROR("timed out waiting for CDclk change\n"); + drm_err(&dev_priv->drm, + "timed out waiting for CDclk change\n"); } /* adjust self-refresh exit latency value */ @@ -611,11 +619,11 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, } static void chv_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - u32 val, cmd = cdclk_state->voltage_level; + int cdclk = cdclk_config->cdclk; + u32 val, cmd = cdclk_config->voltage_level; intel_wakeref_t wakeref; switch (cdclk) { @@ -645,7 +653,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), 50)) { - DRM_ERROR("timed out waiting for CDclk change\n"); + drm_err(&dev_priv->drm, + "timed out waiting for CDclk change\n"); } vlv_punit_put(dev_priv); @@ -685,68 +694,70 @@ static u8 bdw_calc_voltage_level(int cdclk) } static void bdw_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - u32 lcpll = I915_READ(LCPLL_CTL); + u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; if (lcpll & LCPLL_CD_SOURCE_FCLK) - cdclk_state->cdclk = 800000; - else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 800000; + else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) + cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_450) - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; else if (freq == LCPLL_CLK_FREQ_54O_BDW) - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; else if (freq == LCPLL_CLK_FREQ_337_5_BDW) - cdclk_state->cdclk = 337500; + cdclk_config->cdclk = 337500; else - cdclk_state->cdclk = 675000; + cdclk_config->cdclk = 675000; /* * Can't read this out :( Let's assume it's * at least what the CDCLK frequency requires. */ - cdclk_state->voltage_level = - bdw_calc_voltage_level(cdclk_state->cdclk); + cdclk_config->voltage_level = + bdw_calc_voltage_level(cdclk_config->cdclk); } static void bdw_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; + int cdclk = cdclk_config->cdclk; u32 val; int ret; - if (WARN((I915_READ(LCPLL_CTL) & - (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | - LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | - LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | - LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, - "trying to change cdclk frequency with cdclk not enabled\n")) + if (drm_WARN(&dev_priv->drm, + (intel_de_read(dev_priv, LCPLL_CTL) & + (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | + LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | + LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | + LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, + "trying to change cdclk frequency with cdclk not enabled\n")) return; ret = sandybridge_pcode_write(dev_priv, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); if (ret) { - DRM_ERROR("failed to inform pcode about cdclk change\n"); + drm_err(&dev_priv->drm, + "failed to inform pcode about cdclk change\n"); return; } - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); val |= LCPLL_CD_SOURCE_FCLK; - I915_WRITE(LCPLL_CTL, val); + intel_de_write(dev_priv, LCPLL_CTL, val); /* * According to the spec, it should be enough to poll for this 1 us. * However, extensive testing shows that this can take longer. */ - if (wait_for_us(I915_READ(LCPLL_CTL) & + if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & LCPLL_CD_SOURCE_FCLK_DONE, 100)) - DRM_ERROR("Switching to FCLK failed\n"); + drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); val &= ~LCPLL_CLK_FREQ_MASK; switch (cdclk) { @@ -767,20 +778,21 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv, break; } - I915_WRITE(LCPLL_CTL, val); + intel_de_write(dev_priv, LCPLL_CTL, val); - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); val &= ~LCPLL_CD_SOURCE_FCLK; - I915_WRITE(LCPLL_CTL, val); + intel_de_write(dev_priv, LCPLL_CTL, val); - if (wait_for_us((I915_READ(LCPLL_CTL) & - LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) - DRM_ERROR("Switching back to LCPLL failed\n"); + if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & + LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) + drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, - cdclk_state->voltage_level); + cdclk_config->voltage_level); - I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); + intel_de_write(dev_priv, CDCLK_FREQ, + DIV_ROUND_CLOSEST(cdclk, 1000) - 1); intel_update_cdclk(dev_priv); } @@ -821,26 +833,27 @@ static u8 skl_calc_voltage_level(int cdclk) } static void skl_dpll0_update(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 val; - cdclk_state->ref = 24000; - cdclk_state->vco = 0; + cdclk_config->ref = 24000; + cdclk_config->vco = 0; - val = I915_READ(LCPLL1_CTL); + val = intel_de_read(dev_priv, LCPLL1_CTL); if ((val & LCPLL_PLL_ENABLE) == 0) return; - if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) + if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) return; - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); - if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | - DPLL_CTRL1_SSC(SKL_DPLL0) | - DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != - DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) + if (drm_WARN_ON(&dev_priv->drm, + (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | + DPLL_CTRL1_SSC(SKL_DPLL0) | + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != + DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) return; switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { @@ -848,11 +861,11 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): - cdclk_state->vco = 8100000; + cdclk_config->vco = 8100000; break; case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): - cdclk_state->vco = 8640000; + cdclk_config->vco = 8640000; break; default: MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); @@ -861,32 +874,32 @@ static void skl_dpll0_update(struct drm_i915_private *dev_priv, } static void skl_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 cdctl; - skl_dpll0_update(dev_priv, cdclk_state); + skl_dpll0_update(dev_priv, cdclk_config); - cdclk_state->cdclk = cdclk_state->bypass = cdclk_state->ref; + cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; - if (cdclk_state->vco == 0) + if (cdclk_config->vco == 0) goto out; - cdctl = I915_READ(CDCLK_CTL); + cdctl = intel_de_read(dev_priv, CDCLK_CTL); - if (cdclk_state->vco == 8640000) { + if (cdclk_config->vco == 8640000) { switch (cdctl & CDCLK_FREQ_SEL_MASK) { case CDCLK_FREQ_450_432: - cdclk_state->cdclk = 432000; + cdclk_config->cdclk = 432000; break; case CDCLK_FREQ_337_308: - cdclk_state->cdclk = 308571; + cdclk_config->cdclk = 308571; break; case CDCLK_FREQ_540: - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; break; case CDCLK_FREQ_675_617: - cdclk_state->cdclk = 617143; + cdclk_config->cdclk = 617143; break; default: MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); @@ -895,16 +908,16 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv, } else { switch (cdctl & CDCLK_FREQ_SEL_MASK) { case CDCLK_FREQ_450_432: - cdclk_state->cdclk = 450000; + cdclk_config->cdclk = 450000; break; case CDCLK_FREQ_337_308: - cdclk_state->cdclk = 337500; + cdclk_config->cdclk = 337500; break; case CDCLK_FREQ_540: - cdclk_state->cdclk = 540000; + cdclk_config->cdclk = 540000; break; case CDCLK_FREQ_675_617: - cdclk_state->cdclk = 675000; + cdclk_config->cdclk = 675000; break; default: MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); @@ -917,8 +930,8 @@ static void skl_get_cdclk(struct drm_i915_private *dev_priv, * Can't read this out :( Let's assume it's * at least what the CDCLK frequency requires. */ - cdclk_state->voltage_level = - skl_calc_voltage_level(cdclk_state->cdclk); + cdclk_config->voltage_level = + skl_calc_voltage_level(cdclk_config->cdclk); } /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ @@ -942,7 +955,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) { u32 val; - WARN_ON(vco != 8100000 && vco != 8640000); + drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); /* * We always enable DPLL0 with the lowest link rate possible, but still @@ -953,7 +966,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) * rate later on, with the constraint of choosing a frequency that * works with vco. */ - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); @@ -965,13 +978,14 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0); - I915_WRITE(DPLL_CTRL1, val); - POSTING_READ(DPLL_CTRL1); + intel_de_write(dev_priv, DPLL_CTRL1, val); + intel_de_posting_read(dev_priv, DPLL_CTRL1); - I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); + intel_de_write(dev_priv, LCPLL1_CTL, + intel_de_read(dev_priv, LCPLL1_CTL) | LCPLL_PLL_ENABLE); if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) - DRM_ERROR("DPLL0 not locked\n"); + drm_err(&dev_priv->drm, "DPLL0 not locked\n"); dev_priv->cdclk.hw.vco = vco; @@ -981,19 +995,20 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) static void skl_dpll0_disable(struct drm_i915_private *dev_priv) { - I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); + intel_de_write(dev_priv, LCPLL1_CTL, + intel_de_read(dev_priv, LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) - DRM_ERROR("Couldn't disable DPLL0\n"); + drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); dev_priv->cdclk.hw.vco = 0; } static void skl_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - int vco = cdclk_state->vco; + int cdclk = cdclk_config->cdclk; + int vco = cdclk_config->vco; u32 freq_select, cdclk_ctl; int ret; @@ -1005,23 +1020,25 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, * use the corresponding VCO freq as that always leads to using the * minimum 308MHz CDCLK. */ - WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000); + drm_WARN_ON_ONCE(&dev_priv->drm, + IS_SKYLAKE(dev_priv) && vco == 8640000); ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL, SKL_CDCLK_PREPARE_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE, 3); if (ret) { - DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", - ret); + drm_err(&dev_priv->drm, + "Failed to inform PCU about cdclk change (%d)\n", ret); return; } /* Choose frequency for this cdclk */ switch (cdclk) { default: - WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); - WARN_ON(vco != 0); + drm_WARN_ON(&dev_priv->drm, + cdclk != dev_priv->cdclk.hw.bypass); + drm_WARN_ON(&dev_priv->drm, vco != 0); /* fall through */ case 308571: case 337500: @@ -1044,38 +1061,38 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, dev_priv->cdclk.hw.vco != vco) skl_dpll0_disable(dev_priv); - cdclk_ctl = I915_READ(CDCLK_CTL); + cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); if (dev_priv->cdclk.hw.vco != vco) { /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); - I915_WRITE(CDCLK_CTL, cdclk_ctl); + intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); } /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE; - I915_WRITE(CDCLK_CTL, cdclk_ctl); - POSTING_READ(CDCLK_CTL); + intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); + intel_de_posting_read(dev_priv, CDCLK_CTL); if (dev_priv->cdclk.hw.vco != vco) skl_dpll0_enable(dev_priv, vco); /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK); - I915_WRITE(CDCLK_CTL, cdclk_ctl); + intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk); - I915_WRITE(CDCLK_CTL, cdclk_ctl); + intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); /* Wa Display #1183: skl,kbl,cfl */ cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE; - I915_WRITE(CDCLK_CTL, cdclk_ctl); - POSTING_READ(CDCLK_CTL); + intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); + intel_de_posting_read(dev_priv, CDCLK_CTL); /* inform PCU of the change */ sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, - cdclk_state->voltage_level); + cdclk_config->voltage_level); intel_update_cdclk(dev_priv); } @@ -1089,11 +1106,11 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) * There is SWF18 scratchpad register defined which is set by the * pre-os which can be used by the OS drivers to check the status */ - if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) + if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) goto sanitize; intel_update_cdclk(dev_priv); - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); /* Is PLL enabled and locked ? */ if (dev_priv->cdclk.hw.vco == 0 || @@ -1106,7 +1123,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) * decimal part is programmed wrong from BIOS where pre-os does not * enable display. Verify the same as well. */ - cdctl = I915_READ(CDCLK_CTL); + cdctl = intel_de_read(dev_priv, CDCLK_CTL); expected = (cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk); if (cdctl == expected) @@ -1114,7 +1131,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) return; sanitize: - DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); + drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); /* force cdclk programming */ dev_priv->cdclk.hw.cdclk = 0; @@ -1122,9 +1139,9 @@ sanitize: dev_priv->cdclk.hw.vco = -1; } -static void skl_init_cdclk(struct drm_i915_private *dev_priv) +static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state; + struct intel_cdclk_config cdclk_config; skl_sanitize_cdclk(dev_priv); @@ -1140,26 +1157,26 @@ static void skl_init_cdclk(struct drm_i915_private *dev_priv) return; } - cdclk_state = dev_priv->cdclk.hw; + cdclk_config = dev_priv->cdclk.hw; - cdclk_state.vco = dev_priv->skl_preferred_vco_freq; - if (cdclk_state.vco == 0) - cdclk_state.vco = 8100000; - cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco); - cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); + cdclk_config.vco = dev_priv->skl_preferred_vco_freq; + if (cdclk_config.vco == 0) + cdclk_config.vco = 8100000; + cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); + cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); - skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } -static void skl_uninit_cdclk(struct drm_i915_private *dev_priv) +static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; + struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; - cdclk_state.cdclk = cdclk_state.bypass; - cdclk_state.vco = 0; - cdclk_state.voltage_level = skl_calc_voltage_level(cdclk_state.cdclk); + cdclk_config.cdclk = cdclk_config.bypass; + cdclk_config.vco = 0; + cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); - skl_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } static const struct intel_cdclk_vals bxt_cdclk_table[] = { @@ -1223,8 +1240,9 @@ static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) table[i].cdclk >= min_cdclk) return table[i].cdclk; - WARN(1, "Cannot satisfy minimum cdclk %d with refclk %u\n", - min_cdclk, dev_priv->cdclk.hw.ref); + drm_WARN(&dev_priv->drm, 1, + "Cannot satisfy minimum cdclk %d with refclk %u\n", + min_cdclk, dev_priv->cdclk.hw.ref); return 0; } @@ -1241,8 +1259,8 @@ static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) table[i].cdclk == cdclk) return dev_priv->cdclk.hw.ref * table[i].ratio; - WARN(1, "cdclk %d not valid for refclk %u\n", - cdclk, dev_priv->cdclk.hw.ref); + drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", + cdclk, dev_priv->cdclk.hw.ref); return 0; } @@ -1283,56 +1301,68 @@ static u8 ehl_calc_voltage_level(int cdclk) return 0; } +static u8 tgl_calc_voltage_level(int cdclk) +{ + if (cdclk > 556800) + return 3; + else if (cdclk > 326400) + return 2; + else if (cdclk > 312000) + return 1; + else + return 0; +} + static void cnl_readout_refclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) - cdclk_state->ref = 24000; + if (intel_de_read(dev_priv, SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz) + cdclk_config->ref = 24000; else - cdclk_state->ref = 19200; + cdclk_config->ref = 19200; } static void icl_readout_refclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { - u32 dssm = I915_READ(SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; + u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; switch (dssm) { default: MISSING_CASE(dssm); /* fall through */ case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz: - cdclk_state->ref = 24000; + cdclk_config->ref = 24000; break; case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz: - cdclk_state->ref = 19200; + cdclk_config->ref = 19200; break; case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz: - cdclk_state->ref = 38400; + cdclk_config->ref = 38400; break; } } static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 val, ratio; if (INTEL_GEN(dev_priv) >= 11) - icl_readout_refclk(dev_priv, cdclk_state); + icl_readout_refclk(dev_priv, cdclk_config); else if (IS_CANNONLAKE(dev_priv)) - cnl_readout_refclk(dev_priv, cdclk_state); + cnl_readout_refclk(dev_priv, cdclk_config); else - cdclk_state->ref = 19200; + cdclk_config->ref = 19200; - val = I915_READ(BXT_DE_PLL_ENABLE); + val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 || (val & BXT_DE_PLL_LOCK) == 0) { /* * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but * setting it to zero is a way to signal that. */ - cdclk_state->vco = 0; + cdclk_config->vco = 0; return; } @@ -1343,47 +1373,49 @@ static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) >= 10) ratio = val & CNL_CDCLK_PLL_RATIO_MASK; else - ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; + ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; - cdclk_state->vco = ratio * cdclk_state->ref; + cdclk_config->vco = ratio * cdclk_config->ref; } static void bxt_get_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_state) + struct intel_cdclk_config *cdclk_config) { u32 divider; int div; - bxt_de_pll_readout(dev_priv, cdclk_state); + bxt_de_pll_readout(dev_priv, cdclk_config); if (INTEL_GEN(dev_priv) >= 12) - cdclk_state->bypass = cdclk_state->ref / 2; + cdclk_config->bypass = cdclk_config->ref / 2; else if (INTEL_GEN(dev_priv) >= 11) - cdclk_state->bypass = 50000; + cdclk_config->bypass = 50000; else - cdclk_state->bypass = cdclk_state->ref; + cdclk_config->bypass = cdclk_config->ref; - if (cdclk_state->vco == 0) { - cdclk_state->cdclk = cdclk_state->bypass; + if (cdclk_config->vco == 0) { + cdclk_config->cdclk = cdclk_config->bypass; goto out; } - divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; + divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; switch (divider) { case BXT_CDCLK_CD2X_DIV_SEL_1: div = 2; break; case BXT_CDCLK_CD2X_DIV_SEL_1_5: - WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, - "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, + IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); div = 3; break; case BXT_CDCLK_CD2X_DIV_SEL_2: div = 4; break; case BXT_CDCLK_CD2X_DIV_SEL_4: - WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); div = 8; break; default: @@ -1391,25 +1423,25 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, return; } - cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div); + cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); out: /* * Can't read this out :( Let's assume it's * at least what the CDCLK frequency requires. */ - cdclk_state->voltage_level = - dev_priv->display.calc_voltage_level(cdclk_state->cdclk); + cdclk_config->voltage_level = + dev_priv->display.calc_voltage_level(cdclk_config->cdclk); } static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) { - I915_WRITE(BXT_DE_PLL_ENABLE, 0); + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); /* Timeout 200us */ if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) - DRM_ERROR("timeout waiting for DE PLL unlock\n"); + drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); dev_priv->cdclk.hw.vco = 0; } @@ -1419,17 +1451,17 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref); u32 val; - val = I915_READ(BXT_DE_PLL_CTL); + val = intel_de_read(dev_priv, BXT_DE_PLL_CTL); val &= ~BXT_DE_PLL_RATIO_MASK; val |= BXT_DE_PLL_RATIO(ratio); - I915_WRITE(BXT_DE_PLL_CTL, val); + intel_de_write(dev_priv, BXT_DE_PLL_CTL, val); - I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); /* Timeout 200us */ if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) - DRM_ERROR("timeout waiting for DE PLL lock\n"); + drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); dev_priv->cdclk.hw.vco = vco; } @@ -1438,13 +1470,14 @@ static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv) { u32 val; - val = I915_READ(BXT_DE_PLL_ENABLE); + val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); val &= ~BXT_DE_PLL_PLL_ENABLE; - I915_WRITE(BXT_DE_PLL_ENABLE, val); + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); /* Timeout 200us */ - if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) - DRM_ERROR("timeout waiting for CDCLK PLL unlock\n"); + if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) + drm_err(&dev_priv->drm, + "timeout waiting for CDCLK PLL unlock\n"); dev_priv->cdclk.hw.vco = 0; } @@ -1455,14 +1488,15 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) u32 val; val = CNL_CDCLK_PLL_RATIO(ratio); - I915_WRITE(BXT_DE_PLL_ENABLE, val); + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); val |= BXT_DE_PLL_PLL_ENABLE; - I915_WRITE(BXT_DE_PLL_ENABLE, val); + intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); /* Timeout 200us */ - if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) - DRM_ERROR("timeout waiting for CDCLK PLL lock\n"); + if (wait_for((intel_de_read(dev_priv, BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) + drm_err(&dev_priv->drm, + "timeout waiting for CDCLK PLL lock\n"); dev_priv->cdclk.hw.vco = vco; } @@ -1488,11 +1522,11 @@ static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe } static void bxt_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - int cdclk = cdclk_state->cdclk; - int vco = cdclk_state->vco; + int cdclk = cdclk_config->cdclk; + int vco = cdclk_config->vco; u32 val, divider; int ret; @@ -1512,30 +1546,34 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, 0x80000000, 150, 2); if (ret) { - DRM_ERROR("Failed to inform PCU about cdclk change (err %d, freq %d)\n", - ret, cdclk); + drm_err(&dev_priv->drm, + "Failed to inform PCU about cdclk change (err %d, freq %d)\n", + ret, cdclk); return; } /* cdclk = vco / 2 / div{1,1.5,2,4} */ switch (DIV_ROUND_CLOSEST(vco, cdclk)) { default: - WARN_ON(cdclk != dev_priv->cdclk.hw.bypass); - WARN_ON(vco != 0); + drm_WARN_ON(&dev_priv->drm, + cdclk != dev_priv->cdclk.hw.bypass); + drm_WARN_ON(&dev_priv->drm, vco != 0); /* fall through */ case 2: divider = BXT_CDCLK_CD2X_DIV_SEL_1; break; case 3: - WARN(IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, - "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, + IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; break; case 4: divider = BXT_CDCLK_CD2X_DIV_SEL_2; break; case 8: - WARN(INTEL_GEN(dev_priv) >= 10, "Unsupported divider\n"); + drm_WARN(&dev_priv->drm, INTEL_GEN(dev_priv) >= 10, + "Unsupported divider\n"); divider = BXT_CDCLK_CD2X_DIV_SEL_4; break; } @@ -1566,14 +1604,14 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, */ if (IS_GEN9_LP(dev_priv) && cdclk >= 500000) val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; - I915_WRITE(CDCLK_CTL, val); + intel_de_write(dev_priv, CDCLK_CTL, val); if (pipe != INVALID_PIPE) intel_wait_for_vblank(dev_priv, pipe); if (INTEL_GEN(dev_priv) >= 10) { ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, - cdclk_state->voltage_level); + cdclk_config->voltage_level); } else { /* * The timeout isn't specified, the 2ms used here is based on @@ -1583,13 +1621,14 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, */ ret = sandybridge_pcode_write_timeout(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, - cdclk_state->voltage_level, + cdclk_config->voltage_level, 150, 2); } if (ret) { - DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", - ret, cdclk); + drm_err(&dev_priv->drm, + "PCode CDCLK freq set failed, (err %d, freq %d)\n", + ret, cdclk); return; } @@ -1600,7 +1639,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, * Can't read out the voltage level :( * Let's just assume everything is as expected. */ - dev_priv->cdclk.hw.voltage_level = cdclk_state->voltage_level; + dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level; } static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) @@ -1609,7 +1648,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) int cdclk, vco; intel_update_cdclk(dev_priv); - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); if (dev_priv->cdclk.hw.vco == 0 || dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass) @@ -1621,7 +1660,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, * so sanitize this register. */ - cdctl = I915_READ(CDCLK_CTL); + cdctl = intel_de_read(dev_priv, CDCLK_CTL); /* * Let's ignore the pipe field, since BIOS could have configured the * dividers both synching to an active pipe, or asynchronously @@ -1672,7 +1711,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) return; sanitize: - DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); + drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); /* force cdclk programming */ dev_priv->cdclk.hw.cdclk = 0; @@ -1681,9 +1720,9 @@ sanitize: dev_priv->cdclk.hw.vco = -1; } -static void bxt_init_cdclk(struct drm_i915_private *dev_priv) +static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state; + struct intel_cdclk_config cdclk_config; bxt_sanitize_cdclk(dev_priv); @@ -1691,35 +1730,35 @@ static void bxt_init_cdclk(struct drm_i915_private *dev_priv) dev_priv->cdclk.hw.vco != 0) return; - cdclk_state = dev_priv->cdclk.hw; + cdclk_config = dev_priv->cdclk.hw; /* * FIXME: * - The initial CDCLK needs to be read from VBT. * Need to make this change after VBT has changes for BXT. */ - cdclk_state.cdclk = bxt_calc_cdclk(dev_priv, 0); - cdclk_state.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_state.cdclk); - cdclk_state.voltage_level = - dev_priv->display.calc_voltage_level(cdclk_state.cdclk); + cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); + cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); + cdclk_config.voltage_level = + dev_priv->display.calc_voltage_level(cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } -static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) +static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw; + struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw; - cdclk_state.cdclk = cdclk_state.bypass; - cdclk_state.vco = 0; - cdclk_state.voltage_level = - dev_priv->display.calc_voltage_level(cdclk_state.cdclk); + cdclk_config.cdclk = cdclk_config.bypass; + cdclk_config.vco = 0; + cdclk_config.voltage_level = + dev_priv->display.calc_voltage_level(cdclk_config.cdclk); - bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE); + bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); } /** - * intel_cdclk_init - Initialize CDCLK + * intel_cdclk_init_hw - Initialize CDCLK hardware * @i915: i915 device * * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and @@ -1727,39 +1766,41 @@ static void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) * during the display core initialization sequence, after which the DMC will * take care of turning CDCLK off/on as needed. */ -void intel_cdclk_init(struct drm_i915_private *i915) +void intel_cdclk_init_hw(struct drm_i915_private *i915) { if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10) - bxt_init_cdclk(i915); + bxt_cdclk_init_hw(i915); else if (IS_GEN9_BC(i915)) - skl_init_cdclk(i915); + skl_cdclk_init_hw(i915); } /** - * intel_cdclk_uninit - Uninitialize CDCLK + * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware * @i915: i915 device * * Uninitialize CDCLK. This is done only during the display core * uninitialization sequence. */ -void intel_cdclk_uninit(struct drm_i915_private *i915) +void intel_cdclk_uninit_hw(struct drm_i915_private *i915) { if (INTEL_GEN(i915) >= 10 || IS_GEN9_LP(i915)) - bxt_uninit_cdclk(i915); + bxt_cdclk_uninit_hw(i915); else if (IS_GEN9_BC(i915)) - skl_uninit_cdclk(i915); + skl_cdclk_uninit_hw(i915); } /** - * intel_cdclk_needs_modeset - Determine if two CDCLK states require a modeset on all pipes - * @a: first CDCLK state - * @b: second CDCLK state + * intel_cdclk_needs_modeset - Determine if changong between the CDCLK + * configurations requires a modeset on all pipes + * @a: first CDCLK configuration + * @b: second CDCLK configuration * * Returns: - * True if the CDCLK states require pipes to be off during reprogramming, false if not. + * True if changing between the two CDCLK configurations + * requires all pipes to be off, false if not. */ -bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b) +bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) { return a->cdclk != b->cdclk || a->vco != b->vco || @@ -1767,17 +1808,19 @@ bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, } /** - * intel_cdclk_needs_cd2x_update - Determine if two CDCLK states require a cd2x divider update - * @dev_priv: Not a CDCLK state, it's the drm_i915_private! - * @a: first CDCLK state - * @b: second CDCLK state + * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK + * configurations requires only a cd2x divider update + * @dev_priv: i915 device + * @a: first CDCLK configuration + * @b: second CDCLK configuration * * Returns: - * True if the CDCLK states require just a cd2x divider update, false if not. + * True if changing between the two CDCLK configurations + * can be done with just a cd2x divider update, false if not. */ -static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b) +static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, + const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) { /* Older hw doesn't have the capability */ if (INTEL_GEN(dev_priv) < 10 && !IS_GEN9_LP(dev_priv)) @@ -1789,117 +1832,138 @@ static bool intel_cdclk_needs_cd2x_update(struct drm_i915_private *dev_priv, } /** - * intel_cdclk_changed - Determine if two CDCLK states are different - * @a: first CDCLK state - * @b: second CDCLK state + * intel_cdclk_changed - Determine if two CDCLK configurations are different + * @a: first CDCLK configuration + * @b: second CDCLK configuration * * Returns: - * True if the CDCLK states don't match, false if they do. + * True if the CDCLK configurations don't match, false if they do. */ -static bool intel_cdclk_changed(const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b) +static bool intel_cdclk_changed(const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b) { return intel_cdclk_needs_modeset(a, b) || a->voltage_level != b->voltage_level; } -/** - * intel_cdclk_swap_state - make atomic CDCLK configuration effective - * @state: atomic state - * - * This is the CDCLK version of drm_atomic_helper_swap_state() since the - * helper does not handle driver-specific global state. - * - * Similarly to the atomic helpers this function does a complete swap, - * i.e. it also puts the old state into @state. This is used by the commit - * code to determine how CDCLK has changed (for instance did it increase or - * decrease). - */ -void intel_cdclk_swap_state(struct intel_atomic_state *state) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - - swap(state->cdclk.logical, dev_priv->cdclk.logical); - swap(state->cdclk.actual, dev_priv->cdclk.actual); -} - -void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, - const char *context) +void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, + const char *context) { DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", - context, cdclk_state->cdclk, cdclk_state->vco, - cdclk_state->ref, cdclk_state->bypass, - cdclk_state->voltage_level); + context, cdclk_config->cdclk, cdclk_config->vco, + cdclk_config->ref, cdclk_config->bypass, + cdclk_config->voltage_level); } /** - * intel_set_cdclk - Push the CDCLK state to the hardware + * intel_set_cdclk - Push the CDCLK configuration to the hardware * @dev_priv: i915 device - * @cdclk_state: new CDCLK state + * @cdclk_config: new CDCLK configuration * @pipe: pipe with which to synchronize the update * * Program the hardware based on the passed in CDCLK state, * if necessary. */ static void intel_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state, + const struct intel_cdclk_config *cdclk_config, enum pipe pipe) { - if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state)) + struct intel_encoder *encoder; + + if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config)) return; - if (WARN_ON_ONCE(!dev_priv->display.set_cdclk)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk)) return; - intel_dump_cdclk_state(cdclk_state, "Changing CDCLK to"); + intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); - dev_priv->display.set_cdclk(dev_priv, cdclk_state, pipe); + /* + * Lock aux/gmbus while we change cdclk in case those + * functions use cdclk. Not all platforms/ports do, + * but we'll lock them all for simplicity. + */ + mutex_lock(&dev_priv->gmbus_mutex); + for_each_intel_dp(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, + &dev_priv->gmbus_mutex); + } + + dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe); - if (WARN(intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_state), - "cdclk state doesn't match!\n")) { - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "[hw state]"); - intel_dump_cdclk_state(cdclk_state, "[sw state]"); + for_each_intel_dp(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + mutex_unlock(&intel_dp->aux.hw_mutex); + } + mutex_unlock(&dev_priv->gmbus_mutex); + + if (drm_WARN(&dev_priv->drm, + intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), + "cdclk state doesn't match!\n")) { + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]"); + intel_dump_cdclk_config(cdclk_config, "[sw state]"); } } /** * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK state - * @new_state: new CDCLK state - * @pipe: pipe with which to synchronize the update + * @state: intel atomic state * - * Program the hardware before updating the HW plane state based on the passed - * in CDCLK state, if necessary. + * Program the hardware before updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, - enum pipe pipe) +intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) { - if (pipe == INVALID_PIPE || old_state->cdclk <= new_state->cdclk) - intel_set_cdclk(dev_priv, new_state, pipe); + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_cdclk_state *old_cdclk_state = + intel_atomic_get_old_cdclk_state(state); + const struct intel_cdclk_state *new_cdclk_state = + intel_atomic_get_new_cdclk_state(state); + enum pipe pipe = new_cdclk_state->pipe; + + if (!intel_cdclk_changed(&old_cdclk_state->actual, + &new_cdclk_state->actual)) + return; + + if (pipe == INVALID_PIPE || + old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) { + drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); + + intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); + } } /** * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware - * @dev_priv: i915 device - * @old_state: old CDCLK state - * @new_state: new CDCLK state - * @pipe: pipe with which to synchronize the update + * @state: intel atomic state * - * Program the hardware after updating the HW plane state based on the passed - * in CDCLK state, if necessary. + * Program the hardware after updating the HW plane state based on the + * new CDCLK state, if necessary. */ void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, - enum pipe pipe) +intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) { - if (pipe != INVALID_PIPE && old_state->cdclk > new_state->cdclk) - intel_set_cdclk(dev_priv, new_state, pipe); + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_cdclk_state *old_cdclk_state = + intel_atomic_get_old_cdclk_state(state); + const struct intel_cdclk_state *new_cdclk_state = + intel_atomic_get_new_cdclk_state(state); + enum pipe pipe = new_cdclk_state->pipe; + + if (!intel_cdclk_changed(&old_cdclk_state->actual, + &new_cdclk_state->actual)) + return; + + if (pipe != INVALID_PIPE && + old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) { + drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed); + + intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe); + } } static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state) @@ -2017,25 +2081,24 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate); if (min_cdclk > dev_priv->max_cdclk_freq) { - DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n", - min_cdclk, dev_priv->max_cdclk_freq); + drm_dbg_kms(&dev_priv->drm, + "required cdclk (%d kHz) exceeds max (%d kHz)\n", + min_cdclk, dev_priv->max_cdclk_freq); return -EINVAL; } return min_cdclk; } -static int intel_compute_min_cdclk(struct intel_atomic_state *state) +static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) { + struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int min_cdclk, i; enum pipe pipe; - memcpy(state->min_cdclk, dev_priv->min_cdclk, - sizeof(state->min_cdclk)); - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2043,19 +2106,19 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) if (min_cdclk < 0) return min_cdclk; - if (state->min_cdclk[i] == min_cdclk) + if (cdclk_state->min_cdclk[i] == min_cdclk) continue; - state->min_cdclk[i] = min_cdclk; + cdclk_state->min_cdclk[i] = min_cdclk; - ret = intel_atomic_lock_global_state(state); + ret = intel_atomic_lock_global_state(&cdclk_state->base); if (ret) return ret; } - min_cdclk = state->cdclk.force_min_cdclk; + min_cdclk = cdclk_state->force_min_cdclk; for_each_pipe(dev_priv, pipe) - min_cdclk = max(state->min_cdclk[pipe], min_cdclk); + min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); return min_cdclk; } @@ -2073,8 +2136,9 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state) * future platforms this code will need to be * adjusted. */ -static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) +static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) { + struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; @@ -2082,9 +2146,6 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) int i; enum pipe pipe; - memcpy(state->min_voltage_level, dev_priv->min_voltage_level, - sizeof(state->min_voltage_level)); - for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret; @@ -2093,57 +2154,58 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) else min_voltage_level = 0; - if (state->min_voltage_level[i] == min_voltage_level) + if (cdclk_state->min_voltage_level[i] == min_voltage_level) continue; - state->min_voltage_level[i] = min_voltage_level; + cdclk_state->min_voltage_level[i] = min_voltage_level; - ret = intel_atomic_lock_global_state(state); + ret = intel_atomic_lock_global_state(&cdclk_state->base); if (ret) return ret; } min_voltage_level = 0; for_each_pipe(dev_priv, pipe) - min_voltage_level = max(state->min_voltage_level[pipe], + min_voltage_level = max(cdclk_state->min_voltage_level[pipe], min_voltage_level); return min_voltage_level; } -static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) +static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) { + struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); int min_cdclk, cdclk; - min_cdclk = intel_compute_min_cdclk(state); + min_cdclk = intel_compute_min_cdclk(cdclk_state); if (min_cdclk < 0) return min_cdclk; cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = vlv_calc_voltage_level(dev_priv, cdclk); - if (!state->active_pipes) { - cdclk = vlv_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); + if (!cdclk_state->active_pipes) { + cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = vlv_calc_voltage_level(dev_priv, cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; } -static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) +static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) { int min_cdclk, cdclk; - min_cdclk = intel_compute_min_cdclk(state); + min_cdclk = intel_compute_min_cdclk(cdclk_state); if (min_cdclk < 0) return min_cdclk; @@ -2153,31 +2215,32 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) */ cdclk = bdw_calc_cdclk(min_cdclk); - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = bdw_calc_voltage_level(cdclk); - if (!state->active_pipes) { - cdclk = bdw_calc_cdclk(state->cdclk.force_min_cdclk); + if (!cdclk_state->active_pipes) { + cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = bdw_calc_voltage_level(cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; } -static int skl_dpll0_vco(struct intel_atomic_state *state) +static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) { + struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int vco, i; - vco = state->cdclk.logical.vco; + vco = cdclk_state->logical.vco; if (!vco) vco = dev_priv->skl_preferred_vco_freq; @@ -2206,15 +2269,15 @@ static int skl_dpll0_vco(struct intel_atomic_state *state) return vco; } -static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) +static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) { int min_cdclk, cdclk, vco; - min_cdclk = intel_compute_min_cdclk(state); + min_cdclk = intel_compute_min_cdclk(cdclk_state); if (min_cdclk < 0) return min_cdclk; - vco = skl_dpll0_vco(state); + vco = skl_dpll0_vco(cdclk_state); /* * FIXME should also account for plane ratio @@ -2222,57 +2285,58 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) */ cdclk = skl_calc_cdclk(min_cdclk, vco); - state->cdclk.logical.vco = vco; - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.vco = vco; + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = skl_calc_voltage_level(cdclk); - if (!state->active_pipes) { - cdclk = skl_calc_cdclk(state->cdclk.force_min_cdclk, vco); + if (!cdclk_state->active_pipes) { + cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); - state->cdclk.actual.vco = vco; - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.vco = vco; + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = skl_calc_voltage_level(cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; } -static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) +static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) { + struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); int min_cdclk, min_voltage_level, cdclk, vco; - min_cdclk = intel_compute_min_cdclk(state); + min_cdclk = intel_compute_min_cdclk(cdclk_state); if (min_cdclk < 0) return min_cdclk; - min_voltage_level = bxt_compute_min_voltage_level(state); + min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); if (min_voltage_level < 0) return min_voltage_level; cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); - state->cdclk.logical.vco = vco; - state->cdclk.logical.cdclk = cdclk; - state->cdclk.logical.voltage_level = + cdclk_state->logical.vco = vco; + cdclk_state->logical.cdclk = cdclk; + cdclk_state->logical.voltage_level = max_t(int, min_voltage_level, dev_priv->display.calc_voltage_level(cdclk)); - if (!state->active_pipes) { - cdclk = bxt_calc_cdclk(dev_priv, state->cdclk.force_min_cdclk); + if (!cdclk_state->active_pipes) { + cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); - state->cdclk.actual.vco = vco; - state->cdclk.actual.cdclk = cdclk; - state->cdclk.actual.voltage_level = + cdclk_state->actual.vco = vco; + cdclk_state->actual.cdclk = cdclk; + cdclk_state->actual.voltage_level = dev_priv->display.calc_voltage_level(cdclk); } else { - state->cdclk.actual = state->cdclk.logical; + cdclk_state->actual = cdclk_state->logical; } return 0; @@ -2317,7 +2381,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state) return 0; } -static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) +static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) { int min_cdclk; @@ -2326,54 +2390,113 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) * check that the required minimum frequency doesn't exceed * the actual cdclk frequency. */ - min_cdclk = intel_compute_min_cdclk(state); + min_cdclk = intel_compute_min_cdclk(cdclk_state); if (min_cdclk < 0) return min_cdclk; return 0; } +static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj) +{ + struct intel_cdclk_state *cdclk_state; + + cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); + if (!cdclk_state) + return NULL; + + cdclk_state->force_min_cdclk_changed = false; + cdclk_state->pipe = INVALID_PIPE; + + return &cdclk_state->base; +} + +static void intel_cdclk_destroy_state(struct intel_global_obj *obj, + struct intel_global_state *state) +{ + kfree(state); +} + +static const struct intel_global_state_funcs intel_cdclk_funcs = { + .atomic_duplicate_state = intel_cdclk_duplicate_state, + .atomic_destroy_state = intel_cdclk_destroy_state, +}; + +struct intel_cdclk_state * +intel_atomic_get_cdclk_state(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_global_state *cdclk_state; + + cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj); + if (IS_ERR(cdclk_state)) + return ERR_CAST(cdclk_state); + + return to_intel_cdclk_state(cdclk_state); +} + +int intel_cdclk_init(struct drm_i915_private *dev_priv) +{ + struct intel_cdclk_state *cdclk_state; + + cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL); + if (!cdclk_state) + return -ENOMEM; + + intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj, + &cdclk_state->base, &intel_cdclk_funcs); + + return 0; +} + int intel_modeset_calc_cdclk(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); + const struct intel_cdclk_state *old_cdclk_state; + struct intel_cdclk_state *new_cdclk_state; enum pipe pipe; int ret; - ret = dev_priv->display.modeset_calc_cdclk(state); + new_cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(new_cdclk_state)) + return PTR_ERR(new_cdclk_state); + + old_cdclk_state = intel_atomic_get_old_cdclk_state(state); + + new_cdclk_state->active_pipes = + intel_calc_active_pipes(state, old_cdclk_state->active_pipes); + + ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state); if (ret) return ret; - /* - * Writes to dev_priv->cdclk.{actual,logical} must protected - * by holding all the crtc mutexes even if we don't end up - * touching the hardware - */ - if (intel_cdclk_changed(&dev_priv->cdclk.actual, - &state->cdclk.actual)) { + if (intel_cdclk_changed(&old_cdclk_state->actual, + &new_cdclk_state->actual)) { /* * Also serialize commits across all crtcs * if the actual hw needs to be poked. */ - ret = intel_atomic_serialize_global_state(state); + ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); if (ret) return ret; - } else if (intel_cdclk_changed(&dev_priv->cdclk.logical, - &state->cdclk.logical)) { - ret = intel_atomic_lock_global_state(state); + } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || + intel_cdclk_changed(&old_cdclk_state->logical, + &new_cdclk_state->logical)) { + ret = intel_atomic_lock_global_state(&new_cdclk_state->base); if (ret) return ret; } else { return 0; } - if (is_power_of_2(state->active_pipes) && - intel_cdclk_needs_cd2x_update(dev_priv, - &dev_priv->cdclk.actual, - &state->cdclk.actual)) { + if (is_power_of_2(new_cdclk_state->active_pipes) && + intel_cdclk_can_cd2x_update(dev_priv, + &old_cdclk_state->actual, + &new_cdclk_state->actual)) { struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; - pipe = ilog2(state->active_pipes); + pipe = ilog2(new_cdclk_state->active_pipes); crtc = intel_get_crtc_for_pipe(dev_priv, pipe); crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); @@ -2387,28 +2510,32 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) } if (pipe != INVALID_PIPE) { - state->cdclk.pipe = pipe; + new_cdclk_state->pipe = pipe; - DRM_DEBUG_KMS("Can change cdclk with pipe %c active\n", - pipe_name(pipe)); - } else if (intel_cdclk_needs_modeset(&dev_priv->cdclk.actual, - &state->cdclk.actual)) { + drm_dbg_kms(&dev_priv->drm, + "Can change cdclk with pipe %c active\n", + pipe_name(pipe)); + } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, + &new_cdclk_state->actual)) { /* All pipes must be switched off while we change the cdclk. */ ret = intel_modeset_all_pipes(state); if (ret) return ret; - state->cdclk.pipe = INVALID_PIPE; + new_cdclk_state->pipe = INVALID_PIPE; - DRM_DEBUG_KMS("Modeset required for cdclk change\n"); + drm_dbg_kms(&dev_priv->drm, + "Modeset required for cdclk change\n"); } - DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", - state->cdclk.logical.cdclk, - state->cdclk.actual.cdclk); - DRM_DEBUG_KMS("New voltage level calculated to be logical %u, actual %u\n", - state->cdclk.logical.voltage_level, - state->cdclk.actual.voltage_level); + drm_dbg_kms(&dev_priv->drm, + "New cdclk calculated to be logical %u kHz, actual %u kHz\n", + new_cdclk_state->logical.cdclk, + new_cdclk_state->actual.cdclk); + drm_dbg_kms(&dev_priv->drm, + "New voltage level calculated to be logical %u, actual %u\n", + new_cdclk_state->logical.voltage_level, + new_cdclk_state->actual.voltage_level); return 0; } @@ -2453,11 +2580,11 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) } else if (IS_CANNONLAKE(dev_priv)) { dev_priv->max_cdclk_freq = 528000; } else if (IS_GEN9_BC(dev_priv)) { - u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; + u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; int max_cdclk, vco; vco = dev_priv->skl_preferred_vco_freq; - WARN_ON(vco != 8100000 && vco != 8640000); + drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); /* * Use the lower (vco 8640) cdclk values as a @@ -2485,7 +2612,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) * How can we know if extra cooling is * available? PCI ID, VTB, something else? */ - if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) + if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) dev_priv->max_cdclk_freq = 450000; else if (IS_BDW_ULX(dev_priv)) dev_priv->max_cdclk_freq = 450000; @@ -2504,11 +2631,11 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); - DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", - dev_priv->max_cdclk_freq); + drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", + dev_priv->max_cdclk_freq); - DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", - dev_priv->max_dotclk_freq); + drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", + dev_priv->max_dotclk_freq); } /** @@ -2528,8 +2655,8 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv) * generate GMBus clock. This will vary with the cdclk freq. */ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - I915_WRITE(GMBUSFREQ_VLV, - DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); + intel_de_write(dev_priv, GMBUSFREQ_VLV, + DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000)); } static int cnp_rawclk(struct drm_i915_private *dev_priv) @@ -2537,7 +2664,7 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv) u32 rawclk; int divider, fraction; - if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { + if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { /* 24 MHz */ divider = 24000; fraction = 0; @@ -2557,13 +2684,13 @@ static int cnp_rawclk(struct drm_i915_private *dev_priv) rawclk |= ICP_RAWCLK_NUM(numerator); } - I915_WRITE(PCH_RAWCLK_FREQ, rawclk); + intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); return divider + fraction; } static int pch_rawclk(struct drm_i915_private *dev_priv) { - return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; + return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; } static int vlv_hrawclk(struct drm_i915_private *dev_priv) @@ -2578,7 +2705,7 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) u32 clkcfg; /* hrawclock is 1/4 the FSB frequency */ - clkcfg = I915_READ(CLKCFG); + clkcfg = intel_de_read(dev_priv, CLKCFG); switch (clkcfg & CLKCFG_FSB_MASK) { case CLKCFG_FSB_400: return 100000; @@ -2600,27 +2727,29 @@ static int g4x_hrawclk(struct drm_i915_private *dev_priv) } /** - * intel_update_rawclk - Determine the current RAWCLK frequency + * intel_read_rawclk - Determine the current RAWCLK frequency * @dev_priv: i915 device * * Determine the current RAWCLK frequency. RAWCLK is a fixed * frequency clock so this needs to done only once. */ -void intel_update_rawclk(struct drm_i915_private *dev_priv) +u32 intel_read_rawclk(struct drm_i915_private *dev_priv) { + u32 freq; + if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) - dev_priv->rawclk_freq = cnp_rawclk(dev_priv); + freq = cnp_rawclk(dev_priv); else if (HAS_PCH_SPLIT(dev_priv)) - dev_priv->rawclk_freq = pch_rawclk(dev_priv); + freq = pch_rawclk(dev_priv); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) - dev_priv->rawclk_freq = vlv_hrawclk(dev_priv); + freq = vlv_hrawclk(dev_priv); else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) - dev_priv->rawclk_freq = g4x_hrawclk(dev_priv); + freq = g4x_hrawclk(dev_priv); else /* no rawclk on other platforms, or no need to know it */ - return; + return 0; - DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); + return freq; } /** @@ -2629,7 +2758,12 @@ void intel_update_rawclk(struct drm_i915_private *dev_priv) */ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) { - if (IS_ELKHARTLAKE(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 12) { + dev_priv->display.set_cdclk = bxt_set_cdclk; + dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; + dev_priv->display.calc_voltage_level = tgl_calc_voltage_level; + dev_priv->cdclk.table = icl_cdclk_table; + } else if (IS_ELKHARTLAKE(dev_priv)) { dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; dev_priv->display.calc_voltage_level = ehl_calc_voltage_level; @@ -2709,8 +2843,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) else if (IS_I845G(dev_priv)) dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk; else { /* 830 */ - WARN(!IS_I830(dev_priv), - "Unknown platform. Assuming 133 MHz CDCLK\n"); + drm_WARN(&dev_priv->drm, !IS_I830(dev_priv), + "Unknown platform. Assuming 133 MHz CDCLK\n"); dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk; } } diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index cf71394cc79c..5731806e4cee 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -8,11 +8,12 @@ #include <linux/types.h> +#include "i915_drv.h" #include "intel_display.h" +#include "intel_global_state.h" struct drm_i915_private; struct intel_atomic_state; -struct intel_cdclk_state; struct intel_crtc_state; struct intel_cdclk_vals { @@ -22,28 +23,62 @@ struct intel_cdclk_vals { u8 ratio; }; +struct intel_cdclk_state { + struct intel_global_state base; + + /* + * Logical configuration of cdclk (used for all scaling, + * watermark, etc. calculations and checks). This is + * computed as if all enabled crtcs were active. + */ + struct intel_cdclk_config logical; + + /* + * Actual configuration of cdclk, can be different from the + * logical configuration only when all crtc's are DPMS off. + */ + struct intel_cdclk_config actual; + + /* minimum acceptable cdclk for each pipe */ + int min_cdclk[I915_MAX_PIPES]; + /* minimum acceptable voltage level for each pipe */ + u8 min_voltage_level[I915_MAX_PIPES]; + + /* pipe to which cd2x update is synchronized */ + enum pipe pipe; + + /* forced minimum cdclk for glk+ audio w/a */ + int force_min_cdclk; + bool force_min_cdclk_changed; + + /* bitmask of active pipes */ + u8 active_pipes; +}; + int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state); -void intel_cdclk_init(struct drm_i915_private *i915); -void intel_cdclk_uninit(struct drm_i915_private *i915); +void intel_cdclk_init_hw(struct drm_i915_private *i915); +void intel_cdclk_uninit_hw(struct drm_i915_private *i915); void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv); void intel_update_max_cdclk(struct drm_i915_private *dev_priv); void intel_update_cdclk(struct drm_i915_private *dev_priv); -void intel_update_rawclk(struct drm_i915_private *dev_priv); -bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a, - const struct intel_cdclk_state *b); -void intel_cdclk_swap_state(struct intel_atomic_state *state); -void -intel_set_cdclk_pre_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, - enum pipe pipe); -void -intel_set_cdclk_post_plane_update(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *old_state, - const struct intel_cdclk_state *new_state, - enum pipe pipe); -void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state, - const char *context); +u32 intel_read_rawclk(struct drm_i915_private *dev_priv); +bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a, + const struct intel_cdclk_config *b); +void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state); +void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); +void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config, + const char *context); int intel_modeset_calc_cdclk(struct intel_atomic_state *state); +struct intel_cdclk_state * +intel_atomic_get_cdclk_state(struct intel_atomic_state *state); + +#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base) +#define intel_atomic_get_old_cdclk_state(state) \ + to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)) +#define intel_atomic_get_new_cdclk_state(state) \ + to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj)) + +int intel_cdclk_init(struct drm_i915_private *dev_priv); + #endif /* __INTEL_CDCLK_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 3980e8b50c28..c1cce93a1c25 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -157,23 +157,29 @@ static void ilk_update_pipe_csc(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]); - I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]); - I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]); + intel_de_write(dev_priv, PIPE_CSC_PREOFF_HI(pipe), preoff[0]); + intel_de_write(dev_priv, PIPE_CSC_PREOFF_ME(pipe), preoff[1]); + intel_de_write(dev_priv, PIPE_CSC_PREOFF_LO(pipe), preoff[2]); - I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]); - I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); + intel_de_write(dev_priv, PIPE_CSC_COEFF_RY_GY(pipe), + coeff[0] << 16 | coeff[1]); + intel_de_write(dev_priv, PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); - I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]); - I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); + intel_de_write(dev_priv, PIPE_CSC_COEFF_RU_GU(pipe), + coeff[3] << 16 | coeff[4]); + intel_de_write(dev_priv, PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); - I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]); - I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); + intel_de_write(dev_priv, PIPE_CSC_COEFF_RV_GV(pipe), + coeff[6] << 16 | coeff[7]); + intel_de_write(dev_priv, PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); if (INTEL_GEN(dev_priv) >= 7) { - I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff[0]); - I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff[1]); - I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff[2]); + intel_de_write(dev_priv, PIPE_CSC_POSTOFF_HI(pipe), + postoff[0]); + intel_de_write(dev_priv, PIPE_CSC_POSTOFF_ME(pipe), + postoff[1]); + intel_de_write(dev_priv, PIPE_CSC_POSTOFF_LO(pipe), + postoff[2]); } } @@ -185,22 +191,28 @@ static void icl_update_output_csc(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]); - I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]); - I915_WRITE(PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_HI(pipe), preoff[0]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_ME(pipe), preoff[1]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_PREOFF_LO(pipe), preoff[2]); - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]); - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BY(pipe), coeff[2] << 16); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe), + coeff[0] << 16 | coeff[1]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BY(pipe), + coeff[2] << 16); - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]); - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BU(pipe), coeff[5] << 16); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe), + coeff[3] << 16 | coeff[4]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BU(pipe), + coeff[5] << 16); - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]); - I915_WRITE(PIPE_CSC_OUTPUT_COEFF_BV(pipe), coeff[8] << 16); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe), + coeff[6] << 16 | coeff[7]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_COEFF_BV(pipe), + coeff[8] << 16); - I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]); - I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]); - I915_WRITE(PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_HI(pipe), postoff[0]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_ME(pipe), postoff[1]); + intel_de_write(dev_priv, PIPE_CSC_OUTPUT_POSTOFF_LO(pipe), postoff[2]); } static bool ilk_csc_limited_range(const struct intel_crtc_state *crtc_state) @@ -297,14 +309,16 @@ static void ilk_load_csc_matrix(const struct intel_crtc_state *crtc_state) * LUT is needed but CSC is not we need to load an * identity matrix. */ - WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_GEMINILAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_CANNONLAKE(dev_priv) && + !IS_GEMINILAKE(dev_priv)); ilk_update_pipe_csc(crtc, ilk_csc_off_zero, ilk_csc_coeff_identity, ilk_csc_off_zero); } - I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode); + intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe), + crtc_state->csc_mode); } static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) @@ -330,51 +344,74 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) ilk_csc_postoff_limited_range); } - I915_WRITE(PIPE_CSC_MODE(crtc->pipe), crtc_state->csc_mode); + intel_de_write(dev_priv, PIPE_CSC_MODE(crtc->pipe), + crtc_state->csc_mode); } -/* - * Set up the pipe CSC unit on CherryView. - */ -static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state) +static void chv_load_cgm_csc(struct intel_crtc *crtc, + const struct drm_property_blob *blob) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_color_ctm *ctm = blob->data; enum pipe pipe = crtc->pipe; + u16 coeffs[9]; + int i; - if (crtc_state->hw.ctm) { - const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; - u16 coeffs[9] = {}; - int i; - - for (i = 0; i < ARRAY_SIZE(coeffs); i++) { - u64 abs_coeff = - ((1ULL << 63) - 1) & ctm->matrix[i]; - - /* Round coefficient. */ - abs_coeff += 1 << (32 - 13); - /* Clamp to hardware limits. */ - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); - - /* Write coefficients in S3.12 format. */ - if (ctm->matrix[i] & (1ULL << 63)) - coeffs[i] = 1 << 15; - coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; - coeffs[i] |= (abs_coeff >> 20) & 0xfff; - } + for (i = 0; i < ARRAY_SIZE(coeffs); i++) { + u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; + + /* Round coefficient. */ + abs_coeff += 1 << (32 - 13); + /* Clamp to hardware limits. */ + abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); + + coeffs[i] = 0; + + /* Write coefficients in S3.12 format. */ + if (ctm->matrix[i] & (1ULL << 63)) + coeffs[i] |= 1 << 15; - I915_WRITE(CGM_PIPE_CSC_COEFF01(pipe), - coeffs[1] << 16 | coeffs[0]); - I915_WRITE(CGM_PIPE_CSC_COEFF23(pipe), - coeffs[3] << 16 | coeffs[2]); - I915_WRITE(CGM_PIPE_CSC_COEFF45(pipe), - coeffs[5] << 16 | coeffs[4]); - I915_WRITE(CGM_PIPE_CSC_COEFF67(pipe), - coeffs[7] << 16 | coeffs[6]); - I915_WRITE(CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]); + coeffs[i] |= ((abs_coeff >> 32) & 7) << 12; + coeffs[i] |= (abs_coeff >> 20) & 0xfff; } - I915_WRITE(CGM_PIPE_MODE(pipe), crtc_state->cgm_mode); + intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe), + coeffs[1] << 16 | coeffs[0]); + intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe), + coeffs[3] << 16 | coeffs[2]); + intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe), + coeffs[5] << 16 | coeffs[4]); + intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe), + coeffs[7] << 16 | coeffs[6]); + intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe), + coeffs[8]); +} + +/* convert hw value with given bit_precision to lut property val */ +static u32 intel_color_lut_pack(u32 val, int bit_precision) +{ + u32 max = 0xffff >> (16 - bit_precision); + + val = clamp_val(val, 0, max); + + if (bit_precision < 16) + val <<= 16 - bit_precision; + + return val; +} + +static u32 i9xx_lut_8(const struct drm_color_lut *color) +{ + return drm_color_lut_extract(color->red, 8) << 16 | + drm_color_lut_extract(color->green, 8) << 8 | + drm_color_lut_extract(color->blue, 8); +} + +static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val) +{ + entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8); + entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8); + entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8); } /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */ @@ -393,49 +430,34 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color) (color->blue >> 8); } -static u32 ilk_lut_10(const struct drm_color_lut *color) +static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) { - return drm_color_lut_extract(color->red, 10) << 20 | - drm_color_lut_extract(color->green, 10) << 10 | - drm_color_lut_extract(color->blue, 10); + entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 | + REG_FIELD_GET(PALETTE_RED_MASK, ldw); + entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 | + REG_FIELD_GET(PALETTE_GREEN_MASK, ldw); + entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 | + REG_FIELD_GET(PALETTE_BLUE_MASK, ldw); } -/* Loads the legacy palette/gamma unit for the CRTC. */ -static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state, - const struct drm_property_blob *blob) +static u16 i965_lut_11p6_max_pack(u32 val) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - int i; - - if (HAS_GMCH(dev_priv)) { - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) - assert_dsi_pll_enabled(dev_priv); - else - assert_pll_enabled(dev_priv, pipe); - } - - if (blob) { - const struct drm_color_lut *lut = blob->data; - - for (i = 0; i < 256; i++) { - u32 word = - (drm_color_lut_extract(lut[i].red, 8) << 16) | - (drm_color_lut_extract(lut[i].green, 8) << 8) | - drm_color_lut_extract(lut[i].blue, 8); + /* PIPEGCMAX is 11.6, clamp to 10.6 */ + return clamp_val(val, 0, 0xffff); +} - if (HAS_GMCH(dev_priv)) - I915_WRITE(PALETTE(pipe, i), word); - else - I915_WRITE(LGC_PALETTE(pipe, i), word); - } - } +static u32 ilk_lut_10(const struct drm_color_lut *color) +{ + return drm_color_lut_extract(color->red, 10) << 20 | + drm_color_lut_extract(color->green, 10) << 10 | + drm_color_lut_extract(color->blue, 10); } -static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) +static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val) { - i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut); + entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10); + entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10); + entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10); } static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) @@ -445,10 +467,10 @@ static void i9xx_color_commit(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; u32 val; - val = I915_READ(PIPECONF(pipe)); + val = intel_de_read(dev_priv, PIPECONF(pipe)); val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX; val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); - I915_WRITE(PIPECONF(pipe), val); + intel_de_write(dev_priv, PIPECONF(pipe), val); } static void ilk_color_commit(const struct intel_crtc_state *crtc_state) @@ -458,10 +480,10 @@ static void ilk_color_commit(const struct intel_crtc_state *crtc_state) enum pipe pipe = crtc->pipe; u32 val; - val = I915_READ(PIPECONF(pipe)); + val = intel_de_read(dev_priv, PIPECONF(pipe)); val &= ~PIPECONF_GAMMA_MODE_MASK_ILK; val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode); - I915_WRITE(PIPECONF(pipe), val); + intel_de_write(dev_priv, PIPECONF(pipe), val); ilk_load_csc_matrix(crtc_state); } @@ -471,7 +493,8 @@ static void hsw_color_commit(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode); + intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), + crtc_state->gamma_mode); ilk_load_csc_matrix(crtc_state); } @@ -492,9 +515,10 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE; if (crtc_state->csc_enable) val |= SKL_BOTTOM_COLOR_CSC_ENABLE; - I915_WRITE(SKL_BOTTOM_COLOR(pipe), val); + intel_de_write(dev_priv, SKL_BOTTOM_COLOR(pipe), val); - I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode); + intel_de_write(dev_priv, GAMMA_MODE(crtc->pipe), + crtc_state->gamma_mode); if (INTEL_GEN(dev_priv) >= 11) icl_load_csc_matrix(crtc_state); @@ -502,6 +526,35 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state) ilk_load_csc_matrix(crtc_state); } +static void i9xx_load_lut_8(struct intel_crtc *crtc, + const struct drm_property_blob *blob) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_color_lut *lut; + enum pipe pipe = crtc->pipe; + int i; + + if (!blob) + return; + + lut = blob->data; + + for (i = 0; i < 256; i++) + intel_de_write(dev_priv, PALETTE(pipe, i), + i9xx_lut_8(&lut[i])); +} + +static void i9xx_load_luts(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; + + assert_pll_enabled(dev_priv, crtc->pipe); + + i9xx_load_lut_8(crtc, gamma_lut); +} + static void i965_load_lut_10p6(struct intel_crtc *crtc, const struct drm_property_blob *blob) { @@ -511,28 +564,52 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size - 1; i++) { - I915_WRITE(PALETTE(pipe, 2 * i + 0), - i965_lut_10p6_ldw(&lut[i])); - I915_WRITE(PALETTE(pipe, 2 * i + 1), - i965_lut_10p6_udw(&lut[i])); + intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 0), + i965_lut_10p6_ldw(&lut[i])); + intel_de_write(dev_priv, PALETTE(pipe, 2 * i + 1), + i965_lut_10p6_udw(&lut[i])); } - I915_WRITE(PIPEGCMAX(pipe, 0), lut[i].red); - I915_WRITE(PIPEGCMAX(pipe, 1), lut[i].green); - I915_WRITE(PIPEGCMAX(pipe, 2), lut[i].blue); + intel_de_write(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); + intel_de_write(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); + intel_de_write(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); } static void i965_load_luts(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) + assert_dsi_pll_enabled(dev_priv); + else + assert_pll_enabled(dev_priv, crtc->pipe); + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) - i9xx_load_luts(crtc_state); + i9xx_load_lut_8(crtc, gamma_lut); else i965_load_lut_10p6(crtc, gamma_lut); } +static void ilk_load_lut_8(struct intel_crtc *crtc, + const struct drm_property_blob *blob) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_color_lut *lut; + enum pipe pipe = crtc->pipe; + int i; + + if (!blob) + return; + + lut = blob->data; + + for (i = 0; i < 256; i++) + intel_de_write(dev_priv, LGC_PALETTE(pipe, i), + i9xx_lut_8(&lut[i])); +} + static void ilk_load_lut_10(struct intel_crtc *crtc, const struct drm_property_blob *blob) { @@ -542,7 +619,8 @@ static void ilk_load_lut_10(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size; i++) - I915_WRITE(PREC_PALETTE(pipe, i), ilk_lut_10(&lut[i])); + intel_de_write(dev_priv, PREC_PALETTE(pipe, i), + ilk_lut_10(&lut[i])); } static void ilk_load_luts(const struct intel_crtc_state *crtc_state) @@ -551,7 +629,7 @@ static void ilk_load_luts(const struct intel_crtc_state *crtc_state) const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) - i9xx_load_luts(crtc_state); + ilk_load_lut_8(crtc, gamma_lut); else ilk_load_lut_10(crtc, gamma_lut); } @@ -584,15 +662,16 @@ static void ivb_load_lut_10(struct intel_crtc *crtc, const struct drm_color_lut *entry = &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; - I915_WRITE(PREC_PAL_INDEX(pipe), prec_index++); - I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry)); + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), prec_index++); + intel_de_write(dev_priv, PREC_PAL_DATA(pipe), + ilk_lut_10(entry)); } /* * Reset the index, otherwise it prevents the legacy palette to be * written properly. */ - I915_WRITE(PREC_PAL_INDEX(pipe), 0); + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); } /* On BDW+ the index auto increment mode actually works */ @@ -606,22 +685,23 @@ static void bdw_load_lut_10(struct intel_crtc *crtc, int i, lut_size = drm_color_lut_size(blob); enum pipe pipe = crtc->pipe; - I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | - PAL_PREC_AUTO_INCREMENT); + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), + prec_index | PAL_PREC_AUTO_INCREMENT); for (i = 0; i < hw_lut_size; i++) { /* We discard half the user entries in split gamma mode */ const struct drm_color_lut *entry = &lut[i * (lut_size - 1) / (hw_lut_size - 1)]; - I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_10(entry)); + intel_de_write(dev_priv, PREC_PAL_DATA(pipe), + ilk_lut_10(entry)); } /* * Reset the index, otherwise it prevents the legacy palette to be * written properly. */ - I915_WRITE(PREC_PAL_INDEX(pipe), 0); + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); } static void ivb_load_lut_ext_max(struct intel_crtc *crtc) @@ -659,7 +739,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state) const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { - i9xx_load_luts(crtc_state); + ilk_load_lut_8(crtc, gamma_lut); } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); @@ -682,7 +762,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state) const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { - i9xx_load_luts(crtc_state); + ilk_load_lut_8(crtc, gamma_lut); } else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) { bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE | PAL_PREC_INDEX_VALUE(0)); @@ -703,17 +783,17 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; + int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data; - u32 i; /* * When setting the auto-increment bit, the hardware seems to * ignore the index bits, so we need to reset it to index 0 * separately. */ - I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0); - I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT); + intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); + intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), + PRE_CSC_GAMC_AUTO_INCREMENT); for (i = 0; i < lut_size; i++) { /* @@ -729,12 +809,13 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state) * ToDo: Extend to max 7.0. Enable 32 bit input value * as compared to just 16 to achieve this. */ - I915_WRITE(PRE_CSC_GAMC_DATA(pipe), lut[i].green); + intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), + lut[i].green); } /* Clamp values > 1.0. */ while (i++ < 35) - I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16); + intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); } static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_state) @@ -742,26 +823,26 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; - u32 i; + int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; /* * When setting the auto-increment bit, the hardware seems to * ignore the index bits, so we need to reset it to index 0 * separately. */ - I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0); - I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT); + intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), 0); + intel_de_write(dev_priv, PRE_CSC_GAMC_INDEX(pipe), + PRE_CSC_GAMC_AUTO_INCREMENT); for (i = 0; i < lut_size; i++) { u32 v = (i << 16) / (lut_size - 1); - I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v); + intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), v); } /* Clamp values > 1.0. */ while (i++ < 35) - I915_WRITE(PRE_CSC_GAMC_DATA(pipe), 1 << 16); + intel_de_write(dev_priv, PRE_CSC_GAMC_DATA(pipe), 1 << 16); } static void glk_load_luts(const struct intel_crtc_state *crtc_state) @@ -783,7 +864,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state) glk_load_degamma_lut_linear(crtc_state); if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) { - i9xx_load_luts(crtc_state); + ilk_load_lut_8(crtc, gamma_lut); } else { bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0)); ivb_load_lut_ext_max(crtc); @@ -827,7 +908,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state) const struct drm_color_lut *lut = blob->data; struct intel_dsb *dsb = intel_dsb_get(crtc); enum pipe pipe = crtc->pipe; - u32 i; + int i; /* * Program Super Fine segment (let's call it seg1)... @@ -860,7 +941,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state) const struct drm_color_lut *entry; struct intel_dsb *dsb = intel_dsb_get(crtc); enum pipe pipe = crtc->pipe; - u32 i; + int i; /* * Program Fine segment (let's call it seg2)... @@ -919,7 +1000,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { case GAMMA_MODE_MODE_8BIT: - i9xx_load_luts(crtc_state); + ilk_load_lut_8(crtc, gamma_lut); break; case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED: icl_program_gamma_superfine_segment(crtc_state); @@ -945,6 +1026,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color) return drm_color_lut_extract(color->red, 14); } +static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw) +{ + entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10); + entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10); + entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10); +} + static void chv_load_cgm_degamma(struct intel_crtc *crtc, const struct drm_property_blob *blob) { @@ -954,10 +1042,10 @@ static void chv_load_cgm_degamma(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size; i++) { - I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 0), - chv_cgm_degamma_ldw(&lut[i])); - I915_WRITE(CGM_PIPE_DEGAMMA(pipe, i, 1), - chv_cgm_degamma_udw(&lut[i])); + intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 0), + chv_cgm_degamma_ldw(&lut[i])); + intel_de_write(dev_priv, CGM_PIPE_DEGAMMA(pipe, i, 1), + chv_cgm_degamma_udw(&lut[i])); } } @@ -981,31 +1069,34 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size; i++) { - I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 0), - chv_cgm_gamma_ldw(&lut[i])); - I915_WRITE(CGM_PIPE_GAMMA(pipe, i, 1), - chv_cgm_gamma_udw(&lut[i])); + intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0), + chv_cgm_gamma_ldw(&lut[i])); + intel_de_write(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1), + chv_cgm_gamma_udw(&lut[i])); } } static void chv_load_luts(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut; + const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut; + const struct drm_property_blob *ctm = crtc_state->hw.ctm; - cherryview_load_csc_matrix(crtc_state); + if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) + chv_load_cgm_csc(crtc, ctm); - if (crtc_state_is_legacy_gamma(crtc_state)) { - i9xx_load_luts(crtc_state); - return; - } - - if (degamma_lut) + if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA) chv_load_cgm_degamma(crtc, degamma_lut); - if (gamma_lut) + if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) chv_load_cgm_gamma(crtc, gamma_lut); + else + i965_load_luts(crtc_state); + + intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe), + crtc_state->cgm_mode); } void intel_color_load_luts(const struct intel_crtc_state *crtc_state) @@ -1167,7 +1258,8 @@ static int check_luts(const struct intel_crtc_state *crtc_state) /* C8 relies on its palette being stored in the legacy LUT */ if (crtc_state->c8_planes) { - DRM_DEBUG_KMS("C8 pixelformat requires the legacy LUT\n"); + drm_dbg_kms(&dev_priv->drm, + "C8 pixelformat requires the legacy LUT\n"); return -EINVAL; } @@ -1630,28 +1722,13 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1, return true; } -/* convert hw value with given bit_precision to lut property val */ -static u32 intel_color_lut_pack(u32 val, u32 bit_precision) +static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) { - u32 max = 0xffff >> (16 - bit_precision); - - val = clamp_val(val, 0, max); - - if (bit_precision < 16) - val <<= 16 - bit_precision; - - return val; -} - -static struct drm_property_blob * -i9xx_read_lut_8(const struct intel_crtc_state *crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; - u32 i, val; + struct drm_color_lut *lut; + int i; blob = drm_property_create_blob(&dev_priv->drm, sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, @@ -1659,20 +1736,12 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < LEGACY_LUT_LENGTH; i++) { - if (HAS_GMCH(dev_priv)) - val = I915_READ(PALETTE(pipe, i)); - else - val = I915_READ(LGC_PALETTE(pipe, i)); - - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( - LGC_PALETTE_RED_MASK, val), 8); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( - LGC_PALETTE_GREEN_MASK, val), 8); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( - LGC_PALETTE_BLUE_MASK, val), 8); + u32 val = intel_de_read(dev_priv, PALETTE(pipe, i)); + + i9xx_lut_8_pack(&lut[i], val); } return blob; @@ -1680,22 +1749,21 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state) static void i9xx_read_luts(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + if (!crtc_state->gamma_enable) return; - crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state); + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); } -static struct drm_property_blob * -i965_read_lut_10p6(const struct intel_crtc_state *crtc_state) +static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; - u32 i, val1, val2; + struct drm_color_lut *lut; blob = drm_property_create_blob(&dev_priv->drm, sizeof(struct drm_color_lut) * lut_size, @@ -1703,51 +1771,42 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < lut_size - 1; i++) { - val1 = I915_READ(PALETTE(pipe, 2 * i + 0)); - val2 = I915_READ(PALETTE(pipe, 2 * i + 1)); - - blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 | - REG_FIELD_GET(PALETTE_RED_MASK, val1); - blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 | - REG_FIELD_GET(PALETTE_GREEN_MASK, val1); - blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 | - REG_FIELD_GET(PALETTE_BLUE_MASK, val1); + u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0)); + u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1)); + + i965_lut_10p6_pack(&lut[i], ldw, udw); } - blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, - I915_READ(PIPEGCMAX(pipe, 0))); - blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, - I915_READ(PIPEGCMAX(pipe, 1))); - blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK, - I915_READ(PIPEGCMAX(pipe, 2))); + lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0))); + lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1))); + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2))); return blob; } static void i965_read_luts(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + if (!crtc_state->gamma_enable) return; if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) - crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state); + crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc); else - crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state); + crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc); } -static struct drm_property_blob * -chv_read_cgm_lut(const struct intel_crtc_state *crtc_state) +static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; - u32 i, val; + struct drm_color_lut *lut; blob = drm_property_create_blob(&dev_priv->drm, sizeof(struct drm_color_lut) * lut_size, @@ -1755,18 +1814,13 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < lut_size; i++) { - val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 0)); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( - CGM_PIPE_GAMMA_GREEN_MASK, val), 10); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( - CGM_PIPE_GAMMA_BLUE_MASK, val), 10); - - val = I915_READ(CGM_PIPE_GAMMA(pipe, i, 1)); - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( - CGM_PIPE_GAMMA_RED_MASK, val), 10); + u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0)); + u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1)); + + chv_cgm_gamma_pack(&lut[i], ldw, udw); } return blob; @@ -1774,22 +1828,46 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state) static void chv_read_luts(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA) - crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state); + crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc); else i965_read_luts(crtc_state); } -static struct drm_property_blob * -ilk_read_lut_10(const struct intel_crtc_state *crtc_state) +static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + struct drm_property_blob *blob; + struct drm_color_lut *lut; + int i; + + blob = drm_property_create_blob(&dev_priv->drm, + sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH, + NULL); + if (IS_ERR(blob)) + return NULL; + + lut = blob->data; + + for (i = 0; i < LEGACY_LUT_LENGTH; i++) { + u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i)); + + i9xx_lut_8_pack(&lut[i], val); + } + + return blob; +} + +static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; - u32 i, val; + struct drm_color_lut *lut; blob = drm_property_create_blob(&dev_priv->drm, sizeof(struct drm_color_lut) * lut_size, @@ -1797,17 +1875,12 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; for (i = 0; i < lut_size; i++) { - val = I915_READ(PREC_PALETTE(pipe, i)); - - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( - PREC_PALETTE_RED_MASK, val), 10); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( - PREC_PALETTE_GREEN_MASK, val), 10); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( - PREC_PALETTE_BLUE_MASK, val), 10); + u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i)); + + ilk_lut_10_pack(&lut[i], val); } return blob; @@ -1815,6 +1888,8 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state) static void ilk_read_luts(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + if (!crtc_state->gamma_enable) return; @@ -1822,21 +1897,19 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state) return; if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) - crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state); + crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); else - crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state); + crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc); } -static struct drm_property_blob * -glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index) +static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc, + u32 prec_index) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - int hw_lut_size = ivb_lut_10_size(prec_index); + int i, hw_lut_size = ivb_lut_10_size(prec_index); enum pipe pipe = crtc->pipe; struct drm_property_blob *blob; - struct drm_color_lut *blob_data; - u32 i, val; + struct drm_color_lut *lut; blob = drm_property_create_blob(&dev_priv->drm, sizeof(struct drm_color_lut) * hw_lut_size, @@ -1844,36 +1917,33 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index) if (IS_ERR(blob)) return NULL; - blob_data = blob->data; + lut = blob->data; - I915_WRITE(PREC_PAL_INDEX(pipe), prec_index | - PAL_PREC_AUTO_INCREMENT); + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), + prec_index | PAL_PREC_AUTO_INCREMENT); for (i = 0; i < hw_lut_size; i++) { - val = I915_READ(PREC_PAL_DATA(pipe)); - - blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET( - PREC_PAL_DATA_RED_MASK, val), 10); - blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET( - PREC_PAL_DATA_GREEN_MASK, val), 10); - blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET( - PREC_PAL_DATA_BLUE_MASK, val), 10); + u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe)); + + ilk_lut_10_pack(&lut[i], val); } - I915_WRITE(PREC_PAL_INDEX(pipe), 0); + intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0); return blob; } static void glk_read_luts(struct intel_crtc_state *crtc_state) { + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + if (!crtc_state->gamma_enable) return; if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) - crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state); + crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc); else - crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0)); + crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0)); } void intel_color_init(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c b/drivers/gpu/drm/i915/display/intel_combo_phy.c index 44bbc7e74fc3..9ff05ec12115 100644 --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c @@ -48,7 +48,7 @@ cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) const struct cnl_procmon *procmon; u32 val; - val = I915_READ(ICL_PORT_COMP_DW3(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) { default: MISSING_CASE(val); @@ -81,26 +81,27 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, procmon = cnl_get_procmon_ref_values(dev_priv, phy); - val = I915_READ(ICL_PORT_COMP_DW1(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); val &= ~((0xff << 16) | 0xff); val |= procmon->dw1; - I915_WRITE(ICL_PORT_COMP_DW1(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW1(phy), val); - I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); - I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); + intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); + intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); } static bool check_phy_reg(struct drm_i915_private *dev_priv, enum phy phy, i915_reg_t reg, u32 mask, u32 expected_val) { - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); if ((val & mask) != expected_val) { - DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch: " - "current %08x mask %08x expected %08x\n", - phy_name(phy), - reg.reg, val, mask, expected_val); + drm_dbg(&dev_priv->drm, + "Combo PHY %c reg %08x state mismatch: " + "current %08x mask %08x expected %08x\n", + phy_name(phy), + reg.reg, val, mask, expected_val); return false; } @@ -127,8 +128,8 @@ static bool cnl_verify_procmon_ref_values(struct drm_i915_private *dev_priv, static bool cnl_combo_phy_enabled(struct drm_i915_private *dev_priv) { - return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && - (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT); + return !(intel_de_read(dev_priv, CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) && + (intel_de_read(dev_priv, CNL_PORT_COMP_DW0) & COMP_INIT); } static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv) @@ -151,20 +152,20 @@ static void cnl_combo_phys_init(struct drm_i915_private *dev_priv) { u32 val; - val = I915_READ(CHICKEN_MISC_2); + val = intel_de_read(dev_priv, CHICKEN_MISC_2); val &= ~CNL_COMP_PWR_DOWN; - I915_WRITE(CHICKEN_MISC_2, val); + intel_de_write(dev_priv, CHICKEN_MISC_2, val); /* Dummy PORT_A to get the correct CNL register from the ICL macro */ cnl_set_procmon_ref_values(dev_priv, PHY_A); - val = I915_READ(CNL_PORT_COMP_DW0); + val = intel_de_read(dev_priv, CNL_PORT_COMP_DW0); val |= COMP_INIT; - I915_WRITE(CNL_PORT_COMP_DW0, val); + intel_de_write(dev_priv, CNL_PORT_COMP_DW0, val); - val = I915_READ(CNL_PORT_CL1CM_DW5); + val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); val |= CL_POWER_DOWN_ENABLE; - I915_WRITE(CNL_PORT_CL1CM_DW5, val); + intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); } static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) @@ -172,11 +173,12 @@ static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) u32 val; if (!cnl_combo_phy_verify_state(dev_priv)) - DRM_WARN("Combo PHY HW state changed unexpectedly.\n"); + drm_warn(&dev_priv->drm, + "Combo PHY HW state changed unexpectedly.\n"); - val = I915_READ(CHICKEN_MISC_2); + val = intel_de_read(dev_priv, CHICKEN_MISC_2); val |= CNL_COMP_PWR_DOWN; - I915_WRITE(CHICKEN_MISC_2, val); + intel_de_write(dev_priv, CHICKEN_MISC_2, val); } static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, @@ -184,27 +186,65 @@ static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv, { /* The PHY C added by EHL has no PHY_MISC register */ if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) - return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT; + return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; else - return !(I915_READ(ICL_PHY_MISC(phy)) & + return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) && - (I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT); + (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); +} + +static bool ehl_vbt_ddi_d_present(struct drm_i915_private *i915) +{ + bool ddi_a_present = intel_bios_is_port_present(i915, PORT_A); + bool ddi_d_present = intel_bios_is_port_present(i915, PORT_D); + bool dsi_present = intel_bios_is_dsi_present(i915, NULL); + + /* + * VBT's 'dvo port' field for child devices references the DDI, not + * the PHY. So if combo PHY A is wired up to drive an external + * display, we should see a child device present on PORT_D and + * nothing on PORT_A and no DSI. + */ + if (ddi_d_present && !ddi_a_present && !dsi_present) + return true; + + /* + * If we encounter a VBT that claims to have an external display on + * DDI-D _and_ an internal display on DDI-A/DSI leave an error message + * in the log and let the internal display win. + */ + if (ddi_d_present) + drm_err(&i915->drm, + "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); + + return false; } static bool icl_combo_phy_verify_state(struct drm_i915_private *dev_priv, enum phy phy) { bool ret; + u32 expected_val = 0; if (!icl_combo_phy_enabled(dev_priv, phy)) return false; ret = cnl_verify_procmon_ref_values(dev_priv, phy); - if (phy == PHY_A) + if (phy == PHY_A) { ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), IREFGEN, IREFGEN); + if (IS_ELKHARTLAKE(dev_priv)) { + if (ehl_vbt_ddi_d_present(dev_priv)) + expected_val = ICL_PHY_MISC_MUX_DDID; + + ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), + ICL_PHY_MISC_MUX_DDID, + expected_val); + } + } + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), CL_POWER_DOWN_ENABLE, CL_POWER_DOWN_ENABLE); @@ -219,7 +259,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, u32 val; if (is_dsi) { - WARN_ON(lane_reversal); + drm_WARN_ON(&dev_priv->drm, lane_reversal); switch (lane_count) { case 1: @@ -257,36 +297,10 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, } } - val = I915_READ(ICL_PORT_CL_DW10(phy)); + val = intel_de_read(dev_priv, ICL_PORT_CL_DW10(phy)); val &= ~PWR_DOWN_LN_MASK; val |= lane_mask << PWR_DOWN_LN_SHIFT; - I915_WRITE(ICL_PORT_CL_DW10(phy), val); -} - -static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32 val) -{ - bool ddi_a_present = i915->vbt.ddi_port_info[PORT_A].child != NULL; - bool ddi_d_present = i915->vbt.ddi_port_info[PORT_D].child != NULL; - bool dsi_present = intel_bios_is_dsi_present(i915, NULL); - - /* - * VBT's 'dvo port' field for child devices references the DDI, not - * the PHY. So if combo PHY A is wired up to drive an external - * display, we should see a child device present on PORT_D and - * nothing on PORT_A and no DSI. - */ - if (ddi_d_present && !ddi_a_present && !dsi_present) - return val | ICL_PHY_MISC_MUX_DDID; - - /* - * If we encounter a VBT that claims to have an external display on - * DDI-D _and_ an internal display on DDI-A/DSI leave an error message - * in the log and let the internal display win. - */ - if (ddi_d_present) - DRM_ERROR("VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); - - return val & ~ICL_PHY_MISC_MUX_DDID; + intel_de_write(dev_priv, ICL_PORT_CL_DW10(phy), val); } static void icl_combo_phys_init(struct drm_i915_private *dev_priv) @@ -297,8 +311,9 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) u32 val; if (icl_combo_phy_verify_state(dev_priv, phy)) { - DRM_DEBUG_DRIVER("Combo PHY %c already enabled, won't reprogram it.\n", - phy_name(phy)); + drm_dbg(&dev_priv->drm, + "Combo PHY %c already enabled, won't reprogram it.\n", + phy_name(phy)); continue; } @@ -318,28 +333,33 @@ static void icl_combo_phys_init(struct drm_i915_private *dev_priv) * based on whether our VBT indicates the presence of any * "internal" child devices. */ - val = I915_READ(ICL_PHY_MISC(phy)); - if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) - val = ehl_combo_phy_a_mux(dev_priv, val); + val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A) { + val &= ~ICL_PHY_MISC_MUX_DDID; + + if (ehl_vbt_ddi_d_present(dev_priv)) + val |= ICL_PHY_MISC_MUX_DDID; + } + val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; - I915_WRITE(ICL_PHY_MISC(phy), val); + intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); skip_phy_misc: cnl_set_procmon_ref_values(dev_priv, phy); if (phy == PHY_A) { - val = I915_READ(ICL_PORT_COMP_DW8(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW8(phy)); val |= IREFGEN; - I915_WRITE(ICL_PORT_COMP_DW8(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW8(phy), val); } - val = I915_READ(ICL_PORT_COMP_DW0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); val |= COMP_INIT; - I915_WRITE(ICL_PORT_COMP_DW0(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); - val = I915_READ(ICL_PORT_CL_DW5(phy)); + val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= CL_POWER_DOWN_ENABLE; - I915_WRITE(ICL_PORT_CL_DW5(phy), val); + intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); } } @@ -352,7 +372,8 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) if (phy == PHY_A && !icl_combo_phy_verify_state(dev_priv, phy)) - DRM_WARN("Combo PHY %c HW state changed unexpectedly\n", + drm_warn(&dev_priv->drm, + "Combo PHY %c HW state changed unexpectedly\n", phy_name(phy)); /* @@ -363,14 +384,14 @@ static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_C) goto skip_phy_misc; - val = I915_READ(ICL_PHY_MISC(phy)); + val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN; - I915_WRITE(ICL_PHY_MISC(phy), val); + intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); skip_phy_misc: - val = I915_READ(ICL_PORT_COMP_DW0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)); val &= ~COMP_INIT; - I915_WRITE(ICL_PORT_COMP_DW0(phy), val); + intel_de_write(dev_priv, ICL_PORT_COMP_DW0(phy), val); } } diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c index 1133c4e97bb4..903e49659f56 100644 --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c @@ -153,7 +153,7 @@ void intel_connector_attach_encoder(struct intel_connector *connector, bool intel_connector_get_hw_state(struct intel_connector *connector) { enum pipe pipe = 0; - struct intel_encoder *encoder = connector->encoder; + struct intel_encoder *encoder = intel_attached_encoder(connector); return encoder->get_hw_state(encoder, &pipe); } @@ -162,7 +162,8 @@ enum pipe intel_connector_get_pipe(struct intel_connector *connector) { struct drm_device *dev = connector->base.dev; - WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + drm_WARN_ON(dev, + !drm_modeset_is_locked(&dev->mode_config.connection_mutex)); if (!connector->base.state->crtc) return INVALID_PIPE; diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index f976b800b245..78f9b6cde810 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -32,7 +32,6 @@ #include <drm/drm_crtc.h> #include <drm/drm_edid.h> #include <drm/drm_probe_helper.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "intel_connector.h" @@ -75,7 +74,7 @@ bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(adpa_reg); + val = intel_de_read(dev_priv, adpa_reg); /* asserts want to know the pipe even if the port is disabled */ if (HAS_PCH_CPT(dev_priv)) @@ -112,7 +111,7 @@ static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) struct intel_crt *crt = intel_encoder_to_crt(encoder); u32 tmp, flags = 0; - tmp = I915_READ(crt->adpa_reg); + tmp = intel_de_read(dev_priv, crt->adpa_reg); if (tmp & ADPA_HSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; @@ -184,7 +183,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, adpa |= ADPA_PIPE_SEL(crtc->pipe); if (!HAS_PCH_SPLIT(dev_priv)) - I915_WRITE(BCLRPAT(crtc->pipe), 0); + intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); switch (mode) { case DRM_MODE_DPMS_ON: @@ -201,7 +200,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, break; } - I915_WRITE(crt->adpa_reg, adpa); + intel_de_write(dev_priv, crt->adpa_reg, adpa); } static void intel_disable_crt(struct intel_encoder *encoder, @@ -230,7 +229,7 @@ static void hsw_disable_crt(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - WARN_ON(!old_crtc_state->has_pch_encoder); + drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); } @@ -258,7 +257,7 @@ static void hsw_post_disable_crt(struct intel_encoder *encoder, intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); - WARN_ON(!old_crtc_state->has_pch_encoder); + drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); } @@ -269,7 +268,7 @@ static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - WARN_ON(!crtc_state->has_pch_encoder); + drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); } @@ -282,7 +281,7 @@ static void hsw_pre_enable_crt(struct intel_encoder *encoder, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; - WARN_ON(!crtc_state->has_pch_encoder); + drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); @@ -299,7 +298,13 @@ static void hsw_enable_crt(struct intel_encoder *encoder, struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum pipe pipe = crtc->pipe; - WARN_ON(!crtc_state->has_pch_encoder); + drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); + + intel_enable_pipe(crtc_state); + + lpt_pch_enable(crtc_state); + + intel_crtc_vblank_on(crtc_state); intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); @@ -414,7 +419,8 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder, /* LPT FDI RX only supports 8bpc. */ if (HAS_PCH_LPT(dev_priv)) { if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { - DRM_DEBUG_KMS("LPT only supports 24bpp\n"); + drm_dbg_kms(&dev_priv->drm, + "LPT only supports 24bpp\n"); return -EINVAL; } @@ -442,34 +448,37 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector) crt->force_hotplug_required = false; - save_adpa = adpa = I915_READ(crt->adpa_reg); - DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); + save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); + drm_dbg_kms(&dev_priv->drm, + "trigger hotplug detect cycle: adpa=0x%x\n", adpa); adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; if (turn_off_dac) adpa &= ~ADPA_DAC_ENABLE; - I915_WRITE(crt->adpa_reg, adpa); + intel_de_write(dev_priv, crt->adpa_reg, adpa); if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) - DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); + drm_dbg_kms(&dev_priv->drm, + "timed out waiting for FORCE_TRIGGER"); if (turn_off_dac) { - I915_WRITE(crt->adpa_reg, save_adpa); - POSTING_READ(crt->adpa_reg); + intel_de_write(dev_priv, crt->adpa_reg, save_adpa); + intel_de_posting_read(dev_priv, crt->adpa_reg); } } /* Check the status to see if both blue and green are on now */ - adpa = I915_READ(crt->adpa_reg); + adpa = intel_de_read(dev_priv, crt->adpa_reg); if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) ret = true; else ret = false; - DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); + drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", + adpa, ret); return ret; } @@ -498,27 +507,30 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) */ reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); - save_adpa = adpa = I915_READ(crt->adpa_reg); - DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); + save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); + drm_dbg_kms(&dev_priv->drm, + "trigger hotplug detect cycle: adpa=0x%x\n", adpa); adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; - I915_WRITE(crt->adpa_reg, adpa); + intel_de_write(dev_priv, crt->adpa_reg, adpa); if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { - DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); - I915_WRITE(crt->adpa_reg, save_adpa); + drm_dbg_kms(&dev_priv->drm, + "timed out waiting for FORCE_TRIGGER"); + intel_de_write(dev_priv, crt->adpa_reg, save_adpa); } /* Check the status to see if both blue and green are on now */ - adpa = I915_READ(crt->adpa_reg); + adpa = intel_de_read(dev_priv, crt->adpa_reg); if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) ret = true; else ret = false; - DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); + drm_dbg_kms(&dev_priv->drm, + "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); if (reenable_hpd) intel_hpd_enable(dev_priv, crt->base.hpd_pin); @@ -558,15 +570,16 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) /* wait for FORCE_DETECT to go off */ if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, CRT_HOTPLUG_FORCE_DETECT, 1000)) - DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); + drm_dbg_kms(&dev_priv->drm, + "timed out waiting for FORCE_DETECT to go off"); } - stat = I915_READ(PORT_HOTPLUG_STAT); + stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) ret = true; /* clear the interrupt we just generated, if any */ - I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); + intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); @@ -629,13 +642,16 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) * have to check the EDID input spec of the attached device. */ if (!is_digital) { - DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); + drm_dbg_kms(&dev_priv->drm, + "CRT detected via DDC:0x50 [EDID]\n"); ret = true; } else { - DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); + drm_dbg_kms(&dev_priv->drm, + "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); } } else { - DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); + drm_dbg_kms(&dev_priv->drm, + "CRT not detected via DDC:0x50 [no valid EDID found]\n"); } kfree(edid); @@ -660,7 +676,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe) u8 st00; enum drm_connector_status status; - DRM_DEBUG_KMS("starting load-detect on CRT\n"); + drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); bclrpat_reg = BCLRPAT(pipe); vtotal_reg = VTOTAL(pipe); @@ -706,7 +722,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe) * Yes, this will flicker */ if (vblank_start <= vactive && vblank_end >= vtotal) { - u32 vsync = I915_READ(vsync_reg); + u32 vsync = intel_de_read(dev_priv, vsync_reg); u32 vsync_start = (vsync & 0xffff) + 1; vblank_start = vsync_start; @@ -801,9 +817,9 @@ intel_crt_detect(struct drm_connector *connector, int status, ret; struct intel_load_detect_pipe tmp; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", - connector->base.id, connector->name, - force); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", + connector->base.id, connector->name, + force); if (i915_modparams.load_detect_test) { wakeref = intel_display_power_get(dev_priv, @@ -824,11 +840,13 @@ intel_crt_detect(struct drm_connector *connector, * only trust an assertion that the monitor is connected. */ if (intel_crt_detect_hotplug(connector)) { - DRM_DEBUG_KMS("CRT detected via hotplug\n"); + drm_dbg_kms(&dev_priv->drm, + "CRT detected via hotplug\n"); status = connector_status_connected; goto out; } else - DRM_DEBUG_KMS("CRT not detected via hotplug\n"); + drm_dbg_kms(&dev_priv->drm, + "CRT not detected via hotplug\n"); } if (intel_crt_detect_ddc(connector)) { @@ -918,13 +936,13 @@ void intel_crt_reset(struct drm_encoder *encoder) if (INTEL_GEN(dev_priv) >= 5) { u32 adpa; - adpa = I915_READ(crt->adpa_reg); + adpa = intel_de_read(dev_priv, crt->adpa_reg); adpa &= ~ADPA_CRT_HOTPLUG_MASK; adpa |= ADPA_HOTPLUG_BITS; - I915_WRITE(crt->adpa_reg, adpa); - POSTING_READ(crt->adpa_reg); + intel_de_write(dev_priv, crt->adpa_reg, adpa); + intel_de_posting_read(dev_priv, crt->adpa_reg); - DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); + drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); crt->force_hotplug_required = true; } @@ -969,7 +987,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv) else adpa_reg = ADPA; - adpa = I915_READ(adpa_reg); + adpa = intel_de_read(dev_priv, adpa_reg); if ((adpa & ADPA_DAC_ENABLE) == 0) { /* * On some machines (some IVB at least) CRT can be @@ -979,11 +997,11 @@ void intel_crt_init(struct drm_i915_private *dev_priv) * take. So the only way to tell is attempt to enable * it and see what happens. */ - I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | - ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); - if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) + intel_de_write(dev_priv, adpa_reg, + adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); + if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0) return; - I915_WRITE(adpa_reg, adpa); + intel_de_write(dev_priv, adpa_reg, adpa); } crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); @@ -1027,6 +1045,9 @@ void intel_crt_init(struct drm_i915_private *dev_priv) !dmi_check_system(intel_spurious_crt_detect)) { crt->base.hpd_pin = HPD_CRT; crt->base.hotplug = intel_encoder_hotplug; + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; + } else { + intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; } if (HAS_DDI(dev_priv)) { @@ -1057,14 +1078,6 @@ void intel_crt_init(struct drm_i915_private *dev_priv) drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); - if (!I915_HAS_HOTPLUG(dev_priv)) - intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; - - /* - * Configure the automatic hotplug detection stuff - */ - crt->force_hotplug_required = false; - /* * TODO: find a proper way to discover whether we need to set the the * polarity and link reversal bits or not, instead of relying on the @@ -1074,7 +1087,8 @@ void intel_crt_init(struct drm_i915_private *dev_priv) u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | FDI_RX_LINK_REVERSAL_OVERRIDE; - dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; + dev_priv->fdi_rx_config = intel_de_read(dev_priv, + FDI_RX_CTL(PIPE_A)) & fdi_config; } intel_crt_reset(&crt->base.base); diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c new file mode 100644 index 000000000000..3112572cfb7d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_csr.c @@ -0,0 +1,795 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include <linux/firmware.h> + +#include "i915_drv.h" +#include "i915_reg.h" +#include "intel_csr.h" +#include "intel_de.h" + +/** + * DOC: csr support for dmc + * + * Display Context Save and Restore (CSR) firmware support added from gen9 + * onwards to drive newly added DMC (Display microcontroller) in display + * engine to save and restore the state of display engine when it enter into + * low-power state and comes back to normal. + */ + +#define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE + +#define TGL_CSR_PATH "i915/tgl_dmc_ver2_06.bin" +#define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 6) +#define TGL_CSR_MAX_FW_SIZE 0x6000 +MODULE_FIRMWARE(TGL_CSR_PATH); + +#define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin" +#define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9) +#define ICL_CSR_MAX_FW_SIZE 0x6000 +MODULE_FIRMWARE(ICL_CSR_PATH); + +#define CNL_CSR_PATH "i915/cnl_dmc_ver1_07.bin" +#define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) +#define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE +MODULE_FIRMWARE(CNL_CSR_PATH); + +#define GLK_CSR_PATH "i915/glk_dmc_ver1_04.bin" +#define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) +#define GLK_CSR_MAX_FW_SIZE 0x4000 +MODULE_FIRMWARE(GLK_CSR_PATH); + +#define KBL_CSR_PATH "i915/kbl_dmc_ver1_04.bin" +#define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) +#define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE +MODULE_FIRMWARE(KBL_CSR_PATH); + +#define SKL_CSR_PATH "i915/skl_dmc_ver1_27.bin" +#define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27) +#define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE +MODULE_FIRMWARE(SKL_CSR_PATH); + +#define BXT_CSR_PATH "i915/bxt_dmc_ver1_07.bin" +#define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) +#define BXT_CSR_MAX_FW_SIZE 0x3000 +MODULE_FIRMWARE(BXT_CSR_PATH); + +#define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF +#define PACKAGE_MAX_FW_INFO_ENTRIES 20 +#define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 +#define DMC_V1_MAX_MMIO_COUNT 8 +#define DMC_V3_MAX_MMIO_COUNT 20 + +struct intel_css_header { + /* 0x09 for DMC */ + u32 module_type; + + /* Includes the DMC specific header in dwords */ + u32 header_len; + + /* always value would be 0x10000 */ + u32 header_ver; + + /* Not used */ + u32 module_id; + + /* Not used */ + u32 module_vendor; + + /* in YYYYMMDD format */ + u32 date; + + /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ + u32 size; + + /* Not used */ + u32 key_size; + + /* Not used */ + u32 modulus_size; + + /* Not used */ + u32 exponent_size; + + /* Not used */ + u32 reserved1[12]; + + /* Major Minor */ + u32 version; + + /* Not used */ + u32 reserved2[8]; + + /* Not used */ + u32 kernel_header_info; +} __packed; + +struct intel_fw_info { + u8 reserved1; + + /* reserved on package_header version 1, must be 0 on version 2 */ + u8 dmc_id; + + /* Stepping (A, B, C, ..., *). * is a wildcard */ + char stepping; + + /* Sub-stepping (0, 1, ..., *). * is a wildcard */ + char substepping; + + u32 offset; + u32 reserved2; +} __packed; + +struct intel_package_header { + /* DMC container header length in dwords */ + u8 header_len; + + /* 0x01, 0x02 */ + u8 header_ver; + + u8 reserved[10]; + + /* Number of valid entries in the FWInfo array below */ + u32 num_entries; +} __packed; + +struct intel_dmc_header_base { + /* always value would be 0x40403E3E */ + u32 signature; + + /* DMC binary header length */ + u8 header_len; + + /* 0x01 */ + u8 header_ver; + + /* Reserved */ + u16 dmcc_ver; + + /* Major, Minor */ + u32 project; + + /* Firmware program size (excluding header) in dwords */ + u32 fw_size; + + /* Major Minor version */ + u32 fw_version; +} __packed; + +struct intel_dmc_header_v1 { + struct intel_dmc_header_base base; + + /* Number of valid MMIO cycles present. */ + u32 mmio_count; + + /* MMIO address */ + u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; + + /* MMIO data */ + u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; + + /* FW filename */ + char dfile[32]; + + u32 reserved1[2]; +} __packed; + +struct intel_dmc_header_v3 { + struct intel_dmc_header_base base; + + /* DMC RAM start MMIO address */ + u32 start_mmioaddr; + + u32 reserved[9]; + + /* FW filename */ + char dfile[32]; + + /* Number of valid MMIO cycles present. */ + u32 mmio_count; + + /* MMIO address */ + u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; + + /* MMIO data */ + u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; +} __packed; + +struct stepping_info { + char stepping; + char substepping; +}; + +static const struct stepping_info skl_stepping_info[] = { + {'A', '0'}, {'B', '0'}, {'C', '0'}, + {'D', '0'}, {'E', '0'}, {'F', '0'}, + {'G', '0'}, {'H', '0'}, {'I', '0'}, + {'J', '0'}, {'K', '0'} +}; + +static const struct stepping_info bxt_stepping_info[] = { + {'A', '0'}, {'A', '1'}, {'A', '2'}, + {'B', '0'}, {'B', '1'}, {'B', '2'} +}; + +static const struct stepping_info icl_stepping_info[] = { + {'A', '0'}, {'A', '1'}, {'A', '2'}, + {'B', '0'}, {'B', '2'}, + {'C', '0'} +}; + +static const struct stepping_info no_stepping_info = { '*', '*' }; + +static const struct stepping_info * +intel_get_stepping_info(struct drm_i915_private *dev_priv) +{ + const struct stepping_info *si; + unsigned int size; + + if (IS_ICELAKE(dev_priv)) { + size = ARRAY_SIZE(icl_stepping_info); + si = icl_stepping_info; + } else if (IS_SKYLAKE(dev_priv)) { + size = ARRAY_SIZE(skl_stepping_info); + si = skl_stepping_info; + } else if (IS_BROXTON(dev_priv)) { + size = ARRAY_SIZE(bxt_stepping_info); + si = bxt_stepping_info; + } else { + size = 0; + si = NULL; + } + + if (INTEL_REVID(dev_priv) < size) + return si + INTEL_REVID(dev_priv); + + return &no_stepping_info; +} + +static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) +{ + u32 val, mask; + + mask = DC_STATE_DEBUG_MASK_MEMORY_UP; + + if (IS_GEN9_LP(dev_priv)) + mask |= DC_STATE_DEBUG_MASK_CORES; + + /* The below bit doesn't need to be cleared ever afterwards */ + val = intel_de_read(dev_priv, DC_STATE_DEBUG); + if ((val & mask) != mask) { + val |= mask; + intel_de_write(dev_priv, DC_STATE_DEBUG, val); + intel_de_posting_read(dev_priv, DC_STATE_DEBUG); + } +} + +/** + * intel_csr_load_program() - write the firmware from memory to register. + * @dev_priv: i915 drm device. + * + * CSR firmware is read from a .bin file and kept in internal memory one time. + * Everytime display comes back from low power state this function is called to + * copy the firmware from internal memory to registers. + */ +void intel_csr_load_program(struct drm_i915_private *dev_priv) +{ + u32 *payload = dev_priv->csr.dmc_payload; + u32 i, fw_size; + + if (!HAS_CSR(dev_priv)) { + drm_err(&dev_priv->drm, + "No CSR support available for this platform\n"); + return; + } + + if (!dev_priv->csr.dmc_payload) { + drm_err(&dev_priv->drm, + "Tried to program CSR with empty payload\n"); + return; + } + + fw_size = dev_priv->csr.dmc_fw_size; + assert_rpm_wakelock_held(&dev_priv->runtime_pm); + + preempt_disable(); + + for (i = 0; i < fw_size; i++) + intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i), + payload[i]); + + preempt_enable(); + + for (i = 0; i < dev_priv->csr.mmio_count; i++) { + intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i], + dev_priv->csr.mmiodata[i]); + } + + dev_priv->csr.dc_state = 0; + + gen9_set_dc_state_debugmask(dev_priv); +} + +/* + * Search fw_info table for dmc_offset to find firmware binary: num_entries is + * already sanitized. + */ +static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info, + unsigned int num_entries, + const struct stepping_info *si, + u8 package_ver) +{ + u32 dmc_offset = CSR_DEFAULT_FW_OFFSET; + unsigned int i; + + for (i = 0; i < num_entries; i++) { + if (package_ver > 1 && fw_info[i].dmc_id != 0) + continue; + + if (fw_info[i].substepping == '*' && + si->stepping == fw_info[i].stepping) { + dmc_offset = fw_info[i].offset; + break; + } + + if (si->stepping == fw_info[i].stepping && + si->substepping == fw_info[i].substepping) { + dmc_offset = fw_info[i].offset; + break; + } + + if (fw_info[i].stepping == '*' && + fw_info[i].substepping == '*') { + /* + * In theory we should stop the search as generic + * entries should always come after the more specific + * ones, but let's continue to make sure to work even + * with "broken" firmwares. If we don't find a more + * specific one, then we use this entry + */ + dmc_offset = fw_info[i].offset; + } + } + + return dmc_offset; +} + +static u32 parse_csr_fw_dmc(struct intel_csr *csr, + const struct intel_dmc_header_base *dmc_header, + size_t rem_size) +{ + unsigned int header_len_bytes, dmc_header_size, payload_size, i; + const u32 *mmioaddr, *mmiodata; + u32 mmio_count, mmio_count_max; + u8 *payload; + + BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || + ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); + + /* + * Check if we can access common fields, we will checkc again below + * after we have read the version + */ + if (rem_size < sizeof(struct intel_dmc_header_base)) + goto error_truncated; + + /* Cope with small differences between v1 and v3 */ + if (dmc_header->header_ver == 3) { + const struct intel_dmc_header_v3 *v3 = + (const struct intel_dmc_header_v3 *)dmc_header; + + if (rem_size < sizeof(struct intel_dmc_header_v3)) + goto error_truncated; + + mmioaddr = v3->mmioaddr; + mmiodata = v3->mmiodata; + mmio_count = v3->mmio_count; + mmio_count_max = DMC_V3_MAX_MMIO_COUNT; + /* header_len is in dwords */ + header_len_bytes = dmc_header->header_len * 4; + dmc_header_size = sizeof(*v3); + } else if (dmc_header->header_ver == 1) { + const struct intel_dmc_header_v1 *v1 = + (const struct intel_dmc_header_v1 *)dmc_header; + + if (rem_size < sizeof(struct intel_dmc_header_v1)) + goto error_truncated; + + mmioaddr = v1->mmioaddr; + mmiodata = v1->mmiodata; + mmio_count = v1->mmio_count; + mmio_count_max = DMC_V1_MAX_MMIO_COUNT; + header_len_bytes = dmc_header->header_len; + dmc_header_size = sizeof(*v1); + } else { + DRM_ERROR("Unknown DMC fw header version: %u\n", + dmc_header->header_ver); + return 0; + } + + if (header_len_bytes != dmc_header_size) { + DRM_ERROR("DMC firmware has wrong dmc header length " + "(%u bytes)\n", header_len_bytes); + return 0; + } + + /* Cache the dmc header info. */ + if (mmio_count > mmio_count_max) { + DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count); + return 0; + } + + for (i = 0; i < mmio_count; i++) { + if (mmioaddr[i] < CSR_MMIO_START_RANGE || + mmioaddr[i] > CSR_MMIO_END_RANGE) { + DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n", + mmioaddr[i]); + return 0; + } + csr->mmioaddr[i] = _MMIO(mmioaddr[i]); + csr->mmiodata[i] = mmiodata[i]; + } + csr->mmio_count = mmio_count; + + rem_size -= header_len_bytes; + + /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ + payload_size = dmc_header->fw_size * 4; + if (rem_size < payload_size) + goto error_truncated; + + if (payload_size > csr->max_fw_size) { + DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size); + return 0; + } + csr->dmc_fw_size = dmc_header->fw_size; + + csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL); + if (!csr->dmc_payload) { + DRM_ERROR("Memory allocation failed for dmc payload\n"); + return 0; + } + + payload = (u8 *)(dmc_header) + header_len_bytes; + memcpy(csr->dmc_payload, payload, payload_size); + + return header_len_bytes + payload_size; + +error_truncated: + DRM_ERROR("Truncated DMC firmware, refusing.\n"); + return 0; +} + +static u32 +parse_csr_fw_package(struct intel_csr *csr, + const struct intel_package_header *package_header, + const struct stepping_info *si, + size_t rem_size) +{ + u32 package_size = sizeof(struct intel_package_header); + u32 num_entries, max_entries, dmc_offset; + const struct intel_fw_info *fw_info; + + if (rem_size < package_size) + goto error_truncated; + + if (package_header->header_ver == 1) { + max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; + } else if (package_header->header_ver == 2) { + max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; + } else { + DRM_ERROR("DMC firmware has unknown header version %u\n", + package_header->header_ver); + return 0; + } + + /* + * We should always have space for max_entries, + * even if not all are used + */ + package_size += max_entries * sizeof(struct intel_fw_info); + if (rem_size < package_size) + goto error_truncated; + + if (package_header->header_len * 4 != package_size) { + DRM_ERROR("DMC firmware has wrong package header length " + "(%u bytes)\n", package_size); + return 0; + } + + num_entries = package_header->num_entries; + if (WARN_ON(package_header->num_entries > max_entries)) + num_entries = max_entries; + + fw_info = (const struct intel_fw_info *) + ((u8 *)package_header + sizeof(*package_header)); + dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si, + package_header->header_ver); + if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { + DRM_ERROR("DMC firmware not supported for %c stepping\n", + si->stepping); + return 0; + } + + /* dmc_offset is in dwords */ + return package_size + dmc_offset * 4; + +error_truncated: + DRM_ERROR("Truncated DMC firmware, refusing.\n"); + return 0; +} + +/* Return number of bytes parsed or 0 on error */ +static u32 parse_csr_fw_css(struct intel_csr *csr, + struct intel_css_header *css_header, + size_t rem_size) +{ + if (rem_size < sizeof(struct intel_css_header)) { + DRM_ERROR("Truncated DMC firmware, refusing.\n"); + return 0; + } + + if (sizeof(struct intel_css_header) != + (css_header->header_len * 4)) { + DRM_ERROR("DMC firmware has wrong CSS header length " + "(%u bytes)\n", + (css_header->header_len * 4)); + return 0; + } + + if (csr->required_version && + css_header->version != csr->required_version) { + DRM_INFO("Refusing to load DMC firmware v%u.%u," + " please use v%u.%u\n", + CSR_VERSION_MAJOR(css_header->version), + CSR_VERSION_MINOR(css_header->version), + CSR_VERSION_MAJOR(csr->required_version), + CSR_VERSION_MINOR(csr->required_version)); + return 0; + } + + csr->version = css_header->version; + + return sizeof(struct intel_css_header); +} + +static void parse_csr_fw(struct drm_i915_private *dev_priv, + const struct firmware *fw) +{ + struct intel_css_header *css_header; + struct intel_package_header *package_header; + struct intel_dmc_header_base *dmc_header; + struct intel_csr *csr = &dev_priv->csr; + const struct stepping_info *si = intel_get_stepping_info(dev_priv); + u32 readcount = 0; + u32 r; + + if (!fw) + return; + + /* Extract CSS Header information */ + css_header = (struct intel_css_header *)fw->data; + r = parse_csr_fw_css(csr, css_header, fw->size); + if (!r) + return; + + readcount += r; + + /* Extract Package Header information */ + package_header = (struct intel_package_header *)&fw->data[readcount]; + r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount); + if (!r) + return; + + readcount += r; + + /* Extract dmc_header information */ + dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount]; + parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount); +} + +static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv) +{ + drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref); + dev_priv->csr.wakeref = + intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); +} + +static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv) +{ + intel_wakeref_t wakeref __maybe_unused = + fetch_and_zero(&dev_priv->csr.wakeref); + + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); +} + +static void csr_load_work_fn(struct work_struct *work) +{ + struct drm_i915_private *dev_priv; + struct intel_csr *csr; + const struct firmware *fw = NULL; + + dev_priv = container_of(work, typeof(*dev_priv), csr.work); + csr = &dev_priv->csr; + + request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev); + parse_csr_fw(dev_priv, fw); + + if (dev_priv->csr.dmc_payload) { + intel_csr_load_program(dev_priv); + intel_csr_runtime_pm_put(dev_priv); + + drm_info(&dev_priv->drm, + "Finished loading DMC firmware %s (v%u.%u)\n", + dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version), + CSR_VERSION_MINOR(csr->version)); + } else { + drm_notice(&dev_priv->drm, + "Failed to load DMC firmware %s." + " Disabling runtime power management.\n", + csr->fw_path); + drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", + INTEL_UC_FIRMWARE_URL); + } + + release_firmware(fw); +} + +/** + * intel_csr_ucode_init() - initialize the firmware loading. + * @dev_priv: i915 drm device. + * + * This function is called at the time of loading the display driver to read + * firmware from a .bin file and copied into a internal memory. + */ +void intel_csr_ucode_init(struct drm_i915_private *dev_priv) +{ + struct intel_csr *csr = &dev_priv->csr; + + INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); + + if (!HAS_CSR(dev_priv)) + return; + + /* + * Obtain a runtime pm reference, until CSR is loaded, to avoid entering + * runtime-suspend. + * + * On error, we return with the rpm wakeref held to prevent runtime + * suspend as runtime suspend *requires* a working CSR for whatever + * reason. + */ + intel_csr_runtime_pm_get(dev_priv); + + if (INTEL_GEN(dev_priv) >= 12) { + csr->fw_path = TGL_CSR_PATH; + csr->required_version = TGL_CSR_VERSION_REQUIRED; + /* Allow to load fw via parameter using the last known size */ + csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE; + } else if (IS_GEN(dev_priv, 11)) { + csr->fw_path = ICL_CSR_PATH; + csr->required_version = ICL_CSR_VERSION_REQUIRED; + csr->max_fw_size = ICL_CSR_MAX_FW_SIZE; + } else if (IS_CANNONLAKE(dev_priv)) { + csr->fw_path = CNL_CSR_PATH; + csr->required_version = CNL_CSR_VERSION_REQUIRED; + csr->max_fw_size = CNL_CSR_MAX_FW_SIZE; + } else if (IS_GEMINILAKE(dev_priv)) { + csr->fw_path = GLK_CSR_PATH; + csr->required_version = GLK_CSR_VERSION_REQUIRED; + csr->max_fw_size = GLK_CSR_MAX_FW_SIZE; + } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) { + csr->fw_path = KBL_CSR_PATH; + csr->required_version = KBL_CSR_VERSION_REQUIRED; + csr->max_fw_size = KBL_CSR_MAX_FW_SIZE; + } else if (IS_SKYLAKE(dev_priv)) { + csr->fw_path = SKL_CSR_PATH; + csr->required_version = SKL_CSR_VERSION_REQUIRED; + csr->max_fw_size = SKL_CSR_MAX_FW_SIZE; + } else if (IS_BROXTON(dev_priv)) { + csr->fw_path = BXT_CSR_PATH; + csr->required_version = BXT_CSR_VERSION_REQUIRED; + csr->max_fw_size = BXT_CSR_MAX_FW_SIZE; + } + + if (i915_modparams.dmc_firmware_path) { + if (strlen(i915_modparams.dmc_firmware_path) == 0) { + csr->fw_path = NULL; + drm_info(&dev_priv->drm, + "Disabling CSR firmware and runtime PM\n"); + return; + } + + csr->fw_path = i915_modparams.dmc_firmware_path; + /* Bypass version check for firmware override. */ + csr->required_version = 0; + } + + if (csr->fw_path == NULL) { + drm_dbg_kms(&dev_priv->drm, + "No known CSR firmware for platform, disabling runtime PM\n"); + return; + } + + drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path); + schedule_work(&dev_priv->csr.work); +} + +/** + * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend + * @dev_priv: i915 drm device + * + * Prepare the DMC firmware before entering system suspend. This includes + * flushing pending work items and releasing any resources acquired during + * init. + */ +void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) +{ + if (!HAS_CSR(dev_priv)) + return; + + flush_work(&dev_priv->csr.work); + + /* Drop the reference held in case DMC isn't loaded. */ + if (!dev_priv->csr.dmc_payload) + intel_csr_runtime_pm_put(dev_priv); +} + +/** + * intel_csr_ucode_resume() - init CSR firmware during system resume + * @dev_priv: i915 drm device + * + * Reinitialize the DMC firmware during system resume, reacquiring any + * resources released in intel_csr_ucode_suspend(). + */ +void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) +{ + if (!HAS_CSR(dev_priv)) + return; + + /* + * Reacquire the reference to keep RPM disabled in case DMC isn't + * loaded. + */ + if (!dev_priv->csr.dmc_payload) + intel_csr_runtime_pm_get(dev_priv); +} + +/** + * intel_csr_ucode_fini() - unload the CSR firmware. + * @dev_priv: i915 drm device. + * + * Firmmware unloading includes freeing the internal memory and reset the + * firmware loading status. + */ +void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) +{ + if (!HAS_CSR(dev_priv)) + return; + + intel_csr_ucode_suspend(dev_priv); + drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref); + + kfree(dev_priv->csr.dmc_payload); +} diff --git a/drivers/gpu/drm/i915/display/intel_csr.h b/drivers/gpu/drm/i915/display/intel_csr.h new file mode 100644 index 000000000000..03c64f8af7ab --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_csr.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation + */ + +#ifndef __INTEL_CSR_H__ +#define __INTEL_CSR_H__ + +struct drm_i915_private; + +#define CSR_VERSION(major, minor) ((major) << 16 | (minor)) +#define CSR_VERSION_MAJOR(version) ((version) >> 16) +#define CSR_VERSION_MINOR(version) ((version) & 0xffff) + +void intel_csr_ucode_init(struct drm_i915_private *i915); +void intel_csr_load_program(struct drm_i915_private *i915); +void intel_csr_ucode_fini(struct drm_i915_private *i915); +void intel_csr_ucode_suspend(struct drm_i915_private *i915); +void intel_csr_ucode_resume(struct drm_i915_private *i915); + +#endif /* __INTEL_CSR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index d9a61f341070..2c617c98db3a 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -568,6 +568,20 @@ static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = { { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 850 3.0 */ }; +static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_hbr2_hbr3[] = { + /* NT mV Trans mV db */ + { 0xA, 0x33, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ + { 0xA, 0x47, 0x36, 0x00, 0x09 }, /* 350 500 3.1 */ + { 0xC, 0x64, 0x30, 0x00, 0x0F }, /* 350 700 6.0 */ + { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */ + { 0xA, 0x46, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ + { 0xC, 0x64, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */ + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */ + { 0xC, 0x61, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */ + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +}; + struct icl_mg_phy_ddi_buf_trans { u32 cri_txdeemph_override_5_0; u32 cri_txdeemph_override_11_6; @@ -622,6 +636,34 @@ static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = { { 0x0, 0x0, 0xA }, /* 10 Full -3 dB */ }; +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = { + /* NT mV Trans mV db */ + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ + { 0xC, 0x71, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ + { 0x6, 0x7D, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ + { 0xA, 0x4C, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ + { 0xC, 0x73, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ + { 0xC, 0x6C, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +}; + +static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = { + /* NT mV Trans mV db */ + { 0xA, 0x35, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */ + { 0xA, 0x4F, 0x37, 0x00, 0x08 }, /* 350 500 3.1 */ + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */ + { 0x6, 0x7F, 0x2B, 0x00, 0x14 }, /* 350 900 8.2 */ + { 0xA, 0x47, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */ + { 0xC, 0x63, 0x34, 0x00, 0x0B }, /* 500 700 2.9 */ + { 0x6, 0x7F, 0x2F, 0x00, 0x10 }, /* 500 900 5.1 */ + { 0xC, 0x61, 0x3C, 0x00, 0x03 }, /* 650 700 0.6 */ + { 0x6, 0x7B, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */ + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */ +}; + static const struct ddi_buf_trans * bdw_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) { @@ -818,7 +860,7 @@ bxt_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) static const struct cnl_ddi_buf_trans * cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V); @@ -839,7 +881,7 @@ cnl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) static const struct cnl_ddi_buf_trans * cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) { - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (voltage == VOLTAGE_INFO_0_85V) { *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V); @@ -860,7 +902,7 @@ cnl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries) static const struct cnl_ddi_buf_trans * cnl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries) { - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; if (dev_priv->vbt.edp.low_vswing) { if (voltage == VOLTAGE_INFO_0_85V) { @@ -901,15 +943,43 @@ icl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, return icl_combo_phy_ddi_translations_dp_hbr2; } -static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port port) +static const struct cnl_ddi_buf_trans * +ehl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, + int *n_entries) { - struct ddi_vbt_port_info *port_info = &dev_priv->vbt.ddi_port_info[port]; + if (type != INTEL_OUTPUT_HDMI && type != INTEL_OUTPUT_EDP && + rate > 270000) { + *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_hbr2_hbr3); + return ehl_combo_phy_ddi_translations_hbr2_hbr3; + } + + return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); +} + +static const struct cnl_ddi_buf_trans * +tgl_get_combo_buf_trans(struct drm_i915_private *dev_priv, int type, int rate, + int *n_entries) +{ + if (type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_EDP) { + return icl_get_combo_buf_trans(dev_priv, type, rate, n_entries); + } else if (rate > 270000) { + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2); + return tgl_combo_phy_ddi_translations_dp_hbr2; + } + + *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr); + return tgl_combo_phy_ddi_translations_dp_hbr; +} + +static int intel_ddi_hdmi_level(struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int n_entries, level, default_entry; - enum phy phy = intel_port_to_phy(dev_priv, port); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); if (INTEL_GEN(dev_priv) >= 12) { if (intel_phy_is_combo(dev_priv, phy)) - icl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, + tgl_get_combo_buf_trans(dev_priv, INTEL_OUTPUT_HDMI, 0, &n_entries); else n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans); @@ -937,19 +1007,18 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); default_entry = 6; } else { - WARN(1, "ddi translation table missing\n"); + drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n"); return 0; } - if (WARN_ON_ONCE(n_entries == 0)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0)) return 0; - if (port_info->hdmi_level_shift_set) - level = port_info->hdmi_level_shift; - else + level = intel_bios_hdmi_level_shift(encoder); + if (level < 0) level = default_entry; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; return level; @@ -980,15 +1049,14 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, &n_entries); /* If we're boosting the current, set bit 31 of trans1 */ - if (IS_GEN9_BC(dev_priv) && - dev_priv->vbt.ddi_port_info[port].dp_boost_level) + if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; for (i = 0; i < n_entries; i++) { - I915_WRITE(DDI_BUF_TRANS_LO(port, i), - ddi_translations[i].trans1 | iboost_bit); - I915_WRITE(DDI_BUF_TRANS_HI(port, i), - ddi_translations[i].trans2); + intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), + ddi_translations[i].trans1 | iboost_bit); + intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i), + ddi_translations[i].trans2); } } @@ -1008,21 +1076,20 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, ddi_translations = intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; /* If we're boosting the current, set bit 31 of trans1 */ - if (IS_GEN9_BC(dev_priv) && - dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) + if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder)) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; /* Entry 9 is for HDMI: */ - I915_WRITE(DDI_BUF_TRANS_LO(port, 9), - ddi_translations[level].trans1 | iboost_bit); - I915_WRITE(DDI_BUF_TRANS_HI(port, 9), - ddi_translations[level].trans2); + intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9), + ddi_translations[level].trans1 | iboost_bit); + intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9), + ddi_translations[level].trans2); } static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, @@ -1033,7 +1100,7 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, for (i = 0; i < 16; i++) { udelay(1); - if (I915_READ(reg) & DDI_BUF_IS_IDLE) + if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE) return; } DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); @@ -1124,70 +1191,64 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, * * WaFDIAutoLinkSetTimingOverrride:hsw */ - I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | - FDI_RX_PWRDN_LANE0_VAL(2) | - FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); + intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), + FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); /* Enable the PCH Receiver FDI PLL */ rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | FDI_RX_PLL_ENABLE | FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); - I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); - POSTING_READ(FDI_RX_CTL(PIPE_A)); + intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); udelay(220); /* Switch from Rawclk to PCDclk */ rx_ctl_val |= FDI_PCDCLK; - I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); /* Configure Port Clock Select */ ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); - I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel); - WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL); + intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); + drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { /* Configure DP_TP_CTL with auto-training */ - I915_WRITE(DP_TP_CTL(PORT_E), - DP_TP_CTL_FDI_AUTOTRAIN | - DP_TP_CTL_ENHANCED_FRAME_ENABLE | - DP_TP_CTL_LINK_TRAIN_PAT1 | - DP_TP_CTL_ENABLE); + intel_de_write(dev_priv, DP_TP_CTL(PORT_E), + DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_ENABLE); /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. * DDI E does not support port reversal, the functionality is * achieved on the PCH side in FDI_RX_CTL, so no need to set the * port reversal bit */ - I915_WRITE(DDI_BUF_CTL(PORT_E), - DDI_BUF_CTL_ENABLE | - ((crtc_state->fdi_lanes - 1) << 1) | - DDI_BUF_TRANS_SELECT(i / 2)); - POSTING_READ(DDI_BUF_CTL(PORT_E)); + intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), + DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2)); + intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); udelay(600); /* Program PCH FDI Receiver TU */ - I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); + intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); /* Enable PCH FDI Receiver with auto-training */ rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; - I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); - POSTING_READ(FDI_RX_CTL(PIPE_A)); + intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); /* Wait for FDI receiver lane calibration */ udelay(30); /* Unset FDI_RX_MISC pwrdn lanes */ - temp = I915_READ(FDI_RX_MISC(PIPE_A)); + temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); - I915_WRITE(FDI_RX_MISC(PIPE_A), temp); - POSTING_READ(FDI_RX_MISC(PIPE_A)); + intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); + intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); /* Wait for FDI auto training time */ udelay(5); - temp = I915_READ(DP_TP_STATUS(PORT_E)); + temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { DRM_DEBUG_KMS("FDI link training done on step %d\n", i); break; @@ -1203,37 +1264,34 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, } rx_ctl_val &= ~FDI_RX_ENABLE; - I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); - POSTING_READ(FDI_RX_CTL(PIPE_A)); + intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); + intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); - temp = I915_READ(DDI_BUF_CTL(PORT_E)); + temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E)); temp &= ~DDI_BUF_CTL_ENABLE; - I915_WRITE(DDI_BUF_CTL(PORT_E), temp); - POSTING_READ(DDI_BUF_CTL(PORT_E)); + intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp); + intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ - temp = I915_READ(DP_TP_CTL(PORT_E)); + temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E)); temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); temp |= DP_TP_CTL_LINK_TRAIN_PAT1; - I915_WRITE(DP_TP_CTL(PORT_E), temp); - POSTING_READ(DP_TP_CTL(PORT_E)); + intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp); + intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); intel_wait_ddi_buf_idle(dev_priv, PORT_E); /* Reset FDI_RX_MISC pwrdn lanes */ - temp = I915_READ(FDI_RX_MISC(PIPE_A)); + temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); - I915_WRITE(FDI_RX_MISC(PIPE_A), temp); - POSTING_READ(FDI_RX_MISC(PIPE_A)); + intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp); + intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); } /* Enable normal pixel sending for FDI */ - I915_WRITE(DP_TP_CTL(PORT_E), - DP_TP_CTL_FDI_AUTOTRAIN | - DP_TP_CTL_LINK_TRAIN_NORMAL | - DP_TP_CTL_ENHANCED_FRAME_ENABLE | - DP_TP_CTL_ENABLE); + intel_de_write(dev_priv, DP_TP_CTL(PORT_E), + DP_TP_CTL_FDI_AUTOTRAIN | DP_TP_CTL_LINK_TRAIN_NORMAL | DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_ENABLE); } static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) @@ -1260,175 +1318,18 @@ intel_ddi_get_crtc_encoder(struct intel_crtc *crtc) } if (num_encoders != 1) - WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, - pipe_name(crtc->pipe)); + drm_WARN(dev, 1, "%d encoders on crtc for pipe %c\n", + num_encoders, + pipe_name(crtc->pipe)); BUG_ON(ret == NULL); return ret; } -static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, - i915_reg_t reg) -{ - int refclk; - int n, p, r; - u32 wrpll; - - wrpll = I915_READ(reg); - switch (wrpll & WRPLL_REF_MASK) { - case WRPLL_REF_SPECIAL_HSW: - /* - * muxed-SSC for BDW. - * non-SSC for non-ULT HSW. Check FUSE_STRAP3 - * for the non-SSC reference frequency. - */ - if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { - if (I915_READ(FUSE_STRAP3) & HSW_REF_CLK_SELECT) - refclk = 24; - else - refclk = 135; - break; - } - /* fall through */ - case WRPLL_REF_PCH_SSC: - /* - * We could calculate spread here, but our checking - * code only cares about 5% accuracy, and spread is a max of - * 0.5% downspread. - */ - refclk = 135; - break; - case WRPLL_REF_LCPLL: - refclk = 2700; - break; - default: - MISSING_CASE(wrpll); - return 0; - } - - r = wrpll & WRPLL_DIVIDER_REF_MASK; - p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; - n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; - - /* Convert to KHz, p & r have a fixed point portion */ - return (refclk * n * 100) / (p * r); -} - -static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state) -{ - u32 p0, p1, p2, dco_freq; - - p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; - p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; - - if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) - p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; - else - p1 = 1; - - - switch (p0) { - case DPLL_CFGCR2_PDIV_1: - p0 = 1; - break; - case DPLL_CFGCR2_PDIV_2: - p0 = 2; - break; - case DPLL_CFGCR2_PDIV_3: - p0 = 3; - break; - case DPLL_CFGCR2_PDIV_7: - p0 = 7; - break; - } - - switch (p2) { - case DPLL_CFGCR2_KDIV_5: - p2 = 5; - break; - case DPLL_CFGCR2_KDIV_2: - p2 = 2; - break; - case DPLL_CFGCR2_KDIV_3: - p2 = 3; - break; - case DPLL_CFGCR2_KDIV_1: - p2 = 1; - break; - } - - dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) - * 24 * 1000; - - dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) - * 24 * 1000) / 0x8000; - - if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) - return 0; - - return dco_freq / (p0 * p1 * p2 * 5); -} - -int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, - struct intel_dpll_hw_state *pll_state) -{ - u32 p0, p1, p2, dco_freq, ref_clock; - - p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; - p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; - - if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) - p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> - DPLL_CFGCR1_QDIV_RATIO_SHIFT; - else - p1 = 1; - - - switch (p0) { - case DPLL_CFGCR1_PDIV_2: - p0 = 2; - break; - case DPLL_CFGCR1_PDIV_3: - p0 = 3; - break; - case DPLL_CFGCR1_PDIV_5: - p0 = 5; - break; - case DPLL_CFGCR1_PDIV_7: - p0 = 7; - break; - } - - switch (p2) { - case DPLL_CFGCR1_KDIV_1: - p2 = 1; - break; - case DPLL_CFGCR1_KDIV_2: - p2 = 2; - break; - case DPLL_CFGCR1_KDIV_3: - p2 = 3; - break; - } - - ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); - - dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) - * ref_clock; - - dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> - DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; - - if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) - return 0; - - return dco_freq / (p0 * p1 * p2 * 5); -} - static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, enum port port) { - u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; + u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; switch (val) { case DDI_CLK_SEL_NONE: @@ -1447,77 +1348,6 @@ static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, } } -static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, - const struct intel_dpll_hw_state *pll_state) -{ - u32 m1, m2_int, m2_frac, div1, div2, ref_clock; - u64 tmp; - - ref_clock = dev_priv->cdclk.hw.ref; - - if (INTEL_GEN(dev_priv) >= 12) { - m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; - m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; - m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; - - if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { - m2_frac = pll_state->mg_pll_bias & - DKL_PLL_BIAS_FBDIV_FRAC_MASK; - m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; - } else { - m2_frac = 0; - } - } else { - m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; - m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; - - if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { - m2_frac = pll_state->mg_pll_div0 & - MG_PLL_DIV0_FBDIV_FRAC_MASK; - m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; - } else { - m2_frac = 0; - } - } - - switch (pll_state->mg_clktop2_hsclkctl & - MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { - case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: - div1 = 2; - break; - case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: - div1 = 3; - break; - case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: - div1 = 5; - break; - case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: - div1 = 7; - break; - default: - MISSING_CASE(pll_state->mg_clktop2_hsclkctl); - return 0; - } - - div2 = (pll_state->mg_clktop2_hsclkctl & - MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> - MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; - - /* div2 value of 0 is same as 1 means no div */ - if (div2 == 0) - div2 = 1; - - /* - * Adjust the original formula to delay the division by 2^22 in order to - * minimize possible rounding errors. - */ - tmp = (u64)m1 * m2_int * ref_clock + - (((u64)m1 * m2_frac * ref_clock) >> 22); - tmp = div_u64(tmp, 5 * div1 * div2); - - return tmp; -} - static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) { int dotclock; @@ -1543,214 +1373,22 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) pipe_config->hw.adjusted_mode.crtc_clock = dotclock; } -static void icl_ddi_clock_get(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; - enum port port = encoder->port; - enum phy phy = intel_port_to_phy(dev_priv, port); - int link_clock; - - if (intel_phy_is_combo(dev_priv, phy)) { - link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); - } else { - enum intel_dpll_id pll_id = intel_get_shared_dpll_id(dev_priv, - pipe_config->shared_dpll); - - if (pll_id == DPLL_ID_ICL_TBTPLL) - link_clock = icl_calc_tbt_pll_link(dev_priv, port); - else - link_clock = icl_calc_mg_pll_link(dev_priv, pll_state); - } - - pipe_config->port_clock = link_clock; - - ddi_dotclock_get(pipe_config); -} - -static void cnl_ddi_clock_get(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; - int link_clock; - - if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { - link_clock = cnl_calc_wrpll_link(dev_priv, pll_state); - } else { - link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; - - switch (link_clock) { - case DPLL_CFGCR0_LINK_RATE_810: - link_clock = 81000; - break; - case DPLL_CFGCR0_LINK_RATE_1080: - link_clock = 108000; - break; - case DPLL_CFGCR0_LINK_RATE_1350: - link_clock = 135000; - break; - case DPLL_CFGCR0_LINK_RATE_1620: - link_clock = 162000; - break; - case DPLL_CFGCR0_LINK_RATE_2160: - link_clock = 216000; - break; - case DPLL_CFGCR0_LINK_RATE_2700: - link_clock = 270000; - break; - case DPLL_CFGCR0_LINK_RATE_3240: - link_clock = 324000; - break; - case DPLL_CFGCR0_LINK_RATE_4050: - link_clock = 405000; - break; - default: - WARN(1, "Unsupported link rate\n"); - break; - } - link_clock *= 2; - } - - pipe_config->port_clock = link_clock; - - ddi_dotclock_get(pipe_config); -} - -static void skl_ddi_clock_get(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state; - int link_clock; - - /* - * ctrl1 register is already shifted for each pll, just use 0 to get - * the internal shift for each field - */ - if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) { - link_clock = skl_calc_wrpll_link(pll_state); - } else { - link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0); - link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(0); - - switch (link_clock) { - case DPLL_CTRL1_LINK_RATE_810: - link_clock = 81000; - break; - case DPLL_CTRL1_LINK_RATE_1080: - link_clock = 108000; - break; - case DPLL_CTRL1_LINK_RATE_1350: - link_clock = 135000; - break; - case DPLL_CTRL1_LINK_RATE_1620: - link_clock = 162000; - break; - case DPLL_CTRL1_LINK_RATE_2160: - link_clock = 216000; - break; - case DPLL_CTRL1_LINK_RATE_2700: - link_clock = 270000; - break; - default: - WARN(1, "Unsupported link rate\n"); - break; - } - link_clock *= 2; - } - - pipe_config->port_clock = link_clock; - - ddi_dotclock_get(pipe_config); -} - -static void hsw_ddi_clock_get(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - int link_clock = 0; - u32 val, pll; - - val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll); - switch (val & PORT_CLK_SEL_MASK) { - case PORT_CLK_SEL_LCPLL_810: - link_clock = 81000; - break; - case PORT_CLK_SEL_LCPLL_1350: - link_clock = 135000; - break; - case PORT_CLK_SEL_LCPLL_2700: - link_clock = 270000; - break; - case PORT_CLK_SEL_WRPLL1: - link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0)); - break; - case PORT_CLK_SEL_WRPLL2: - link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1)); - break; - case PORT_CLK_SEL_SPLL: - pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK; - if (pll == SPLL_FREQ_810MHz) - link_clock = 81000; - else if (pll == SPLL_FREQ_1350MHz) - link_clock = 135000; - else if (pll == SPLL_FREQ_2700MHz) - link_clock = 270000; - else { - WARN(1, "bad spll freq\n"); - return; - } - break; - default: - WARN(1, "bad port clock sel\n"); - return; - } - - pipe_config->port_clock = link_clock * 2; - - ddi_dotclock_get(pipe_config); -} - -static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state) -{ - struct dpll clock; - - clock.m1 = 2; - clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; - if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) - clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; - clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; - clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; - clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; - - return chv_calc_dpll_params(100000, &clock); -} - -static void bxt_ddi_clock_get(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - pipe_config->port_clock = - bxt_calc_pll_link(&pipe_config->dpll_hw_state); - - ddi_dotclock_get(pipe_config); -} - static void intel_ddi_clock_get(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum phy phy = intel_port_to_phy(dev_priv, encoder->port); - if (INTEL_GEN(dev_priv) >= 11) - icl_ddi_clock_get(encoder, pipe_config); - else if (IS_CANNONLAKE(dev_priv)) - cnl_ddi_clock_get(encoder, pipe_config); - else if (IS_GEN9_LP(dev_priv)) - bxt_ddi_clock_get(encoder, pipe_config); - else if (IS_GEN9_BC(dev_priv)) - skl_ddi_clock_get(encoder, pipe_config); - else if (INTEL_GEN(dev_priv) <= 8) - hsw_ddi_clock_get(encoder, pipe_config); + if (intel_phy_is_tc(dev_priv, phy) && + intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) == + DPLL_ID_ICL_TBTPLL) + pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv, + encoder->port); + else + pipe_config->port_clock = + intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll); + + ddi_dotclock_get(pipe_config); } void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, @@ -1764,7 +1402,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, if (!intel_crtc_has_dp_encoder(crtc_state)) return; - WARN_ON(transcoder_is_dsi(cpu_transcoder)); + drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); temp = DP_MSA_MISC_SYNC_CLOCK; @@ -1787,8 +1425,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, } /* nonsense combination */ - WARN_ON(crtc_state->limited_color_range && - crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); + drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->limited_color_range) temp |= DP_MSA_MISC_COLOR_CEA_RGB; @@ -1810,7 +1448,7 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) temp |= DP_MSA_MISC_COLOR_VSC_SDP; - I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); + intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); } /* @@ -1904,7 +1542,8 @@ intel_ddi_transcoder_func_reg_val_get(const struct intel_crtc_state *crtc_state) enum transcoder master; master = crtc_state->mst_master_transcoder; - WARN_ON(master == INVALID_TRANSCODER); + drm_WARN_ON(&dev_priv->drm, + master == INVALID_TRANSCODER); temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master); } } else { @@ -1925,7 +1564,7 @@ void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state) temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); } /* @@ -1942,7 +1581,7 @@ intel_ddi_config_transcoder_func(const struct intel_crtc_state *crtc_state) temp = intel_ddi_transcoder_func_reg_val_get(crtc_state); temp &= ~TRANS_DDI_FUNC_ENABLE; - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); } void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) @@ -1952,16 +1591,18 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 val; - val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + val = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); val &= ~TRANS_DDI_FUNC_ENABLE; if (INTEL_GEN(dev_priv) >= 12) { - if (!intel_dp_mst_is_master_trans(crtc_state)) - val &= ~TGL_TRANS_DDI_PORT_MASK; + if (!intel_dp_mst_is_master_trans(crtc_state)) { + val &= ~(TGL_TRANS_DDI_PORT_MASK | + TRANS_DDI_MODE_SELECT_MASK); + } } else { - val &= ~TRANS_DDI_PORT_MASK; + val &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); } - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), val); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), val); if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { @@ -1983,20 +1624,21 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, wakeref = intel_display_power_get_if_enabled(dev_priv, intel_encoder->power_domain); - if (WARN_ON(!wakeref)) + if (drm_WARN_ON(dev, !wakeref)) return -ENXIO; - if (WARN_ON(!intel_encoder->get_hw_state(intel_encoder, &pipe))) { + if (drm_WARN_ON(dev, + !intel_encoder->get_hw_state(intel_encoder, &pipe))) { ret = -EIO; goto out; } - tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe)); + tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe)); if (enable) tmp |= TRANS_DDI_HDCP_SIGNALLING; else tmp &= ~TRANS_DDI_HDCP_SIGNALLING; - I915_WRITE(TRANS_DDI_FUNC_CTL(pipe), tmp); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp); out: intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); return ret; @@ -2006,7 +1648,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) { struct drm_device *dev = intel_connector->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_encoder *encoder = intel_connector->encoder; + struct intel_encoder *encoder = intel_attached_encoder(intel_connector); int type = intel_connector->base.connector_type; enum port port = encoder->port; enum transcoder cpu_transcoder; @@ -2030,7 +1672,7 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) else cpu_transcoder = (enum transcoder) pipe; - tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { case TRANS_DDI_MODE_SELECT_HDMI: @@ -2083,12 +1725,13 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if (!wakeref) return; - tmp = I915_READ(DDI_BUF_CTL(port)); + tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); if (!(tmp & DDI_BUF_CTL_ENABLE)) goto out; if (HAS_TRANSCODER_EDP(dev_priv) && port == PORT_A) { - tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: @@ -2128,7 +1771,8 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, ddi_select = TRANS_DDI_SELECT_PORT(port); } - tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(cpu_transcoder)); intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), trans_wakeref); @@ -2162,7 +1806,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, out: if (*pipe_mask && IS_GEN9_LP(dev_priv)) { - tmp = I915_READ(BXT_PHY_CTL(port)); + tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)); if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | BXT_PHY_LANE_POWERDOWN_ACK | BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED) @@ -2221,11 +1865,16 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder, * happen since fake-MST encoders don't set their get_power_domains() * hook. */ - if (WARN_ON(intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) + if (drm_WARN_ON(&dev_priv->drm, + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))) return; dig_port = enc_to_dig_port(encoder); - intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain); + + if (!intel_phy_is_tc(dev_priv, phy) || + dig_port->tc_mode != TC_PORT_TBT_ALT) + intel_display_power_get(dev_priv, + dig_port->ddi_io_power_domain); /* * AUX power is only needed for (e)DP mode, and for HDMI mode on TC @@ -2254,11 +1903,13 @@ void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state) if (cpu_transcoder != TRANSCODER_EDP) { if (INTEL_GEN(dev_priv) >= 12) - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), - TGL_TRANS_CLK_SEL_PORT(port)); + intel_de_write(dev_priv, + TRANS_CLK_SEL(cpu_transcoder), + TGL_TRANS_CLK_SEL_PORT(port)); else - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), - TRANS_CLK_SEL_PORT(port)); + intel_de_write(dev_priv, + TRANS_CLK_SEL(cpu_transcoder), + TRANS_CLK_SEL_PORT(port)); } } @@ -2269,11 +1920,13 @@ void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) if (cpu_transcoder != TRANSCODER_EDP) { if (INTEL_GEN(dev_priv) >= 12) - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), - TGL_TRANS_CLK_SEL_DISABLED); + intel_de_write(dev_priv, + TRANS_CLK_SEL(cpu_transcoder), + TGL_TRANS_CLK_SEL_DISABLED); else - I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), - TRANS_CLK_SEL_DISABLED); + intel_de_write(dev_priv, + TRANS_CLK_SEL(cpu_transcoder), + TRANS_CLK_SEL_DISABLED); } } @@ -2282,13 +1935,13 @@ static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv, { u32 tmp; - tmp = I915_READ(DISPIO_CR_TX_BMU_CR0); + tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0); tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port)); if (iboost) tmp |= iboost << BALANCE_LEG_SHIFT(port); else tmp |= BALANCE_LEG_DISABLE(port); - I915_WRITE(DISPIO_CR_TX_BMU_CR0, tmp); + intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp); } static void skl_ddi_set_iboost(struct intel_encoder *encoder, @@ -2300,9 +1953,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, u8 iboost; if (type == INTEL_OUTPUT_HDMI) - iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; + iboost = intel_bios_hdmi_boost_level(encoder); else - iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; + iboost = intel_bios_dp_boost_level(encoder); if (iboost == 0) { const struct ddi_buf_trans *ddi_translations; @@ -2315,9 +1968,9 @@ static void skl_ddi_set_iboost(struct intel_encoder *encoder, else ddi_translations = intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; iboost = ddi_translations[level].i_boost; @@ -2350,9 +2003,9 @@ static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder, else ddi_translations = bxt_get_buf_trans_dp(dev_priv, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; bxt_ddi_phy_set_signal_level(dev_priv, port, @@ -2372,12 +2025,15 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) if (INTEL_GEN(dev_priv) >= 12) { if (intel_phy_is_combo(dev_priv, phy)) - icl_get_combo_buf_trans(dev_priv, encoder->type, + tgl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); else n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans); } else if (INTEL_GEN(dev_priv) == 11) { - if (intel_phy_is_combo(dev_priv, phy)) + if (IS_ELKHARTLAKE(dev_priv)) + ehl_get_combo_buf_trans(dev_priv, encoder->type, + intel_dp->link_rate, &n_entries); + else if (intel_phy_is_combo(dev_priv, phy)) icl_get_combo_buf_trans(dev_priv, encoder->type, intel_dp->link_rate, &n_entries); else @@ -2399,9 +2055,10 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) intel_ddi_get_buf_trans_dp(dev_priv, port, &n_entries); } - if (WARN_ON(n_entries < 1)) + if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) n_entries = 1; - if (WARN_ON(n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) + if (drm_WARN_ON(&dev_priv->drm, + n_entries > ARRAY_SIZE(index_to_dp_signal_levels))) n_entries = ARRAY_SIZE(index_to_dp_signal_levels); return index_to_dp_signal_levels[n_entries - 1] & @@ -2444,52 +2101,52 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, else ddi_translations = cnl_get_buf_trans_dp(dev_priv, &n_entries); - if (WARN_ON_ONCE(!ddi_translations)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations)) return; - if (WARN_ON_ONCE(level >= n_entries)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries)) level = n_entries - 1; /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */ - val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); val &= ~SCALING_MODE_SEL_MASK; val |= SCALING_MODE_SEL(2); - I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); /* Program PORT_TX_DW2 */ - val = I915_READ(CNL_PORT_TX_DW2_LN0(port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); /* Rcomp scalar is fixed as 0x98 for every table entry */ val |= RCOMP_SCALAR(0x98); - I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val); /* Program PORT_TX_DW4 */ /* We cannot write to GRP. It would overrite individual loadgen */ for (ln = 0; ln < 4; ln++) { - val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); - I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); } /* Program PORT_TX_DW5 */ /* All DW5 values are fixed for every table entry */ - val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); val &= ~RTERM_SELECT_MASK; val |= RTERM_SELECT(6); val |= TAP3_DISABLE; - I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); /* Program PORT_TX_DW7 */ - val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port)); val &= ~N_SCALAR_MASK; val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); - I915_WRITE(CNL_PORT_TX_DW7_GRP(port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val); } static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, @@ -2515,12 +2172,12 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, * set PORT_PCS_DW1 cmnkeeper_enable to 1b, * else clear to 0b. */ - val = I915_READ(CNL_PORT_PCS_DW1_LN0(port)); + val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port)); if (type != INTEL_OUTPUT_HDMI) val |= COMMON_KEEPER_EN; else val &= ~COMMON_KEEPER_EN; - I915_WRITE(CNL_PORT_PCS_DW1_GRP(port), val); + intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val); /* 2. Program loadgen select */ /* @@ -2530,33 +2187,33 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port)); val &= ~LOADGEN_SELECT; if ((rate <= 600000 && width == 4 && ln >= 1) || (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { val |= LOADGEN_SELECT; } - I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val); } /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ - val = I915_READ(CNL_PORT_CL1CM_DW5); + val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5); val |= SUS_CLOCK_CONFIG; - I915_WRITE(CNL_PORT_CL1CM_DW5, val); + intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val); /* 4. Clear training enable to change swing values */ - val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); val &= ~TX_TRAINING_EN; - I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); /* 5. Program swing and de-emphasis */ cnl_ddi_vswing_program(encoder, level, type); /* 6. Set training enable to trigger update */ - val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); + val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port)); val |= TX_TRAINING_EN; - I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); + intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val); } static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, @@ -2567,8 +2224,15 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, u32 n_entries, val; int ln; - ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, - &n_entries); + if (INTEL_GEN(dev_priv) >= 12) + ddi_translations = tgl_get_combo_buf_trans(dev_priv, type, rate, + &n_entries); + else if (IS_ELKHARTLAKE(dev_priv)) + ddi_translations = ehl_get_combo_buf_trans(dev_priv, type, rate, + &n_entries); + else + ddi_translations = icl_get_combo_buf_trans(dev_priv, type, rate, + &n_entries); if (!ddi_translations) return; @@ -2578,41 +2242,41 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, } /* Set PORT_TX_DW5 */ - val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK | TAP2_DISABLE | TAP3_DISABLE); val |= SCALING_MODE_SEL(0x2); val |= RTERM_SELECT(0x6); val |= TAP3_DISABLE; - I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); /* Program PORT_TX_DW2 */ - val = I915_READ(ICL_PORT_TX_DW2_LN0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | RCOMP_SCALAR_MASK); val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel); val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel); /* Program Rcomp scalar for every table entry */ val |= RCOMP_SCALAR(0x98); - I915_WRITE(ICL_PORT_TX_DW2_GRP(phy), val); + intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val); /* Program PORT_TX_DW4 */ /* We cannot write to GRP. It would overwrite individual loadgen. */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); + val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); + intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); } /* Program PORT_TX_DW7 */ - val = I915_READ(ICL_PORT_TX_DW7_LN0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy)); val &= ~N_SCALAR_MASK; val |= N_SCALAR(ddi_translations[level].dw7_n_scalar); - I915_WRITE(ICL_PORT_TX_DW7_GRP(phy), val); + intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val); } static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, @@ -2641,12 +2305,12 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * set PORT_PCS_DW1 cmnkeeper_enable to 1b, * else clear to 0b. */ - val = I915_READ(ICL_PORT_PCS_DW1_LN0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); if (type == INTEL_OUTPUT_HDMI) val &= ~COMMON_KEEPER_EN; else val |= COMMON_KEEPER_EN; - I915_WRITE(ICL_PORT_PCS_DW1_GRP(phy), val); + intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); /* 2. Program loadgen select */ /* @@ -2656,33 +2320,33 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(ICL_PORT_TX_DW4_LN(ln, phy)); + val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)); val &= ~LOADGEN_SELECT; if ((rate <= 600000 && width == 4 && ln >= 1) || (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { val |= LOADGEN_SELECT; } - I915_WRITE(ICL_PORT_TX_DW4_LN(ln, phy), val); + intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val); } /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ - val = I915_READ(ICL_PORT_CL_DW5(phy)); + val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); val |= SUS_CLOCK_CONFIG; - I915_WRITE(ICL_PORT_CL_DW5(phy), val); + intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val); /* 4. Clear training enable to change swing values */ - val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); val &= ~TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); /* 5. Program swing and de-emphasis */ icl_ddi_combo_vswing_program(dev_priv, level, phy, type, rate); /* 6. Set training enable to trigger update */ - val = I915_READ(ICL_PORT_TX_DW5_LN0(phy)); + val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); val |= TX_TRAINING_EN; - I915_WRITE(ICL_PORT_TX_DW5_GRP(phy), val); + intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val); } static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, @@ -2706,33 +2370,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_LINK_PARAMS(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)); val &= ~CRI_USE_FS32; - I915_WRITE(MG_TX1_LINK_PARAMS(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val); - val = I915_READ(MG_TX2_LINK_PARAMS(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)); val &= ~CRI_USE_FS32; - I915_WRITE(MG_TX2_LINK_PARAMS(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val); } /* Program MG_TX_SWINGCTRL with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_SWINGCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( ddi_translations[level].cri_txdeemph_override_17_12); - I915_WRITE(MG_TX1_SWINGCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val); - val = I915_READ(MG_TX2_SWINGCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( ddi_translations[level].cri_txdeemph_override_17_12); - I915_WRITE(MG_TX2_SWINGCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val); } /* Program MG_TX_DRVCTRL with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_DRVCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)); val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( @@ -2740,9 +2404,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, CRI_TXDEEMPH_OVERRIDE_11_6( ddi_translations[level].cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; - I915_WRITE(MG_TX1_DRVCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val); - val = I915_READ(MG_TX2_DRVCTRL(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)); val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( @@ -2750,7 +2414,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, CRI_TXDEEMPH_OVERRIDE_11_6( ddi_translations[level].cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; - I915_WRITE(MG_TX2_DRVCTRL(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val); /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ } @@ -2761,17 +2425,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * values from table for which TX1 and TX2 enabled. */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_CLKHUB(ln, tc_port)); + val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port)); if (link_clock < 300000) val |= CFG_LOW_RATE_LKREN_EN; else val &= ~CFG_LOW_RATE_LKREN_EN; - I915_WRITE(MG_CLKHUB(ln, tc_port), val); + intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val); } /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_DCC(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port)); val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; if (link_clock <= 500000) { val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; @@ -2779,9 +2443,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val |= CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); } - I915_WRITE(MG_TX1_DCC(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val); - val = I915_READ(MG_TX2_DCC(ln, tc_port)); + val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port)); val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; if (link_clock <= 500000) { val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; @@ -2789,18 +2453,22 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val |= CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); } - I915_WRITE(MG_TX2_DCC(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val); } /* Program MG_TX_PISO_READLOAD with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_PISO_READLOAD(ln, tc_port)); + val = intel_de_read(dev_priv, + MG_TX1_PISO_READLOAD(ln, tc_port)); val |= CRI_CALCINIT; - I915_WRITE(MG_TX1_PISO_READLOAD(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port), + val); - val = I915_READ(MG_TX2_PISO_READLOAD(ln, tc_port)); + val = intel_de_read(dev_priv, + MG_TX2_PISO_READLOAD(ln, tc_port)); val |= CRI_CALCINIT; - I915_WRITE(MG_TX2_PISO_READLOAD(ln, tc_port), val); + intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port), + val); } } @@ -2846,24 +2514,25 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock, dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control); for (ln = 0; ln < 2; ln++) { - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, ln)); - I915_WRITE(DKL_TX_PMD_LANE_SUS(tc_port), 0); + intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0); /* All the registers are RMW */ - val = I915_READ(DKL_TX_DPCNTL0(tc_port)); + val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port)); val &= ~dpcnt_mask; val |= dpcnt_val; - I915_WRITE(DKL_TX_DPCNTL0(tc_port), val); + intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val); - val = I915_READ(DKL_TX_DPCNTL1(tc_port)); + val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port)); val &= ~dpcnt_mask; val |= dpcnt_val; - I915_WRITE(DKL_TX_DPCNTL1(tc_port), val); + intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val); - val = I915_READ(DKL_TX_DPCNTL2(tc_port)); + val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port)); val &= ~DKL_TX_DP20BITMODE; - I915_WRITE(DKL_TX_DPCNTL2(tc_port), val); + intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val); } } @@ -2963,10 +2632,11 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, enum phy phy = intel_port_to_phy(dev_priv, encoder->port); u32 val; - mutex_lock(&dev_priv->dpll_lock); + mutex_lock(&dev_priv->dpll.lock); - val = I915_READ(ICL_DPCLKA_CFGCR0); - WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); + val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); + drm_WARN_ON(&dev_priv->drm, + (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0); if (intel_phy_is_combo(dev_priv, phy)) { /* @@ -2981,14 +2651,14 @@ static void icl_map_plls_to_ports(struct intel_encoder *encoder, */ val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); - I915_WRITE(ICL_DPCLKA_CFGCR0, val); - POSTING_READ(ICL_DPCLKA_CFGCR0); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); + intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); } val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - I915_WRITE(ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); - mutex_unlock(&dev_priv->dpll_lock); + mutex_unlock(&dev_priv->dpll.lock); } static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) @@ -2997,13 +2667,13 @@ static void icl_unmap_plls_to_ports(struct intel_encoder *encoder) enum phy phy = intel_port_to_phy(dev_priv, encoder->port); u32 val; - mutex_lock(&dev_priv->dpll_lock); + mutex_lock(&dev_priv->dpll.lock); - val = I915_READ(ICL_DPCLKA_CFGCR0); + val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - I915_WRITE(ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); - mutex_unlock(&dev_priv->dpll_lock); + mutex_unlock(&dev_priv->dpll.lock); } static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, @@ -3012,7 +2682,7 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, enum port port; u32 val; - val = I915_READ(ICL_DPCLKA_CFGCR0); + val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); for_each_port_masked(port, port_mask) { enum phy phy = intel_port_to_phy(dev_priv, port); bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv, @@ -3025,13 +2695,13 @@ static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv, * Punt on the case now where clock is gated, but it would * be needed by the port. Something else is really broken then. */ - if (WARN_ON(ddi_clk_needed)) + if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed)) continue; DRM_NOTE("PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n", phy_name(phy)); val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy); - I915_WRITE(ICL_DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); } } @@ -3057,7 +2727,7 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) * In the unlikely case that BIOS enables DP in MST mode, just * warn since our MST HW readout is incomplete. */ - if (WARN_ON(is_mst)) + if (drm_WARN_ON(&dev_priv->drm, is_mst)) return; } @@ -3076,7 +2746,8 @@ void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) if (other_encoder == encoder) continue; - if (WARN_ON(port_mask & BIT(other_encoder->port))) + if (drm_WARN_ON(&dev_priv->drm, + port_mask & BIT(other_encoder->port))) return; } /* @@ -3098,52 +2769,54 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, u32 val; const struct intel_shared_dpll *pll = crtc_state->shared_dpll; - if (WARN_ON(!pll)) + if (drm_WARN_ON(&dev_priv->drm, !pll)) return; - mutex_lock(&dev_priv->dpll_lock); + mutex_lock(&dev_priv->dpll.lock); if (INTEL_GEN(dev_priv) >= 11) { if (!intel_phy_is_combo(dev_priv, phy)) - I915_WRITE(DDI_CLK_SEL(port), - icl_pll_to_ddi_clk_sel(encoder, crtc_state)); + intel_de_write(dev_priv, DDI_CLK_SEL(port), + icl_pll_to_ddi_clk_sel(encoder, crtc_state)); else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C) /* * MG does not exist but the programming is required * to ungate DDIC and DDID */ - I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_MG); + intel_de_write(dev_priv, DDI_CLK_SEL(port), + DDI_CLK_SEL_MG); } else if (IS_CANNONLAKE(dev_priv)) { /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */ - val = I915_READ(DPCLKA_CFGCR0); + val = intel_de_read(dev_priv, DPCLKA_CFGCR0); val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port); - I915_WRITE(DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, DPCLKA_CFGCR0, val); /* * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI. * This step and the step before must be done with separate * register writes. */ - val = I915_READ(DPCLKA_CFGCR0); + val = intel_de_read(dev_priv, DPCLKA_CFGCR0); val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); - I915_WRITE(DPCLKA_CFGCR0, val); + intel_de_write(dev_priv, DPCLKA_CFGCR0, val); } else if (IS_GEN9_BC(dev_priv)) { /* DDI -> PLL mapping */ - val = I915_READ(DPLL_CTRL2); + val = intel_de_read(dev_priv, DPLL_CTRL2); val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); - I915_WRITE(DPLL_CTRL2, val); + intel_de_write(dev_priv, DPLL_CTRL2, val); } else if (INTEL_GEN(dev_priv) < 9) { - I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); + intel_de_write(dev_priv, PORT_CLK_SEL(port), + hsw_pll_to_ddi_pll_sel(pll)); } - mutex_unlock(&dev_priv->dpll_lock); + mutex_unlock(&dev_priv->dpll.lock); } static void intel_ddi_clk_disable(struct intel_encoder *encoder) @@ -3155,15 +2828,17 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) if (INTEL_GEN(dev_priv) >= 11) { if (!intel_phy_is_combo(dev_priv, phy) || (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)) - I915_WRITE(DDI_CLK_SEL(port), DDI_CLK_SEL_NONE); + intel_de_write(dev_priv, DDI_CLK_SEL(port), + DDI_CLK_SEL_NONE); } else if (IS_CANNONLAKE(dev_priv)) { - I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | - DPCLKA_CFGCR0_DDI_CLK_OFF(port)); + intel_de_write(dev_priv, DPCLKA_CFGCR0, + intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); } else if (IS_GEN9_BC(dev_priv)) { - I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | - DPLL_CTRL2_DDI_CLK_OFF(port)); + intel_de_write(dev_priv, DPLL_CTRL2, + intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); } else if (INTEL_GEN(dev_priv) < 9) { - I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); + intel_de_write(dev_priv, PORT_CLK_SEL(port), + PORT_CLK_SEL_NONE); } } @@ -3180,13 +2855,15 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, return; if (INTEL_GEN(dev_priv) >= 12) { - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); - ln0 = I915_READ(DKL_DP_MODE(tc_port)); - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); - ln1 = I915_READ(DKL_DP_MODE(tc_port)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x0)); + ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x1)); + ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port)); } else { - ln0 = I915_READ(MG_DP_MODE(0, tc_port)); - ln1 = I915_READ(MG_DP_MODE(1, tc_port)); + ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)); + ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)); } ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X1_MODE); @@ -3198,7 +2875,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, switch (pin_assignment) { case 0x0: - WARN_ON(intel_dig_port->tc_mode != TC_PORT_LEGACY); + drm_WARN_ON(&dev_priv->drm, + intel_dig_port->tc_mode != TC_PORT_LEGACY); if (width == 1) { ln1 |= MG_DP_MODE_CFG_DP_X1_MODE; } else { @@ -3243,13 +2921,15 @@ icl_program_mg_dp_mode(struct intel_digital_port *intel_dig_port, } if (INTEL_GEN(dev_priv) >= 12) { - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x0)); - I915_WRITE(DKL_DP_MODE(tc_port), ln0); - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x1)); - I915_WRITE(DKL_DP_MODE(tc_port), ln1); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x0)); + intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x1)); + intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1); } else { - I915_WRITE(MG_DP_MODE(0, tc_port), ln0); - I915_WRITE(MG_DP_MODE(1, tc_port), ln1); + intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0); + intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1); } } @@ -3274,9 +2954,9 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, return; intel_dp = enc_to_intel_dp(encoder); - val = I915_READ(intel_dp->regs.dp_tp_ctl); + val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); val |= DP_TP_CTL_FEC_ENABLE; - I915_WRITE(intel_dp->regs.dp_tp_ctl, val); + intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_FEC_ENABLE_LIVE, 1)) @@ -3294,90 +2974,10 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, return; intel_dp = enc_to_intel_dp(encoder); - val = I915_READ(intel_dp->regs.dp_tp_ctl); + val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); val &= ~DP_TP_CTL_FEC_ENABLE; - I915_WRITE(intel_dp->regs.dp_tp_ctl, val); - POSTING_READ(intel_dp->regs.dp_tp_ctl); -} - -static void -tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) -{ - struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); - u32 val; - - if (!cstate->dc3co_exitline) - return; - - val = I915_READ(EXITLINE(cstate->cpu_transcoder)); - val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); - I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); -} - -static void -tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate) -{ - u32 val, exit_scanlines; - struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); - - if (!cstate->dc3co_exitline) - return; - - exit_scanlines = cstate->dc3co_exitline; - exit_scanlines <<= EXITLINE_SHIFT; - val = I915_READ(EXITLINE(cstate->cpu_transcoder)); - val &= ~(EXITLINE_MASK | EXITLINE_ENABLE); - val |= exit_scanlines; - val |= EXITLINE_ENABLE; - I915_WRITE(EXITLINE(cstate->cpu_transcoder), val); -} - -static void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder, - struct intel_crtc_state *cstate) -{ - u32 exit_scanlines; - struct drm_i915_private *dev_priv = to_i915(cstate->uapi.crtc->dev); - u32 crtc_vdisplay = cstate->hw.adjusted_mode.crtc_vdisplay; - - cstate->dc3co_exitline = 0; - - if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) - return; - - /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ - if (to_intel_crtc(cstate->uapi.crtc)->pipe != PIPE_A || - encoder->port != PORT_A) - return; - - if (!cstate->has_psr2 || !cstate->hw.active) - return; - - /* - * DC3CO Exit time 200us B.Spec 49196 - * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 - */ - exit_scanlines = - intel_usecs_to_scanlines(&cstate->hw.adjusted_mode, 200) + 1; - - if (WARN_ON(exit_scanlines > crtc_vdisplay)) - return; - - cstate->dc3co_exitline = crtc_vdisplay - exit_scanlines; - DRM_DEBUG_KMS("DC3CO exit scanlines %d\n", cstate->dc3co_exitline); -} - -static void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state) -{ - u32 val; - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - - if (INTEL_GEN(dev_priv) < 12) - return; - - val = I915_READ(EXITLINE(crtc_state->cpu_transcoder)); - - if (val & EXITLINE_ENABLE) - crtc_state->dc3co_exitline = val & EXITLINE_MASK; + intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); + intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); } static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, @@ -3392,7 +2992,6 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder, int level = intel_ddi_dp_level(intel_dp); enum transcoder transcoder = crtc_state->cpu_transcoder; - tgl_set_psr2_transcoder_exitline(crtc_state); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count, is_mst); @@ -3534,9 +3133,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, int level = intel_ddi_dp_level(intel_dp); if (INTEL_GEN(dev_priv) < 11) - WARN_ON(is_mst && (port == PORT_A || port == PORT_E)); + drm_WARN_ON(&dev_priv->drm, + is_mst && (port == PORT_A || port == PORT_E)); else - WARN_ON(is_mst && port == PORT_A); + drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count, is_mst); @@ -3607,8 +3207,11 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, /* MST will call a setting of MSA after an allocating of Virtual Channel * from MST encoder pre_enable callback. */ - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) + if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { intel_ddi_set_dp_msa(crtc_state, conn_state); + + intel_dp_set_m_n(crtc_state, M1_N1); + } } static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, @@ -3618,8 +3221,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - enum port port = encoder->port; - int level = intel_ddi_hdmi_level(dev_priv, port); + int level = intel_ddi_hdmi_level(encoder); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); @@ -3673,7 +3275,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *encoder, * the DP link parameteres */ - WARN_ON(crtc_state->has_pch_encoder); + drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); if (INTEL_GEN(dev_priv) >= 11) icl_map_plls_to_ports(encoder, crtc_state); @@ -3706,20 +3308,20 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, bool wait = false; u32 val; - val = I915_READ(DDI_BUF_CTL(port)); + val = intel_de_read(dev_priv, DDI_BUF_CTL(port)); if (val & DDI_BUF_CTL_ENABLE) { val &= ~DDI_BUF_CTL_ENABLE; - I915_WRITE(DDI_BUF_CTL(port), val); + intel_de_write(dev_priv, DDI_BUF_CTL(port), val); wait = true; } if (intel_crtc_has_dp_encoder(crtc_state)) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - val = I915_READ(intel_dp->regs.dp_tp_ctl); + val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); val |= DP_TP_CTL_LINK_TRAIN_PAT1; - I915_WRITE(intel_dp->regs.dp_tp_ctl, val); + intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); } /* Disable FEC in DP Sink */ @@ -3751,9 +3353,13 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; u32 val; - val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); - val &= ~TGL_TRANS_DDI_PORT_MASK; - I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), val); + val = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(cpu_transcoder)); + val &= ~(TGL_TRANS_DDI_PORT_MASK | + TRANS_DDI_MODE_SELECT_MASK); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL(cpu_transcoder), + val); } } else { if (!is_mst) @@ -3779,7 +3385,6 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder, dig_port->ddi_io_power_domain); intel_ddi_clk_disable(encoder); - tgl_clear_psr2_transcoder_exitline(old_crtc_state); } static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder, @@ -3816,7 +3421,8 @@ static void icl_disable_transcoder_port_sync(const struct intel_crtc_state *old_ DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n", transcoder_name(old_crtc_state->cpu_transcoder)); - I915_WRITE(TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0); } static void intel_ddi_post_disable(struct intel_encoder *encoder, @@ -3890,25 +3496,25 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *encoder, * step 13 is the correct place for it. Step 18 is where it was * originally before the BUN. */ - val = I915_READ(FDI_RX_CTL(PIPE_A)); + val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); val &= ~FDI_RX_ENABLE; - I915_WRITE(FDI_RX_CTL(PIPE_A), val); + intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); intel_disable_ddi_buf(encoder, old_crtc_state); intel_ddi_clk_disable(encoder); - val = I915_READ(FDI_RX_MISC(PIPE_A)); + val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A)); val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); - I915_WRITE(FDI_RX_MISC(PIPE_A), val); + intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val); - val = I915_READ(FDI_RX_CTL(PIPE_A)); + val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); val &= ~FDI_PCDCLK; - I915_WRITE(FDI_RX_CTL(PIPE_A), val); + intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); - val = I915_READ(FDI_RX_CTL(PIPE_A)); + val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); val &= ~FDI_RX_PLL_ENABLE; - I915_WRITE(FDI_RX_CTL(PIPE_A), val); + intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val); } static void intel_enable_ddi_dp(struct intel_encoder *encoder, @@ -3944,9 +3550,9 @@ gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv, [PORT_E] = TRANSCODER_A, }; - WARN_ON(INTEL_GEN(dev_priv) < 9); + drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9); - if (WARN_ON(port < PORT_A || port > PORT_E)) + if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) port = PORT_A; return CHICKEN_TRANS(trans[port]); @@ -3964,8 +3570,9 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, if (!intel_hdmi_handle_sink_scrambling(encoder, connector, crtc_state->hdmi_high_tmds_clock_ratio, crtc_state->hdmi_scrambling)) - DRM_ERROR("[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n", - connector->base.id, connector->name); + DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Failed to configure sink " + "scrambling/TMDS bit clock ratio\n", + connector->base.id, connector->name); /* Display WA #1143: skl,kbl,cfl */ if (IS_GEN9_BC(dev_priv)) { @@ -3978,7 +3585,7 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); u32 val; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if (port == PORT_E) val |= DDIE_TRAINING_OVERRIDE_ENABLE | @@ -3987,8 +3594,8 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, val |= DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); udelay(1); @@ -3999,15 +3606,15 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, val &= ~(DDI_TRAINING_OVERRIDE_ENABLE | DDI_TRAINING_OVERRIDE_VALUE); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } /* In HDMI/DVI mode, the port width, and swing/emphasis values * are ignored so nothing special needs to be done besides * enabling the port. */ - I915_WRITE(DDI_BUF_CTL(port), - dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); + intel_de_write(dev_priv, DDI_BUF_CTL(port), + dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE); if (crtc_state->has_audio) intel_audio_codec_enable(encoder, crtc_state, conn_state); @@ -4017,6 +3624,12 @@ static void intel_enable_ddi(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { + WARN_ON(crtc_state->has_pch_encoder); + + intel_enable_pipe(crtc_state); + + intel_crtc_vblank_on(crtc_state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) intel_enable_ddi_hdmi(encoder, crtc_state, conn_state); else @@ -4096,43 +3709,11 @@ static void intel_ddi_update_pipe(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { - struct intel_connector *connector = - to_intel_connector(conn_state->connector); - struct intel_hdcp *hdcp = &connector->hdcp; - bool content_protection_type_changed = - (conn_state->hdcp_content_type != hdcp->content_type && - conn_state->content_protection != - DRM_MODE_CONTENT_PROTECTION_UNDESIRED); if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) intel_ddi_update_pipe_dp(encoder, crtc_state, conn_state); - /* - * During the HDCP encryption session if Type change is requested, - * disable the HDCP and reenable it with new TYPE value. - */ - if (conn_state->content_protection == - DRM_MODE_CONTENT_PROTECTION_UNDESIRED || - content_protection_type_changed) - intel_hdcp_disable(connector); - - /* - * Mark the hdcp state as DESIRED after the hdcp disable of type - * change procedure. - */ - if (content_protection_type_changed) { - mutex_lock(&hdcp->mutex); - hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; - schedule_work(&hdcp->prop_work); - mutex_unlock(&hdcp->mutex); - } - - if (conn_state->content_protection == - DRM_MODE_CONTENT_PROTECTION_DESIRED || - content_protection_type_changed) - intel_hdcp_enable(connector, - crtc_state->cpu_transcoder, - (u8)conn_state->hdcp_content_type); + intel_hdcp_update_pipe(encoder, crtc_state, conn_state); } static void @@ -4197,20 +3778,20 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) u32 dp_tp_ctl, ddi_buf_ctl; bool wait = false; - dp_tp_ctl = I915_READ(intel_dp->regs.dp_tp_ctl); + dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); if (dp_tp_ctl & DP_TP_CTL_ENABLE) { - ddi_buf_ctl = I915_READ(DDI_BUF_CTL(port)); + ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)); if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) { - I915_WRITE(DDI_BUF_CTL(port), - ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); + intel_de_write(dev_priv, DDI_BUF_CTL(port), + ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE); wait = true; } dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1; - I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl); - POSTING_READ(intel_dp->regs.dp_tp_ctl); + intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); + intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); if (wait) intel_wait_ddi_buf_idle(dev_priv, port); @@ -4225,12 +3806,12 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp) if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; } - I915_WRITE(intel_dp->regs.dp_tp_ctl, dp_tp_ctl); - POSTING_READ(intel_dp->regs.dp_tp_ctl); + intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl); + intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl); intel_dp->DP |= DDI_BUF_CTL_ENABLE; - I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); - POSTING_READ(DDI_BUF_CTL(port)); + intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); + intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)); udelay(600); } @@ -4244,14 +3825,16 @@ static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv, if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) return false; - return I915_READ(HSW_AUD_PIN_ELD_CP_VLD) & + return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) & AUDIO_OUTPUT_ENABLE(cpu_transcoder); } void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, struct intel_crtc_state *crtc_state) { - if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) + if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000) + crtc_state->min_voltage_level = 2; + else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000) crtc_state->min_voltage_level = 3; else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000) crtc_state->min_voltage_level = 1; @@ -4268,12 +3851,12 @@ void intel_ddi_get_config(struct intel_encoder *encoder, u32 temp, flags = 0; /* XXX: DSI transcoder paranoia */ - if (WARN_ON(transcoder_is_dsi(cpu_transcoder))) + if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) return; intel_dsc_get_config(encoder, pipe_config); - temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); if (temp & TRANS_DDI_PHSYNC) flags |= DRM_MODE_FLAG_PHSYNC; else @@ -4342,7 +3925,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder); pipe_config->fec_enable = - I915_READ(dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; + intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE; DRM_DEBUG_KMS("[ENCODER:%d:%s] Fec status: %u\n", encoder->base.base.id, encoder->base.name, @@ -4365,9 +3948,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, break; } - if (encoder->type == INTEL_OUTPUT_EDP) - tgl_dc3co_exitline_get_config(pipe_config); - pipe_config->has_audio = intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); @@ -4449,7 +4029,6 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); } else { ret = intel_dp_compute_config(encoder, pipe_config, conn_state); - tgl_dc3co_exitline_compute_config(encoder, pipe_config); } if (ret) @@ -4470,6 +4049,112 @@ static int intel_ddi_compute_config(struct intel_encoder *encoder, return 0; } +static bool mode_equal(const struct drm_display_mode *mode1, + const struct drm_display_mode *mode2) +{ + return drm_mode_match(mode1, mode2, + DRM_MODE_MATCH_TIMINGS | + DRM_MODE_MATCH_FLAGS | + DRM_MODE_MATCH_3D_FLAGS) && + mode1->clock == mode2->clock; /* we want an exact match */ +} + +static bool m_n_equal(const struct intel_link_m_n *m_n_1, + const struct intel_link_m_n *m_n_2) +{ + return m_n_1->tu == m_n_2->tu && + m_n_1->gmch_m == m_n_2->gmch_m && + m_n_1->gmch_n == m_n_2->gmch_n && + m_n_1->link_m == m_n_2->link_m && + m_n_1->link_n == m_n_2->link_n; +} + +static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, + const struct intel_crtc_state *crtc_state2) +{ + return crtc_state1->hw.active && crtc_state2->hw.active && + crtc_state1->output_types == crtc_state2->output_types && + crtc_state1->output_format == crtc_state2->output_format && + crtc_state1->lane_count == crtc_state2->lane_count && + crtc_state1->port_clock == crtc_state2->port_clock && + mode_equal(&crtc_state1->hw.adjusted_mode, + &crtc_state2->hw.adjusted_mode) && + m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); +} + +static u8 +intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, + int tile_group_id) +{ + struct drm_connector *connector; + const struct drm_connector_state *conn_state; + struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); + struct intel_atomic_state *state = + to_intel_atomic_state(ref_crtc_state->uapi.state); + u8 transcoders = 0; + int i; + + if (INTEL_GEN(dev_priv) < 11) + return 0; + + if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) + return 0; + + for_each_new_connector_in_state(&state->base, connector, conn_state, i) { + struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); + const struct intel_crtc_state *crtc_state; + + if (!crtc) + continue; + + if (!connector->has_tile || + connector->tile_group->id != + tile_group_id) + continue; + crtc_state = intel_atomic_get_new_crtc_state(state, + crtc); + if (!crtcs_port_sync_compatible(ref_crtc_state, + crtc_state)) + continue; + transcoders |= BIT(crtc_state->cpu_transcoder); + } + + return transcoders; +} + +static int intel_ddi_compute_config_late(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_connector *connector = conn_state->connector; + u8 port_sync_transcoders = 0; + + DRM_DEBUG_KMS("[ENCODER:%d:%s] [CRTC:%d:%s]", + encoder->base.base.id, encoder->base.name, + crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); + + if (connector->has_tile) + port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, + connector->tile_group->id); + + /* + * EDP Transcoders cannot be ensalved + * make them a master always when present + */ + if (port_sync_transcoders & BIT(TRANSCODER_EDP)) + crtc_state->master_transcoder = TRANSCODER_EDP; + else + crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; + + if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { + crtc_state->master_transcoder = INVALID_TRANSCODER; + crtc_state->sync_mode_slaves_mask = + port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); + } + + return 0; +} + static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) { struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); @@ -4569,7 +4254,8 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, crtc_state = to_intel_crtc_state(crtc->base.state); - WARN_ON(!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); + drm_WARN_ON(&dev_priv->drm, + !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)); if (!crtc_state->hw.active) return 0; @@ -4636,7 +4322,8 @@ intel_ddi_hotplug(struct intel_encoder *encoder, drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); - WARN(ret, "Acquiring modeset locks failed with %i\n", ret); + drm_WARN(encoder->base.dev, ret, + "Acquiring modeset locks failed with %i\n", ret); /* * Unpowered type-c dongles can take some time to boot and be @@ -4716,7 +4403,7 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) return max_lanes; if (port == PORT_A || port == PORT_E) { - if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) max_lanes = port == PORT_A ? 4 : 0; else /* Both A and E share 2 lanes */ @@ -4739,15 +4426,14 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) { - struct ddi_vbt_port_info *port_info = - &dev_priv->vbt.ddi_port_info[port]; struct intel_digital_port *intel_dig_port; struct intel_encoder *encoder; bool init_hdmi, init_dp, init_lspcon = false; enum phy phy = intel_port_to_phy(dev_priv, port); - init_hdmi = port_info->supports_dvi || port_info->supports_hdmi; - init_dp = port_info->supports_dp; + init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) || + intel_bios_port_supports_hdmi(dev_priv, port); + init_dp = intel_bios_port_supports_dp(dev_priv, port); if (intel_bios_is_lspcon_present(dev_priv, port)) { /* @@ -4779,6 +4465,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->hotplug = intel_ddi_hotplug; encoder->compute_output_type = intel_ddi_compute_output_type; encoder->compute_config = intel_ddi_compute_config; + encoder->compute_config_late = intel_ddi_compute_config_late; encoder->enable = intel_enable_ddi; encoder->pre_pll_enable = intel_ddi_pre_pll_enable; encoder->pre_enable = intel_ddi_pre_enable; @@ -4797,10 +4484,12 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->pipe_mask = ~0; if (INTEL_GEN(dev_priv) >= 11) - intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & + intel_dig_port->saved_port_bits = intel_de_read(dev_priv, + DDI_BUF_CTL(port)) & DDI_BUF_PORT_REVERSAL; else - intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & + intel_dig_port->saved_port_bits = intel_de_read(dev_priv, + DDI_BUF_CTL(port)) & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES); intel_dig_port->dp.output_reg = INVALID_MMIO_REG; @@ -4808,8 +4497,9 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); if (intel_phy_is_tc(dev_priv, phy)) { - bool is_legacy = !port_info->supports_typec_usb && - !port_info->supports_tbt; + bool is_legacy = + !intel_bios_port_supports_typec_usb(dev_priv, port) && + !intel_bios_port_supports_tbt(dev_priv, port); intel_tc_port_init(intel_dig_port, is_legacy); @@ -4817,7 +4507,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) encoder->update_complete = intel_ddi_update_complete; } - WARN_ON(port > PORT_I); + drm_WARN_ON(&dev_priv->drm, port > PORT_I); intel_dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO + port - PORT_A; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h index 167c6579d972..55fd72b901fe 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h @@ -6,8 +6,6 @@ #ifndef __INTEL_DDI_H__ #define __INTEL_DDI_H__ -#include <drm/i915_drm.h> - #include "intel_display.h" struct drm_connector_state; @@ -47,7 +45,5 @@ u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder, int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, bool enable); void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); -int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, - struct intel_dpll_hw_state *state); #endif /* __INTEL_DDI_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h new file mode 100644 index 000000000000..00da10bf35f5 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_de.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2019 Intel Corporation + */ + +#ifndef __INTEL_DE_H__ +#define __INTEL_DE_H__ + +#include "i915_drv.h" +#include "i915_reg.h" +#include "intel_uncore.h" + +static inline u32 +intel_de_read(struct drm_i915_private *i915, i915_reg_t reg) +{ + return intel_uncore_read(&i915->uncore, reg); +} + +static inline void +intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg) +{ + intel_uncore_posting_read(&i915->uncore, reg); +} + +/* Note: read the warnings for intel_uncore_*_fw() functions! */ +static inline u32 +intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg) +{ + return intel_uncore_read_fw(&i915->uncore, reg); +} + +static inline void +intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val) +{ + intel_uncore_write(&i915->uncore, reg, val); +} + +/* Note: read the warnings for intel_uncore_*_fw() functions! */ +static inline void +intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val) +{ + intel_uncore_write_fw(&i915->uncore, reg, val); +} + +static inline void +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) +{ + intel_uncore_rmw(&i915->uncore, reg, clear, set); +} + +static inline int +intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, u32 value, unsigned int timeout) +{ + return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout); +} + +static inline int +intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, unsigned int timeout) +{ + return intel_de_wait_for_register(i915, reg, mask, mask, timeout); +} + +static inline int +intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg, + u32 mask, unsigned int timeout) +{ + return intel_de_wait_for_register(i915, reg, mask, 0, timeout); +} + +#endif /* __INTEL_DE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index aa453953908b..346846609f45 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -41,7 +41,6 @@ #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_rect.h> -#include <drm/i915_drm.h> #include "display/intel_crt.h" #include "display/intel_ddi.h" @@ -203,9 +202,9 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv, val = vlv_cck_read(dev_priv, reg); divider = val & CCK_FREQUENCY_VALUES; - WARN((val & CCK_FREQUENCY_STATUS) != - (divider << CCK_FREQUENCY_STATUS_SHIFT), - "%s change in progress\n", name); + drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != + (divider << CCK_FREQUENCY_STATUS_SHIFT), + "%s change in progress\n", name); return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); } @@ -235,7 +234,8 @@ static void intel_update_czclk(struct drm_i915_private *dev_priv) dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", CCK_CZ_CLOCK_CONTROL); - DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); + drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", + dev_priv->czclk_freq); } static inline u32 /* units of 100MHz */ @@ -518,13 +518,11 @@ static void skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { if (enable) - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) | - DUPS1_GATING_DIS | DUPS2_GATING_DIS); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DUPS1_GATING_DIS | DUPS2_GATING_DIS); else - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) & - ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS)); } /* Wa_2006604312:icl */ @@ -533,11 +531,11 @@ icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) { if (enable) - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); else - I915_WRITE(CLKGATE_DIS_PSL(pipe), - I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), + intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); } static bool @@ -883,7 +881,7 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, return calculated_clock->p > best_clock->p; } - if (WARN_ON_ONCE(!target_freq)) + if (drm_WARN_ON_ONCE(dev, !target_freq)) return false; *error_ppm = div_u64(1000000ULL * @@ -1049,9 +1047,9 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, else line_mask = DSL_LINEMASK_GEN3; - line1 = I915_READ(reg) & line_mask; + line1 = intel_de_read(dev_priv, reg) & line_mask; msleep(5); - line2 = I915_READ(reg) & line_mask; + line2 = intel_de_read(dev_priv, reg) & line_mask; return line1 != line2; } @@ -1063,8 +1061,9 @@ static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) /* Wait for the display line to settle/start moving */ if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) - DRM_ERROR("pipe %c scanline %s wait timed out\n", - pipe_name(pipe), onoff(state)); + drm_err(&dev_priv->drm, + "pipe %c scanline %s wait timed out\n", + pipe_name(pipe), onoff(state)); } static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) @@ -1090,7 +1089,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) /* Wait for the Pipe State to go off */ if (intel_de_wait_for_clear(dev_priv, reg, I965_PIPECONF_ACTIVE, 100)) - WARN(1, "pipe_off wait timed out\n"); + drm_WARN(&dev_priv->drm, 1, + "pipe_off wait timed out\n"); } else { intel_wait_for_pipe_scanline_stopped(crtc); } @@ -1103,7 +1103,7 @@ void assert_pll(struct drm_i915_private *dev_priv, u32 val; bool cur_state; - val = I915_READ(DPLL(pipe)); + val = intel_de_read(dev_priv, DPLL(pipe)); cur_state = !!(val & DPLL_VCO_ENABLE); I915_STATE_WARN(cur_state != state, "PLL state assertion failure (expected %s, current %s)\n", @@ -1139,10 +1139,11 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv, * so pipe->transcoder cast is fine here. */ enum transcoder cpu_transcoder = (enum transcoder)pipe; - u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + u32 val = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(cpu_transcoder)); cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); } else { - u32 val = I915_READ(FDI_TX_CTL(pipe)); + u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); cur_state = !!(val & FDI_TX_ENABLE); } I915_STATE_WARN(cur_state != state, @@ -1158,7 +1159,7 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv, u32 val; bool cur_state; - val = I915_READ(FDI_RX_CTL(pipe)); + val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); cur_state = !!(val & FDI_RX_ENABLE); I915_STATE_WARN(cur_state != state, "FDI RX state assertion failure (expected %s, current %s)\n", @@ -1180,7 +1181,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, if (HAS_DDI(dev_priv)) return; - val = I915_READ(FDI_TX_CTL(pipe)); + val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)); I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); } @@ -1190,7 +1191,7 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, u32 val; bool cur_state; - val = I915_READ(FDI_RX_CTL(pipe)); + val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)); cur_state = !!(val & FDI_RX_PLL_ENABLE); I915_STATE_WARN(cur_state != state, "FDI RX PLL assertion failure (expected %s, current %s)\n", @@ -1204,14 +1205,14 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) enum pipe panel_pipe = INVALID_PIPE; bool locked = true; - if (WARN_ON(HAS_DDI(dev_priv))) + if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))) return; if (HAS_PCH_SPLIT(dev_priv)) { u32 port_sel; pp_reg = PP_CONTROL(0); - port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; + port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; switch (port_sel) { case PANEL_PORT_SELECT_LVDS: @@ -1238,13 +1239,14 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) u32 port_sel; pp_reg = PP_CONTROL(0); - port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; + port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; - WARN_ON(port_sel != PANEL_PORT_SELECT_LVDS); + drm_WARN_ON(&dev_priv->drm, + port_sel != PANEL_PORT_SELECT_LVDS); intel_lvds_port_enabled(dev_priv, LVDS, &panel_pipe); } - val = I915_READ(pp_reg); + val = intel_de_read(dev_priv, pp_reg); if (!(val & PANEL_POWER_ON) || ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) locked = false; @@ -1268,7 +1270,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); if (wakeref) { - u32 val = I915_READ(PIPECONF(cpu_transcoder)); + u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); cur_state = !!(val & PIPECONF_ENABLE); intel_display_power_put(dev_priv, power_domain, wakeref); @@ -1318,7 +1320,7 @@ void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, u32 val; bool enabled; - val = I915_READ(PCH_TRANSCONF(pipe)); + val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); enabled = !!(val & TRANS_ENABLE); I915_STATE_WARN(enabled, "transcoder assertion failed, should be off on pipe %c but is still active\n", @@ -1392,12 +1394,12 @@ static void _vlv_enable_pll(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); + intel_de_posting_read(dev_priv, DPLL(pipe)); udelay(150); if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) - DRM_ERROR("DPLL %d failed to lock\n", pipe); + drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); } static void vlv_enable_pll(struct intel_crtc *crtc, @@ -1414,8 +1416,9 @@ static void vlv_enable_pll(struct intel_crtc *crtc, if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) _vlv_enable_pll(crtc, pipe_config); - I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); - POSTING_READ(DPLL_MD(pipe)); + intel_de_write(dev_priv, DPLL_MD(pipe), + pipe_config->dpll_hw_state.dpll_md); + intel_de_posting_read(dev_priv, DPLL_MD(pipe)); } @@ -1442,11 +1445,11 @@ static void _chv_enable_pll(struct intel_crtc *crtc, udelay(1); /* Enable PLL */ - I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); + intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); /* Check PLL is locked */ if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) - DRM_ERROR("PLL %d failed to lock\n", pipe); + drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); } static void chv_enable_pll(struct intel_crtc *crtc, @@ -1470,19 +1473,23 @@ static void chv_enable_pll(struct intel_crtc *crtc, * DPLLCMD is AWOL. Use chicken bits to propagate * the value from DPLLBMD to either pipe B or C. */ - I915_WRITE(CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); - I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); - I915_WRITE(CBR4_VLV, 0); + intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); + intel_de_write(dev_priv, DPLL_MD(PIPE_B), + pipe_config->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, CBR4_VLV, 0); dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; /* * DPLLB VGA mode also seems to cause problems. * We should always have it disabled. */ - WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); + drm_WARN_ON(&dev_priv->drm, + (intel_de_read(dev_priv, DPLL(PIPE_B)) & + DPLL_VGA_MODE_DIS) == 0); } else { - I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); - POSTING_READ(DPLL_MD(pipe)); + intel_de_write(dev_priv, DPLL_MD(pipe), + pipe_config->dpll_hw_state.dpll_md); + intel_de_posting_read(dev_priv, DPLL_MD(pipe)); } } @@ -1513,29 +1520,29 @@ static void i9xx_enable_pll(struct intel_crtc *crtc, * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS); - I915_WRITE(reg, dpll); + intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); + intel_de_write(dev_priv, reg, dpll); /* Wait for the clocks to stabilize. */ - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE(DPLL_MD(crtc->pipe), - crtc_state->dpll_hw_state.dpll_md); + intel_de_write(dev_priv, DPLL_MD(crtc->pipe), + crtc_state->dpll_hw_state.dpll_md); } else { /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. * * So write it again. */ - I915_WRITE(reg, dpll); + intel_de_write(dev_priv, reg, dpll); } /* We do this three times for luck */ for (i = 0; i < 3; i++) { - I915_WRITE(reg, dpll); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, dpll); + intel_de_posting_read(dev_priv, reg); udelay(150); /* wait for warmup */ } } @@ -1553,8 +1560,8 @@ static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) /* Make sure the pipe isn't still relying on us */ assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); - I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); + intel_de_posting_read(dev_priv, DPLL(pipe)); } static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -1569,8 +1576,8 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - I915_WRITE(DPLL(pipe), val); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), val); + intel_de_posting_read(dev_priv, DPLL(pipe)); } static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -1586,8 +1593,8 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - I915_WRITE(DPLL(pipe), val); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), val); + intel_de_posting_read(dev_priv, DPLL(pipe)); vlv_dpio_get(dev_priv); @@ -1626,9 +1633,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, if (intel_de_wait_for_register(dev_priv, dpll_reg, port_mask, expected_mask, 1000)) - WARN(1, "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", - dport->base.base.base.id, dport->base.base.name, - I915_READ(dpll_reg) & port_mask, expected_mask); + drm_WARN(&dev_priv->drm, 1, + "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n", + dport->base.base.base.id, dport->base.base.name, + intel_de_read(dev_priv, dpll_reg) & port_mask, + expected_mask); } static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) @@ -1648,7 +1657,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) if (HAS_PCH_CPT(dev_priv)) { reg = TRANS_CHICKEN2(pipe); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); /* * Workaround: Set the timing override bit * before enabling the pch transcoder. @@ -1657,12 +1666,12 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) /* Configure frame start delay to match the CPU */ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } reg = PCH_TRANSCONF(pipe); - val = I915_READ(reg); - pipeconf_val = I915_READ(PIPECONF(pipe)); + val = intel_de_read(dev_priv, reg); + pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)); if (HAS_PCH_IBX(dev_priv)) { /* Configure frame start delay to match the CPU */ @@ -1692,9 +1701,10 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) val |= TRANS_PROGRESSIVE; } - I915_WRITE(reg, val | TRANS_ENABLE); + intel_de_write(dev_priv, reg, val | TRANS_ENABLE); if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE, 100)) - DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); + drm_err(&dev_priv->drm, "failed to enable transcoder %c\n", + pipe_name(pipe)); } static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, @@ -1706,16 +1716,16 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); assert_fdi_rx_enabled(dev_priv, PIPE_A); - val = I915_READ(TRANS_CHICKEN2(PIPE_A)); + val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); /* Workaround: set timing override bit. */ val |= TRANS_CHICKEN2_TIMING_OVERRIDE; /* Configure frame start delay to match the CPU */ val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); - I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); + intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); val = TRANS_ENABLE; - pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); + pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACED_ILK) @@ -1723,10 +1733,10 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, else val |= TRANS_PROGRESSIVE; - I915_WRITE(LPT_TRANSCONF, val); + intel_de_write(dev_priv, LPT_TRANSCONF, val); if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF, TRANS_STATE_ENABLE, 100)) - DRM_ERROR("Failed to enable PCH transcoder\n"); + drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n"); } static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv, @@ -1743,19 +1753,20 @@ static void ilk_disable_pch_transcoder(struct drm_i915_private *dev_priv, assert_pch_ports_disabled(dev_priv, pipe); reg = PCH_TRANSCONF(pipe); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~TRANS_ENABLE; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); /* wait for PCH transcoder off, transcoder state */ if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50)) - DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); + drm_err(&dev_priv->drm, "failed to disable transcoder %c\n", + pipe_name(pipe)); if (HAS_PCH_CPT(dev_priv)) { /* Workaround: Clear the timing override chicken bit again. */ reg = TRANS_CHICKEN2(pipe); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } } @@ -1763,18 +1774,18 @@ void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) { u32 val; - val = I915_READ(LPT_TRANSCONF); + val = intel_de_read(dev_priv, LPT_TRANSCONF); val &= ~TRANS_ENABLE; - I915_WRITE(LPT_TRANSCONF, val); + intel_de_write(dev_priv, LPT_TRANSCONF, val); /* wait for PCH transcoder off, transcoder state */ if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF, TRANS_STATE_ENABLE, 50)) - DRM_ERROR("Failed to disable PCH transcoder\n"); + drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n"); /* Workaround: clear timing override bit. */ - val = I915_READ(TRANS_CHICKEN2(PIPE_A)); + val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; - I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); + intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); } enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) @@ -1807,7 +1818,7 @@ static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state return 0; /* Gen2 doesn't have a hardware frame counter */ } -static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) +void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -1825,7 +1836,7 @@ void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) assert_vblank_disabled(&crtc->base); } -static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) +void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -1834,7 +1845,7 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) i915_reg_t reg; u32 val; - DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe)); assert_planes_disabled(crtc); @@ -1862,15 +1873,15 @@ static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) trace_intel_pipe_enable(crtc); reg = PIPECONF(cpu_transcoder); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if (val & PIPECONF_ENABLE) { /* we keep both pipes enabled on 830 */ - WARN_ON(!IS_I830(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); return; } - I915_WRITE(reg, val | PIPECONF_ENABLE); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE); + intel_de_posting_read(dev_priv, reg); /* * Until the pipe starts PIPEDSL reads will return a stale value, @@ -1892,7 +1903,7 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) i915_reg_t reg; u32 val; - DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe)); /* * Make sure planes won't keep trying to pump pixels to us, @@ -1903,7 +1914,7 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) trace_intel_pipe_disable(crtc); reg = PIPECONF(cpu_transcoder); - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if ((val & PIPECONF_ENABLE) == 0) return; @@ -1918,7 +1929,7 @@ void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) if (!IS_I830(dev_priv)) val &= ~PIPECONF_ENABLE; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); if ((val & PIPECONF_ENABLE) == 0) intel_wait_for_pipe_off(old_crtc_state); } @@ -2211,11 +2222,11 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int pinctl; u32 alignment; - if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) + if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); alignment = intel_surf_alignment(fb, 0); - if (WARN_ON(alignment && !is_power_of_2(alignment))) + if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) return ERR_PTR(-EINVAL); /* Note that the w/a also requires 64 PTE of padding following the @@ -2386,7 +2397,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y, struct drm_i915_private *dev_priv = to_i915(fb->dev); unsigned int cpp = fb->format->cpp[color_plane]; - WARN_ON(new_offset > old_offset); + drm_WARN_ON(&dev_priv->drm, new_offset > old_offset); if (!is_surface_linear(fb, color_plane)) { unsigned int tile_size, tile_width, tile_height; @@ -2537,8 +2548,9 @@ static int intel_fb_offset_to_xy(int *x, int *y, alignment = 0; if (alignment != 0 && fb->offsets[color_plane] % alignment) { - DRM_DEBUG_KMS("Misaligned offset 0x%08x for color plane %d\n", - fb->offsets[color_plane], color_plane); + drm_dbg_kms(&dev_priv->drm, + "Misaligned offset 0x%08x for color plane %d\n", + fb->offsets[color_plane], color_plane); return -EINVAL; } @@ -2548,9 +2560,10 @@ static int intel_fb_offset_to_xy(int *x, int *y, /* Catch potential overflows early */ if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]), fb->offsets[color_plane])) { - DRM_DEBUG_KMS("Bad offset 0x%08x or pitch %d for color plane %d\n", - fb->offsets[color_plane], fb->pitches[color_plane], - color_plane); + drm_dbg_kms(&dev_priv->drm, + "Bad offset 0x%08x or pitch %d for color plane %d\n", + fb->offsets[color_plane], fb->pitches[color_plane], + color_plane); return -ERANGE; } @@ -2706,9 +2719,10 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, /* * We assume the primary plane for pipe A has - * the highest stride limits of them all. + * the highest stride limits of them all, + * if in case pipe A is disabled, use the first pipe from pipe_mask. */ - crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); + crtc = intel_get_first_crtc(dev_priv); if (!crtc) return 0; @@ -3034,8 +3048,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, ret = intel_fb_offset_to_xy(&x, &y, fb, i); if (ret) { - DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", - i, fb->offsets[i]); + drm_dbg_kms(&dev_priv->drm, + "bad fb plane %d offset: 0x%x\n", + i, fb->offsets[i]); return ret; } @@ -3054,8 +3069,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, */ if (i == 0 && i915_gem_object_is_tiled(obj) && (x + width) * cpp > fb->pitches[i]) { - DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", - i, fb->offsets[i]); + drm_dbg_kms(&dev_priv->drm, + "bad fb plane %d offset: 0x%x\n", + i, fb->offsets[i]); return -EINVAL; } @@ -3111,8 +3127,9 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv, } if (mul_u32_u32(max_size, tile_size) > obj->base.size) { - DRM_DEBUG_KMS("fb too big for bo (need %llu bytes, have %zu bytes)\n", - mul_u32_u32(max_size, tile_size), obj->base.size); + drm_dbg_kms(&dev_priv->drm, + "fb too big for bo (need %llu bytes, have %zu bytes)\n", + mul_u32_u32(max_size, tile_size), obj->base.size); return -EINVAL; } @@ -3143,7 +3160,7 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state) src_w = drm_rect_width(&plane_state->uapi.src) >> 16; src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - WARN_ON(is_ccs_modifier(fb->modifier)); + drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier)); /* Make src coordinates relative to the viewport */ drm_rect_translate(&plane_state->uapi.src, @@ -3184,7 +3201,7 @@ intel_plane_remap_gtt(struct intel_plane_state *plane_state) DRM_MODE_ROTATE_0, tile_size); offset /= tile_size; - WARN_ON(i >= ARRAY_SIZE(info->plane)); + drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane)); info->plane[i].offset = offset; info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); @@ -3377,6 +3394,67 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) } } +static struct i915_vma * +initial_plane_vma(struct drm_i915_private *i915, + struct intel_initial_plane_config *plane_config) +{ + struct drm_i915_gem_object *obj; + struct i915_vma *vma; + u32 base, size; + + if (plane_config->size == 0) + return NULL; + + base = round_down(plane_config->base, + I915_GTT_MIN_ALIGNMENT); + size = round_up(plane_config->base + plane_config->size, + I915_GTT_MIN_ALIGNMENT); + size -= base; + + /* + * If the FB is too big, just don't use it since fbdev is not very + * important and we should probably use that space with FBC or other + * features. + */ + if (size * 2 > i915->stolen_usable_size) + return NULL; + + obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size); + if (IS_ERR(obj)) + return NULL; + + switch (plane_config->tiling) { + case I915_TILING_NONE: + break; + case I915_TILING_X: + case I915_TILING_Y: + obj->tiling_and_stride = + plane_config->fb->base.pitches[0] | + plane_config->tiling; + break; + default: + MISSING_CASE(plane_config->tiling); + goto err_obj; + } + + vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL); + if (IS_ERR(vma)) + goto err_obj; + + if (i915_ggtt_pin(vma, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base)) + goto err_obj; + + if (i915_gem_object_is_tiled(obj) && + !i915_vma_is_map_and_fenceable(vma)) + goto err_obj; + + return vma; + +err_obj: + i915_gem_object_put(obj); + return NULL; +} + static bool intel_alloc_initial_plane_obj(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config) @@ -3385,22 +3463,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); struct drm_mode_fb_cmd2 mode_cmd = { 0 }; struct drm_framebuffer *fb = &plane_config->fb->base; - u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); - u32 size_aligned = round_up(plane_config->base + plane_config->size, - PAGE_SIZE); - struct drm_i915_gem_object *obj; - bool ret = false; - - size_aligned -= base_aligned; - - if (plane_config->size == 0) - return false; - - /* If the FB is too big, just don't use it since fbdev is not very - * important and we should probably use that space with FBC or other - * features. */ - if (size_aligned * 2 > dev_priv->stolen_usable_size) - return false; + struct i915_vma *vma; switch (fb->modifier) { case DRM_FORMAT_MOD_LINEAR: @@ -3408,30 +3471,16 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, case I915_FORMAT_MOD_Y_TILED: break; default: - DRM_DEBUG_DRIVER("Unsupported modifier for initial FB: 0x%llx\n", - fb->modifier); + drm_dbg(&dev_priv->drm, + "Unsupported modifier for initial FB: 0x%llx\n", + fb->modifier); return false; } - obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, - base_aligned, - base_aligned, - size_aligned); - if (IS_ERR(obj)) + vma = initial_plane_vma(dev_priv, plane_config); + if (!vma) return false; - switch (plane_config->tiling) { - case I915_TILING_NONE: - break; - case I915_TILING_X: - case I915_TILING_Y: - obj->tiling_and_stride = fb->pitches[0] | plane_config->tiling; - break; - default: - MISSING_CASE(plane_config->tiling); - goto out; - } - mode_cmd.pixel_format = fb->format->format; mode_cmd.width = fb->width; mode_cmd.height = fb->height; @@ -3439,17 +3488,18 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, mode_cmd.modifier[0] = fb->modifier; mode_cmd.flags = DRM_MODE_FB_MODIFIERS; - if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { - DRM_DEBUG_KMS("intel fb init failed\n"); - goto out; + if (intel_framebuffer_init(to_intel_framebuffer(fb), + vma->obj, &mode_cmd)) { + drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); + goto err_vma; } + plane_config->vma = vma; + return true; - DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); - ret = true; -out: - i915_gem_object_put(obj); - return ret; +err_vma: + i915_vma_put(vma); + return false; } static void @@ -3493,9 +3543,10 @@ static void intel_plane_disable_noatomic(struct intel_crtc *crtc, struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state); - DRM_DEBUG_KMS("Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", - plane->base.base.id, plane->base.name, - crtc->base.base.id, crtc->base.name); + drm_dbg_kms(&dev_priv->drm, + "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n", + plane->base.base.id, plane->base.name, + crtc->base.base.id, crtc->base.name); intel_set_plane_visible(crtc_state, plane_state, false); fixup_active_planes(crtc_state); @@ -3547,17 +3598,17 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, struct intel_plane_state *intel_state = to_intel_plane_state(plane_state); struct drm_framebuffer *fb; + struct i915_vma *vma; if (!plane_config->fb) return; if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { fb = &plane_config->fb->base; + vma = plane_config->vma; goto valid_fb; } - kfree(plane_config->fb); - /* * Failed to alloc the obj, check to see if we should share * an fb with another CRTC instead @@ -3577,7 +3628,7 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, if (intel_plane_ggtt_offset(state) == plane_config->base) { fb = state->hw.fb; - drm_framebuffer_get(fb); + vma = state->vma; goto valid_fb; } } @@ -3600,21 +3651,11 @@ valid_fb: intel_state->color_plane[0].stride = intel_fb_pitch(fb, 0, intel_state->hw.rotation); - intel_state->vma = - intel_pin_and_fence_fb_obj(fb, - &intel_state->view, - intel_plane_uses_fence(intel_state), - &intel_state->flags); - if (IS_ERR(intel_state->vma)) { - DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", - intel_crtc->pipe, PTR_ERR(intel_state->vma)); - - intel_state->vma = NULL; - drm_framebuffer_put(fb); - return; - } - - intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); + __i915_vma_pin(vma); + intel_state->vma = i915_vma_get(vma); + if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0) + if (vma->fence) + intel_state->flags |= PLANE_HAS_FENCE; plane_state->src_x = 0; plane_state->src_y = 0; @@ -3633,9 +3674,13 @@ valid_fb: dev_priv->preserve_bios_swizzle = true; plane_state->fb = fb; + drm_framebuffer_get(fb); + plane_state->crtc = &intel_crtc->base; intel_plane_copy_uapi_to_hw_state(intel_state, intel_state); + intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); + atomic_or(to_intel_plane(primary)->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits); } @@ -3798,15 +3843,16 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) max_height = skl_max_plane_height(); if (w > max_width || h > max_height) { - DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", - w, h, max_width, max_height); + drm_dbg_kms(&dev_priv->drm, + "requested Y/RGB source size %dx%d too big (limit %dx%d)\n", + w, h, max_width, max_height); return -EINVAL; } intel_add_fb_offsets(&x, &y, plane_state, 0); offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0); alignment = intel_surf_alignment(fb, 0); - if (WARN_ON(alignment && !is_power_of_2(alignment))) + if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))) return -EINVAL; /* @@ -3829,7 +3875,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) while ((x + w) * cpp > plane_state->color_plane[0].stride) { if (offset == 0) { - DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); + drm_dbg_kms(&dev_priv->drm, + "Unable to find suitable display surface offset due to X-tiling\n"); return -EINVAL; } @@ -3854,7 +3901,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) if (x != plane_state->color_plane[aux_plane].x || y != plane_state->color_plane[aux_plane].y) { - DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); + drm_dbg_kms(&dev_priv->drm, + "Unable to find suitable display surface offset due to CCS\n"); return -EINVAL; } } @@ -3875,6 +3923,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) { + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); const struct drm_framebuffer *fb = plane_state->hw.fb; unsigned int rotation = plane_state->hw.rotation; int uv_plane = 1; @@ -3892,8 +3941,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) /* FIXME not quite sure how/if these apply to the chroma plane */ if (w > max_width || h > max_height) { - DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", - w, h, max_width, max_height); + drm_dbg_kms(&i915->drm, + "CbCr source size %dx%d too big (limit %dx%d)\n", + w, h, max_width, max_height); return -EINVAL; } @@ -3922,7 +3972,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) if (x != plane_state->color_plane[ccs_plane].x || y != plane_state->color_plane[ccs_plane].y) { - DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); + drm_dbg_kms(&i915->drm, + "Unable to find suitable display surface offset due to CCS\n"); return -EINVAL; } } @@ -4331,7 +4382,8 @@ static void i9xx_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), + plane_state->color_plane[0].stride); if (INTEL_GEN(dev_priv) < 4) { /* @@ -4339,21 +4391,26 @@ static void i9xx_update_plane(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - I915_WRITE_FW(DSPPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DSPSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); } else if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) { - I915_WRITE_FW(PRIMPOS(i9xx_plane), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PRIMSIZE(i9xx_plane), - ((crtc_h - 1) << 16) | (crtc_w - 1)); - I915_WRITE_FW(PRIMCNSTALPHA(i9xx_plane), 0); + intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + ((crtc_h - 1) << 16) | (crtc_w - 1)); + intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), + (y << 16) | x); } else if (INTEL_GEN(dev_priv) >= 4) { - I915_WRITE_FW(DSPLINOFF(i9xx_plane), linear_offset); - I915_WRITE_FW(DSPTILEOFF(i9xx_plane), (y << 16) | x); + intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), + linear_offset); + intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), + (y << 16) | x); } /* @@ -4361,15 +4418,13 @@ static void i9xx_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - I915_WRITE_FW(DSPADDR(i9xx_plane), - intel_plane_ggtt_offset(plane_state) + - dspaddr_offset); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -4396,11 +4451,11 @@ static void i9xx_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE_FW(DSPSURF(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); else - I915_WRITE_FW(DSPADDR(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -4425,7 +4480,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = I915_READ(DSPCNTR(i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); ret = val & DISPLAY_PLANE_ENABLE; @@ -4444,10 +4499,15 @@ static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) { struct drm_device *dev = intel_crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + + intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id), 0); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); - I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); - I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); - I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } /* @@ -4791,7 +4851,7 @@ __intel_display_resume(struct drm_device *dev, ret = drm_atomic_helper_commit_duplicated_state(state, ctx); - WARN_ON(ret == -EDEADLK); + drm_WARN_ON(dev, ret == -EDEADLK); return ret; } @@ -4819,7 +4879,8 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET); if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)) { - DRM_DEBUG_KMS("Modeset potentially stuck, unbreaking through wedging\n"); + drm_dbg_kms(&dev_priv->drm, + "Modeset potentially stuck, unbreaking through wedging\n"); intel_gt_set_wedged(&dev_priv->gt); } @@ -4843,13 +4904,15 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) state = drm_atomic_helper_duplicate_state(dev, ctx); if (IS_ERR(state)) { ret = PTR_ERR(state); - DRM_ERROR("Duplicating state failed with %i\n", ret); + drm_err(&dev_priv->drm, "Duplicating state failed with %i\n", + ret); return; } ret = drm_atomic_helper_disable_all(dev, ctx); if (ret) { - DRM_ERROR("Suspending crtc's failed with %i\n", ret); + drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", + ret); drm_atomic_state_put(state); return; } @@ -4878,7 +4941,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) /* for testing only restore the display */ ret = __intel_display_resume(dev, state, ctx); if (ret) - DRM_ERROR("Restoring old state failed with %i\n", ret); + drm_err(&dev_priv->drm, + "Restoring old state failed with %i\n", ret); } else { /* * The display has been reset as well, @@ -4895,7 +4959,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) ret = __intel_display_resume(dev, state, ctx); if (ret) - DRM_ERROR("Restoring old state failed with %i\n", ret); + drm_err(&dev_priv->drm, + "Restoring old state failed with %i\n", ret); intel_hpd_init(dev_priv); } @@ -4915,7 +4980,7 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) enum pipe pipe = crtc->pipe; u32 tmp; - tmp = I915_READ(PIPE_CHICKEN(pipe)); + tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); /* * Display WA #1153: icl @@ -4930,7 +4995,7 @@ static void icl_set_pipe_chicken(struct intel_crtc *crtc) * across pipe */ tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU; - I915_WRITE(PIPE_CHICKEN(pipe), tmp); + intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp); } static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state) @@ -4959,8 +5024,9 @@ static void icl_enable_trans_port_sync(const struct intel_crtc_state *crtc_state /* Enable Transcoder Port Sync */ trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE; - I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder), - trans_ddi_func_ctl2_val); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder), + trans_ddi_func_ctl2_val); } static void intel_fdi_normal_train(struct intel_crtc *crtc) @@ -4973,7 +5039,7 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc) /* enable normal train */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (IS_IVYBRIDGE(dev_priv)) { temp &= ~FDI_LINK_TRAIN_NONE_IVB; temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; @@ -4981,10 +5047,10 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc) temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; } - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_NORMAL_CPT; @@ -4992,16 +5058,16 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc) temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_NONE; } - I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); /* wait one idle pattern time */ - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(1000); /* IVB wants error correction enabled */ if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | - FDI_FE_ERRC_ENABLE); + intel_de_write(dev_priv, reg, + intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); } /* The FDI link training functions for ILK/Ibexpeak. */ @@ -5020,81 +5086,83 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - I915_WRITE(reg, temp); - I915_READ(reg); + intel_de_write(dev_priv, reg, temp); + intel_de_read(dev_priv, reg); udelay(150); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; - I915_WRITE(reg, temp | FDI_TX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; - I915_WRITE(reg, temp | FDI_RX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); /* Ironlake workaround, enable clock pointer after FDI enable*/ - I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); - I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | - FDI_RX_PHASE_SYNC_POINTER_EN); + intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + FDI_RX_PHASE_SYNC_POINTER_OVR); + intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { - temp = I915_READ(reg); - DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(dev_priv, reg); + drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if ((temp & FDI_RX_BIT_LOCK)) { - DRM_DEBUG_KMS("FDI train 1 done.\n"); - I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); + drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); + intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); break; } } if (tries == 5) - DRM_ERROR("FDI train 1 fail!\n"); + drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); /* Train 2 */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { - temp = I915_READ(reg); - DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(dev_priv, reg); + drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK) { - I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); - DRM_DEBUG_KMS("FDI train 2 done.\n"); + intel_de_write(dev_priv, reg, + temp | FDI_RX_SYMBOL_LOCK); + drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); break; } } if (tries == 5) - DRM_ERROR("FDI train 2 fail!\n"); + drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); - DRM_DEBUG_KMS("FDI train done\n"); + drm_dbg_kms(&dev_priv->drm, "FDI train done\n"); } @@ -5118,17 +5186,17 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp &= ~FDI_LINK_TRAIN_NONE; @@ -5136,13 +5204,13 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; - I915_WRITE(reg, temp | FDI_TX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); - I915_WRITE(FDI_RX_MISC(pipe), - FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); + intel_de_write(dev_priv, FDI_RX_MISC(pipe), + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; @@ -5150,28 +5218,30 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; } - I915_WRITE(reg, temp | FDI_RX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); for (i = 0; i < 4; i++) { reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[i]; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(500); for (retry = 0; retry < 5; retry++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); - DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(dev_priv, reg); + drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_BIT_LOCK) { - I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); - DRM_DEBUG_KMS("FDI train 1 done.\n"); + intel_de_write(dev_priv, reg, + temp | FDI_RX_BIT_LOCK); + drm_dbg_kms(&dev_priv->drm, + "FDI train 1 done.\n"); break; } udelay(50); @@ -5180,11 +5250,11 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, break; } if (i == 4) - DRM_ERROR("FDI train 1 fail!\n"); + drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); /* Train 2 */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; if (IS_GEN(dev_priv, 6)) { @@ -5192,10 +5262,10 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; } - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; @@ -5203,28 +5273,30 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; } - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); for (i = 0; i < 4; i++) { reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[i]; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(500); for (retry = 0; retry < 5; retry++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); - DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(dev_priv, reg); + drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK) { - I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); - DRM_DEBUG_KMS("FDI train 2 done.\n"); + intel_de_write(dev_priv, reg, + temp | FDI_RX_SYMBOL_LOCK); + drm_dbg_kms(&dev_priv->drm, + "FDI train 2 done.\n"); break; } udelay(50); @@ -5233,9 +5305,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, break; } if (i == 4) - DRM_ERROR("FDI train 2 fail!\n"); + drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); - DRM_DEBUG_KMS("FDI train done.\n"); + drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); } /* Manual link training for Ivy Bridge A0 parts */ @@ -5251,111 +5323,117 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ reg = FDI_RX_IMR(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_RX_SYMBOL_LOCK; temp &= ~FDI_RX_BIT_LOCK; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(150); - DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", - I915_READ(FDI_RX_IIR(pipe))); + drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", + intel_de_read(dev_priv, FDI_RX_IIR(pipe))); /* Try each vswing and preemphasis setting twice before moving on */ for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { /* disable first in case we need to retry */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); temp &= ~FDI_TX_ENABLE; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_AUTO; temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp &= ~FDI_RX_ENABLE; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); /* enable CPU FDI TX and PCH FDI RX */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_DP_PORT_WIDTH_MASK; temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; temp |= snb_b_fdi_train_param[j/2]; temp |= FDI_COMPOSITE_SYNC; - I915_WRITE(reg, temp | FDI_TX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); - I915_WRITE(FDI_RX_MISC(pipe), - FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); + intel_de_write(dev_priv, FDI_RX_MISC(pipe), + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; temp |= FDI_COMPOSITE_SYNC; - I915_WRITE(reg, temp | FDI_RX_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(1); /* should be 0.5us */ for (i = 0; i < 4; i++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); - DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(dev_priv, reg); + drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_BIT_LOCK || - (I915_READ(reg) & FDI_RX_BIT_LOCK)) { - I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); - DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", - i); + (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) { + intel_de_write(dev_priv, reg, + temp | FDI_RX_BIT_LOCK); + drm_dbg_kms(&dev_priv->drm, + "FDI train 1 done, level %i.\n", + i); break; } udelay(1); /* should be 0.5us */ } if (i == 4) { - DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); + drm_dbg_kms(&dev_priv->drm, + "FDI train 1 fail on vswing %d\n", j / 2); continue; } /* Train 2 */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE_IVB; temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(2); /* should be 1.5us */ for (i = 0; i < 4; i++) { reg = FDI_RX_IIR(pipe); - temp = I915_READ(reg); - DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); + temp = intel_de_read(dev_priv, reg); + drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); if (temp & FDI_RX_SYMBOL_LOCK || - (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { - I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); - DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", - i); + (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) { + intel_de_write(dev_priv, reg, + temp | FDI_RX_SYMBOL_LOCK); + drm_dbg_kms(&dev_priv->drm, + "FDI train 2 done, level %i.\n", + i); goto train_done; } udelay(2); /* should be 1.5us */ } if (i == 4) - DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); + drm_dbg_kms(&dev_priv->drm, + "FDI train 2 fail on vswing %d\n", j / 2); } train_done: - DRM_DEBUG_KMS("FDI train done.\n"); + drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); } static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) @@ -5368,29 +5446,29 @@ static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); - temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; - I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); + temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; + intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(200); /* Switch from Rawclk to PCDclk */ - temp = I915_READ(reg); - I915_WRITE(reg, temp | FDI_PCDCLK); + temp = intel_de_read(dev_priv, reg); + intel_de_write(dev_priv, reg, temp | FDI_PCDCLK); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(200); /* Enable CPU FDI TX PLL, always on for Ironlake */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if ((temp & FDI_TX_PLL_ENABLE) == 0) { - I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); + intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(100); } } @@ -5405,23 +5483,23 @@ static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc) /* Switch from PCDclk to Rawclk */ reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); - I915_WRITE(reg, temp & ~FDI_PCDCLK); + temp = intel_de_read(dev_priv, reg); + intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK); /* Disable CPU FDI TX PLL */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); - I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); + temp = intel_de_read(dev_priv, reg); + intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(100); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); - I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); + temp = intel_de_read(dev_priv, reg); + intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE); /* Wait for the clocks to turn off. */ - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(100); } @@ -5434,32 +5512,33 @@ static void ilk_fdi_disable(struct intel_crtc *crtc) /* disable CPU FDI tx and PCH FDI rx */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); - I915_WRITE(reg, temp & ~FDI_TX_ENABLE); - POSTING_READ(reg); + temp = intel_de_read(dev_priv, reg); + intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE); + intel_de_posting_read(dev_priv, reg); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~(0x7 << 16); - temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; - I915_WRITE(reg, temp & ~FDI_RX_ENABLE); + temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; + intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(100); /* Ironlake workaround, disable clock pointer after downing FDI */ if (HAS_PCH_IBX(dev_priv)) - I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); + intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), + FDI_RX_PHASE_SYNC_POINTER_OVR); /* still set train pattern 1 */ reg = FDI_TX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_1; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); reg = FDI_RX_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); if (HAS_PCH_CPT(dev_priv)) { temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; @@ -5469,10 +5548,10 @@ static void ilk_fdi_disable(struct intel_crtc *crtc) } /* BPC in FDI rx is consistent with that in PIPECONF */ temp &= ~(0x07 << 16); - temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; - I915_WRITE(reg, temp); + temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; + intel_de_write(dev_priv, reg, temp); - POSTING_READ(reg); + intel_de_posting_read(dev_priv, reg); udelay(100); } @@ -5505,7 +5584,7 @@ void lpt_disable_iclkip(struct drm_i915_private *dev_priv) { u32 temp; - I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); + intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_GATE); mutex_lock(&dev_priv->sb_lock); @@ -5552,17 +5631,14 @@ static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) } /* This should not happen with any sane values */ - WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & - ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); - WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & - ~SBI_SSCDIVINTPHASE_INCVAL_MASK); - - DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", - clock, - auxdiv, - divsel, - phasedir, - phaseinc); + drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) & + ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); + drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) & + ~SBI_SSCDIVINTPHASE_INCVAL_MASK); + + drm_dbg_kms(&dev_priv->drm, + "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", + clock, auxdiv, divsel, phasedir, phaseinc); mutex_lock(&dev_priv->sb_lock); @@ -5592,7 +5668,7 @@ static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) /* Wait for initialization time */ udelay(24); - I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); + intel_de_write(dev_priv, PIXCLK_GATE, PIXCLK_GATE_UNGATE); } int lpt_get_iclkip(struct drm_i915_private *dev_priv) @@ -5603,7 +5679,7 @@ int lpt_get_iclkip(struct drm_i915_private *dev_priv) u32 desired_divisor; u32 temp; - if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) + if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) return 0; mutex_lock(&dev_priv->sb_lock); @@ -5639,41 +5715,46 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), - I915_READ(HTOTAL(cpu_transcoder))); - I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), - I915_READ(HBLANK(cpu_transcoder))); - I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), - I915_READ(HSYNC(cpu_transcoder))); + intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), + intel_de_read(dev_priv, HTOTAL(cpu_transcoder))); + intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), + intel_de_read(dev_priv, HBLANK(cpu_transcoder))); + intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), + intel_de_read(dev_priv, HSYNC(cpu_transcoder))); - I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), - I915_READ(VTOTAL(cpu_transcoder))); - I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), - I915_READ(VBLANK(cpu_transcoder))); - I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), - I915_READ(VSYNC(cpu_transcoder))); - I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), - I915_READ(VSYNCSHIFT(cpu_transcoder))); + intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), + intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); + intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), + intel_de_read(dev_priv, VBLANK(cpu_transcoder))); + intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), + intel_de_read(dev_priv, VSYNC(cpu_transcoder))); + intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), + intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder))); } static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) { u32 temp; - temp = I915_READ(SOUTH_CHICKEN1); + temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) return; - WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); - WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & + FDI_RX_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & + FDI_RX_ENABLE); temp &= ~FDI_BC_BIFURCATION_SELECT; if (enable) temp |= FDI_BC_BIFURCATION_SELECT; - DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); - I915_WRITE(SOUTH_CHICKEN1, temp); - POSTING_READ(SOUTH_CHICKEN1); + drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n", + enable ? "en" : "dis"); + intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); + intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); } static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) @@ -5723,8 +5804,9 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state, num_encoders++; } - WARN(num_encoders != 1, "%d encoders for pipe %c\n", - num_encoders, pipe_name(crtc->pipe)); + drm_WARN(encoder->base.dev, num_encoders != 1, + "%d encoders for pipe %c\n", + num_encoders, pipe_name(crtc->pipe)); return encoder; } @@ -5753,8 +5835,8 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, /* Write the TU size bits before fdi link training, so that error * detection works. */ - I915_WRITE(FDI_RX_TUSIZE1(pipe), - I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); + intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), + intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); /* For PCH output, training FDI link */ dev_priv->display.fdi_link_train(crtc, crtc_state); @@ -5764,7 +5846,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, if (HAS_PCH_CPT(dev_priv)) { u32 sel; - temp = I915_READ(PCH_DPLL_SEL); + temp = intel_de_read(dev_priv, PCH_DPLL_SEL); temp |= TRANS_DPLL_ENABLE(pipe); sel = TRANS_DPLLB_SEL(pipe); if (crtc_state->shared_dpll == @@ -5772,7 +5854,7 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, temp |= sel; else temp &= ~sel; - I915_WRITE(PCH_DPLL_SEL, temp); + intel_de_write(dev_priv, PCH_DPLL_SEL, temp); } /* XXX: pch pll's can be enabled any time before we enable the PCH @@ -5795,11 +5877,11 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, intel_crtc_has_dp_encoder(crtc_state)) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; + u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; i915_reg_t reg = TRANS_DP_CTL(pipe); enum port port; - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~(TRANS_DP_PORT_SEL_MASK | TRANS_DP_SYNC_MASK | TRANS_DP_BPC_MASK); @@ -5812,17 +5894,16 @@ static void ilk_pch_enable(const struct intel_atomic_state *state, temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; port = intel_get_crtc_new_encoder(state, crtc_state)->port; - WARN_ON(port < PORT_B || port > PORT_D); + drm_WARN_ON(dev, port < PORT_B || port > PORT_D); temp |= TRANS_DP_PORT_SEL(port); - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); } ilk_enable_pch_transcoder(crtc_state); } -static void lpt_pch_enable(const struct intel_atomic_state *state, - const struct intel_crtc_state *crtc_state) +void lpt_pch_enable(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -5844,11 +5925,13 @@ static void cpt_verify_modeset(struct drm_i915_private *dev_priv, i915_reg_t dslreg = PIPEDSL(pipe); u32 temp; - temp = I915_READ(dslreg); + temp = intel_de_read(dev_priv, dslreg); udelay(500); - if (wait_for(I915_READ(dslreg) != temp, 5)) { - if (wait_for(I915_READ(dslreg) != temp, 5)) - DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); + if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) { + if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)) + drm_err(&dev_priv->drm, + "mode set failed: pipe %c stuck\n", + pipe_name(pipe)); } } @@ -5963,7 +6046,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, */ if (INTEL_GEN(dev_priv) >= 9 && crtc_state->hw.enable && need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { - DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); + drm_dbg_kms(&dev_priv->drm, + "Pipe/Plane scaling not supported with IF-ID mode\n"); return -EINVAL; } @@ -5982,10 +6066,11 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, scaler_state->scaler_users &= ~(1 << scaler_user); scaler_state->scalers[*scaler_id].in_use = 0; - DRM_DEBUG_KMS("scaler_user index %u.%u: " - "Staged freeing scaler id %d scaler_users = 0x%x\n", - intel_crtc->pipe, scaler_user, *scaler_id, - scaler_state->scaler_users); + drm_dbg_kms(&dev_priv->drm, + "scaler_user index %u.%u: " + "Staged freeing scaler id %d scaler_users = 0x%x\n", + intel_crtc->pipe, scaler_user, *scaler_id, + scaler_state->scaler_users); *scaler_id = -1; } return 0; @@ -5993,7 +6078,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && (src_h < SKL_MIN_YUV_420_SRC_H || src_w < SKL_MIN_YUV_420_SRC_W)) { - DRM_DEBUG_KMS("Planar YUV: src dimensions not met\n"); + drm_dbg_kms(&dev_priv->drm, + "Planar YUV: src dimensions not met\n"); return -EINVAL; } @@ -6006,18 +6092,20 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, (INTEL_GEN(dev_priv) < 11 && (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { - DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " - "size is out of scaler range\n", - intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); + drm_dbg_kms(&dev_priv->drm, + "scaler_user index %u.%u: src %ux%u dst %ux%u " + "size is out of scaler range\n", + intel_crtc->pipe, scaler_user, src_w, src_h, + dst_w, dst_h); return -EINVAL; } /* mark this plane as a scaler user in crtc_state */ scaler_state->scaler_users |= (1 << scaler_user); - DRM_DEBUG_KMS("scaler_user index %u.%u: " - "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", - intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, - scaler_state->scaler_users); + drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: " + "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", + intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, + scaler_state->scaler_users); return 0; } @@ -6036,7 +6124,8 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state) const struct drm_display_mode *adjusted_mode = &state->hw.adjusted_mode; bool need_scaler = false; - if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + if (state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + state->pch_pfit.enabled) need_scaler = true; return skl_update_scaler(state, !state->hw.active, SKL_CRTC_INDEX, @@ -6088,9 +6177,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, /* check colorkey */ if (plane_state->ckey.flags) { - DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", - intel_plane->base.base.id, - intel_plane->base.name); + drm_dbg_kms(&dev_priv->drm, + "[PLANE:%d:%s] scaling with color key not allowed", + intel_plane->base.base.id, + intel_plane->base.name); return -EINVAL; } @@ -6128,9 +6218,10 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, break; /* fall through */ default: - DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", - intel_plane->base.base.id, intel_plane->base.name, - fb->base.id, fb->format->format); + drm_dbg_kms(&dev_priv->drm, + "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", + intel_plane->base.base.id, intel_plane->base.name, + fb->base.id, fb->format->format); return -EINVAL; } @@ -6157,9 +6248,11 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) if (crtc_state->pch_pfit.enabled) { u16 uv_rgb_hphase, uv_rgb_vphase; int pfit_w, pfit_h, hscale, vscale; + unsigned long irqflags; int id; - if (WARN_ON(crtc_state->scaler_state.scaler_id < 0)) + if (drm_WARN_ON(&dev_priv->drm, + crtc_state->scaler_state.scaler_id < 0)) return; pfit_w = (crtc_state->pch_pfit.size >> 16) & 0xFFFF; @@ -6172,14 +6265,21 @@ static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); id = scaler_state->scaler_id; - I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | - PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, id), - PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc_state->pch_pfit.pos); - I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc_state->pch_pfit.size); + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id), PS_SCALER_EN | + PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id), + PS_Y_PHASE(0) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id), + crtc_state->pch_pfit.pos); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id), + crtc_state->pch_pfit.size); + + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } } @@ -6195,12 +6295,15 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) * e.g. x201. */ if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) - I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | - PF_PIPE_SEL_IVB(pipe)); + intel_de_write(dev_priv, PF_CTL(pipe), + PF_ENABLE | PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe)); else - I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); - I915_WRITE(PF_WIN_POS(pipe), crtc_state->pch_pfit.pos); - I915_WRITE(PF_WIN_SZ(pipe), crtc_state->pch_pfit.size); + intel_de_write(dev_priv, PF_CTL(pipe), + PF_ENABLE | PF_FILTER_MED_3x3); + intel_de_write(dev_priv, PF_WIN_POS(pipe), + crtc_state->pch_pfit.pos); + intel_de_write(dev_priv, PF_WIN_SZ(pipe), + crtc_state->pch_pfit.size); } } @@ -6218,25 +6321,26 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state) * This function is called from post_plane_update, which is run after * a vblank wait. */ - WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); + drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR))); if (IS_BROADWELL(dev_priv)) { - WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, - IPS_ENABLE | IPS_PCODE_CONTROL)); + drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, + IPS_ENABLE | IPS_PCODE_CONTROL)); /* Quoting Art Runyan: "its not safe to expect any particular * value in IPS_CTL bit 31 after enabling IPS through the * mailbox." Moreover, the mailbox may return a bogus state, * so we need to just enable it and continue on. */ } else { - I915_WRITE(IPS_CTL, IPS_ENABLE); + intel_de_write(dev_priv, IPS_CTL, IPS_ENABLE); /* The bit only becomes 1 in the next vblank, so this wait here * is essentially intel_wait_for_vblank. If we don't have this * and don't wait for vblanks until the end of crtc_enable, then * the HW state readout code will complain that the expected * IPS_CTL value is not the one we read. */ if (intel_de_wait_for_set(dev_priv, IPS_CTL, IPS_ENABLE, 50)) - DRM_ERROR("Timed out waiting for IPS enable\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for IPS enable\n"); } } @@ -6250,17 +6354,19 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state) return; if (IS_BROADWELL(dev_priv)) { - WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); + drm_WARN_ON(dev, + sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); /* * Wait for PCODE to finish disabling IPS. The BSpec specified * 42ms timeout value leads to occasional timeouts so use 100ms * instead. */ if (intel_de_wait_for_clear(dev_priv, IPS_CTL, IPS_ENABLE, 100)) - DRM_ERROR("Timed out waiting for IPS disable\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for IPS disable\n"); } else { - I915_WRITE(IPS_CTL, 0); - POSTING_READ(IPS_CTL); + intel_de_write(dev_priv, IPS_CTL, 0); + intel_de_posting_read(dev_priv, IPS_CTL); } /* We need to wait for a vblank before we can disable the plane. */ @@ -6382,13 +6488,10 @@ static void intel_post_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_plane *primary = to_intel_plane(crtc->base.primary); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - const struct intel_plane_state *new_primary_state = - intel_atomic_get_new_plane_state(state, primary); enum pipe pipe = crtc->pipe; intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); @@ -6399,8 +6502,7 @@ static void intel_post_plane_update(struct intel_atomic_state *state, if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state)) hsw_enable_ips(new_crtc_state); - if (new_primary_state) - intel_fbc_post_update(crtc); + intel_fbc_post_update(state, crtc); if (needs_nv12_wa(old_crtc_state) && !needs_nv12_wa(new_crtc_state)) @@ -6415,20 +6517,16 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_plane *primary = to_intel_plane(crtc->base.primary); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - const struct intel_plane_state *new_primary_state = - intel_atomic_get_new_plane_state(state, primary); enum pipe pipe = crtc->pipe; if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state)) hsw_disable_ips(old_crtc_state); - if (new_primary_state && - intel_fbc_pre_update(crtc, new_crtc_state, new_primary_state)) + if (intel_fbc_pre_update(state, crtc)) intel_wait_for_vblank(dev_priv, pipe); /* Display WA 827 */ @@ -6770,7 +6868,7 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; /* @@ -6863,7 +6961,7 @@ static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, enum pipe pipe, bool apply) { - u32 val = I915_READ(CLKGATE_DIS_PSL(pipe)); + u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS; if (apply) @@ -6871,7 +6969,7 @@ static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv, else val &= ~mask; - I915_WRITE(CLKGATE_DIS_PSL(pipe), val); + intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val); } static void icl_pipe_mbus_enable(struct intel_crtc *crtc) @@ -6890,7 +6988,17 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc) val |= MBUS_DBOX_B_CREDIT(8); } - I915_WRITE(PIPE_MBUS_DBOX_CTL(pipe), val); + intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe), val); +} + +static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + + intel_de_write(dev_priv, WM_LINETIME(crtc->pipe), + HSW_LINETIME(crtc_state->linetime) | + HSW_IPS_LINETIME(crtc_state->ips_linetime)); } static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) @@ -6900,10 +7008,10 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); u32 val; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~HSW_FRAME_START_DELAY_MASK; val |= HSW_FRAME_START_DELAY(0); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } static void hsw_crtc_enable(struct intel_atomic_state *state, @@ -6916,7 +7024,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; bool psl_clkgate_wa; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; intel_encoders_pre_pll_enable(state, crtc); @@ -6926,9 +7034,6 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, intel_encoders_pre_enable(state, crtc); - if (intel_crtc_has_dp_encoder(new_crtc_state)) - intel_dp_set_m_n(new_crtc_state, M1_N1); - if (!transcoder_is_dsi(cpu_transcoder)) intel_set_pipe_timings(new_crtc_state); @@ -6939,8 +7044,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (cpu_transcoder != TRANSCODER_EDP && !transcoder_is_dsi(cpu_transcoder)) - I915_WRITE(PIPE_MULT(cpu_transcoder), - new_crtc_state->pixel_multiplier - 1); + intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder), + new_crtc_state->pixel_multiplier - 1); if (new_crtc_state->has_pch_encoder) intel_cpu_transcoder_set_m_n(new_crtc_state, @@ -6977,6 +7082,8 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (INTEL_GEN(dev_priv) < 9) intel_disable_primary_plane(new_crtc_state); + hsw_set_linetime_wm(new_crtc_state); + if (INTEL_GEN(dev_priv) >= 11) icl_set_pipe_chicken(crtc); @@ -6989,15 +7096,6 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, if (INTEL_GEN(dev_priv) >= 11) icl_pipe_mbus_enable(crtc); - /* XXX: Do the pipe assertions at the right place for BXT DSI. */ - if (!transcoder_is_dsi(cpu_transcoder)) - intel_enable_pipe(new_crtc_state); - - if (new_crtc_state->has_pch_encoder) - lpt_pch_enable(state, new_crtc_state); - - intel_crtc_vblank_on(new_crtc_state); - intel_encoders_enable(state, crtc); if (psl_clkgate_wa) { @@ -7023,9 +7121,9 @@ void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) /* To avoid upsetting the power well on haswell only disable the pfit if * it's in use. The hw state code will make sure we get this right. */ if (old_crtc_state->pch_pfit.enabled) { - I915_WRITE(PF_CTL(pipe), 0); - I915_WRITE(PF_WIN_POS(pipe), 0); - I915_WRITE(PF_WIN_SZ(pipe), 0); + intel_de_write(dev_priv, PF_CTL(pipe), 0); + intel_de_write(dev_priv, PF_WIN_POS(pipe), 0); + intel_de_write(dev_priv, PF_WIN_SZ(pipe), 0); } } @@ -7067,16 +7165,16 @@ static void ilk_crtc_disable(struct intel_atomic_state *state, /* disable TRANS_DP_CTL */ reg = TRANS_DP_CTL(pipe); - temp = I915_READ(reg); + temp = intel_de_read(dev_priv, reg); temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); temp |= TRANS_DP_PORT_SEL_NONE; - I915_WRITE(reg, temp); + intel_de_write(dev_priv, reg, temp); /* disable DPLL_SEL */ - temp = I915_READ(PCH_DPLL_SEL); + temp = intel_de_read(dev_priv, PCH_DPLL_SEL); temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); - I915_WRITE(PCH_DPLL_SEL, temp); + intel_de_write(dev_priv, PCH_DPLL_SEL, temp); } ilk_fdi_pll_disable(crtc); @@ -7109,15 +7207,17 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) * The panel fitter should only be adjusted whilst the pipe is disabled, * according to register description and PRM. */ - WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); - I915_WRITE(PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios); - I915_WRITE(PFIT_CONTROL, crtc_state->gmch_pfit.control); + intel_de_write(dev_priv, PFIT_PGM_RATIOS, + crtc_state->gmch_pfit.pgm_ratios); + intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); /* Border color in case we don't scale up to the full screen. Black by * default, change to something else for debugging. */ - I915_WRITE(BCLRPAT(crtc->pipe), 0); + intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); } bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) @@ -7304,7 +7404,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; if (intel_crtc_has_dp_encoder(new_crtc_state)) @@ -7314,8 +7414,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, intel_set_pipe_src_size(new_crtc_state); if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { - I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); - I915_WRITE(CHV_CANVAS(pipe), 0); + intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); + intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); } i9xx_set_pipeconf(new_crtc_state); @@ -7356,8 +7456,10 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - I915_WRITE(FP0(crtc->pipe), crtc_state->dpll_hw_state.fp0); - I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1); + intel_de_write(dev_priv, FP0(crtc->pipe), + crtc_state->dpll_hw_state.fp0); + intel_de_write(dev_priv, FP1(crtc->pipe), + crtc_state->dpll_hw_state.fp1); } static void i9xx_crtc_enable(struct intel_atomic_state *state, @@ -7368,7 +7470,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (WARN_ON(crtc->active)) + if (drm_WARN_ON(&dev_priv->drm, crtc->active)) return; i9xx_set_pll_dividers(new_crtc_state); @@ -7418,9 +7520,9 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder); - DRM_DEBUG_KMS("disabling pfit, current: 0x%08x\n", - I915_READ(PFIT_CONTROL)); - I915_WRITE(PFIT_CONTROL, 0); + drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", + intel_de_read(dev_priv, PFIT_CONTROL)); + intel_de_write(dev_priv, PFIT_CONTROL, 0); } static void i9xx_crtc_disable(struct intel_atomic_state *state, @@ -7477,6 +7579,8 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_bw_state *bw_state = to_intel_bw_state(dev_priv->bw_obj.state); + struct intel_cdclk_state *cdclk_state = + to_intel_cdclk_state(dev_priv->cdclk.obj.state); struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); enum intel_display_power_domain domain; @@ -7500,8 +7604,9 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, state = drm_atomic_state_alloc(&dev_priv->drm); if (!state) { - DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", - crtc->base.base.id, crtc->base.name); + drm_dbg_kms(&dev_priv->drm, + "failed to disable [CRTC:%d:%s], out of memory", + crtc->base.base.id, crtc->base.name); return; } @@ -7511,19 +7616,21 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); ret = drm_atomic_add_affected_connectors(state, &crtc->base); - WARN_ON(IS_ERR(temp_crtc_state) || ret); + drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret); dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc); drm_atomic_state_put(state); - DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", - crtc->base.base.id, crtc->base.name); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", + crtc->base.base.id, crtc->base.name); crtc->active = false; crtc->base.enabled = false; - WARN_ON(drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); + drm_WARN_ON(&dev_priv->drm, + drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0); crtc_state->uapi.active = false; crtc_state->uapi.connector_mask = 0; crtc_state->uapi.encoder_mask = 0; @@ -7543,8 +7650,9 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, crtc->enabled_power_domains = 0; dev_priv->active_pipes &= ~BIT(pipe); - dev_priv->min_cdclk[pipe] = 0; - dev_priv->min_voltage_level[pipe] = 0; + cdclk_state->min_cdclk[pipe] = 0; + cdclk_state->min_voltage_level[pipe] = 0; + cdclk_state->active_pipes &= ~BIT(pipe); bw_state->data_rate[pipe] = 0; bw_state->num_active_planes[pipe] = 0; @@ -7563,7 +7671,8 @@ int intel_display_suspend(struct drm_device *dev) state = drm_atomic_helper_suspend(dev); ret = PTR_ERR_OR_ZERO(state); if (ret) - DRM_ERROR("Suspending crtc's failed with %i\n", ret); + drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n", + ret); else dev_priv->modeset_restore_state = state; return ret; @@ -7583,13 +7692,13 @@ static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) { struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", - connector->base.base.id, - connector->base.name); + drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", + connector->base.base.id, connector->base.name); if (connector->get_hw_state(connector)) { - struct intel_encoder *encoder = connector->encoder; + struct intel_encoder *encoder = intel_attached_encoder(connector); I915_STATE_WARN(!crtc_state, "connector enabled without attached crtc\n"); @@ -7632,18 +7741,21 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, struct intel_crtc *other_crtc; struct intel_crtc_state *other_crtc_state; - DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", - pipe_name(pipe), pipe_config->fdi_lanes); + drm_dbg_kms(&dev_priv->drm, + "checking fdi config on pipe %c, lanes %i\n", + pipe_name(pipe), pipe_config->fdi_lanes); if (pipe_config->fdi_lanes > 4) { - DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", - pipe_name(pipe), pipe_config->fdi_lanes); + drm_dbg_kms(&dev_priv->drm, + "invalid fdi lane config on pipe %c: %i lanes\n", + pipe_name(pipe), pipe_config->fdi_lanes); return -EINVAL; } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { if (pipe_config->fdi_lanes > 2) { - DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", - pipe_config->fdi_lanes); + drm_dbg_kms(&dev_priv->drm, + "only 2 lanes on haswell, required: %i lanes\n", + pipe_config->fdi_lanes); return -EINVAL; } else { return 0; @@ -7668,15 +7780,17 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, return PTR_ERR(other_crtc_state); if (pipe_required_fdi_lanes(other_crtc_state) > 0) { - DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", - pipe_name(pipe), pipe_config->fdi_lanes); + drm_dbg_kms(&dev_priv->drm, + "invalid shared fdi lane config on pipe %c: %i lanes\n", + pipe_name(pipe), pipe_config->fdi_lanes); return -EINVAL; } return 0; case PIPE_C: if (pipe_config->fdi_lanes > 2) { - DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", - pipe_name(pipe), pipe_config->fdi_lanes); + drm_dbg_kms(&dev_priv->drm, + "only 2 lanes on pipe %c: required %i lanes\n", + pipe_name(pipe), pipe_config->fdi_lanes); return -EINVAL; } @@ -7687,7 +7801,8 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, return PTR_ERR(other_crtc_state); if (pipe_required_fdi_lanes(other_crtc_state) > 2) { - DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); + drm_dbg_kms(&dev_priv->drm, + "fdi link B uses too many lanes to enable link C\n"); return -EINVAL; } return 0; @@ -7701,6 +7816,7 @@ static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc, struct intel_crtc_state *pipe_config) { struct drm_device *dev = intel_crtc->base.dev; + struct drm_i915_private *i915 = to_i915(dev); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int lane, link_bw, fdi_dotclock, ret; bool needs_recompute = false; @@ -7713,7 +7829,7 @@ retry: * Hence the bw of each lane in terms of the mode signal * is: */ - link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); + link_bw = intel_fdi_link_freq(i915, pipe_config); fdi_dotclock = adjusted_mode->crtc_clock; @@ -7731,8 +7847,9 @@ retry: if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { pipe_config->pipe_bpp -= 2*3; - DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", - pipe_config->pipe_bpp); + drm_dbg_kms(&i915->drm, + "fdi link bw constraint, reducing pipe bpp to %i\n", + pipe_config->pipe_bpp); needs_recompute = true; pipe_config->bw_constrained = true; @@ -7774,15 +7891,17 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) return true; } -static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state) +static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - struct intel_atomic_state *intel_state = + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); + crtc_state->ips_enabled = false; + if (!hsw_crtc_state_ips_capable(crtc_state)) - return false; + return 0; /* * When IPS gets enabled, the pipe CRC changes. Since IPS gets @@ -7791,18 +7910,27 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state) * completely disable it. */ if (crtc_state->crc_enabled) - return false; + return 0; /* IPS should be fine as long as at least one plane is enabled. */ if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR))) - return false; + return 0; - /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ - if (IS_BROADWELL(dev_priv) && - crtc_state->pixel_rate > intel_state->cdclk.logical.cdclk * 95 / 100) - return false; + if (IS_BROADWELL(dev_priv)) { + const struct intel_cdclk_state *cdclk_state; - return true; + cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(cdclk_state)) + return PTR_ERR(cdclk_state); + + /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ + if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) + return 0; + } + + crtc_state->ips_enabled = true; + + return 0; } static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) @@ -7884,9 +8012,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, } if (adjusted_mode->crtc_clock > clock_limit) { - DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", - adjusted_mode->crtc_clock, clock_limit, - yesno(pipe_config->double_wide)); + drm_dbg_kms(&dev_priv->drm, + "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", + adjusted_mode->crtc_clock, clock_limit, + yesno(pipe_config->double_wide)); return -EINVAL; } @@ -7898,7 +8027,8 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, * for output conversion from RGB->YCBCR. So if CTM is already * applied we can't support YCBCR420 output. */ - DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); + drm_dbg_kms(&dev_priv->drm, + "YCBCR420 and CTM together are not possible\n"); return -EINVAL; } @@ -7910,13 +8040,15 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, */ if (pipe_config->pipe_src_w & 1) { if (pipe_config->double_wide) { - DRM_DEBUG_KMS("Odd pipe source width not supported with double wide pipe\n"); + drm_dbg_kms(&dev_priv->drm, + "Odd pipe source width not supported with double wide pipe\n"); return -EINVAL; } if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && intel_is_dual_link_lvds(dev_priv)) { - DRM_DEBUG_KMS("Odd pipe source width not supported with dual link LVDS\n"); + drm_dbg_kms(&dev_priv->drm, + "Odd pipe source width not supported with dual link LVDS\n"); return -EINVAL; } } @@ -7997,13 +8129,15 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv) * indicates as much. */ if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { - bool bios_lvds_use_ssc = I915_READ(PCH_DREF_CONTROL) & + bool bios_lvds_use_ssc = intel_de_read(dev_priv, + PCH_DREF_CONTROL) & DREF_SSC1_ENABLE; if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { - DRM_DEBUG_KMS("SSC %s by BIOS, overriding VBT which says %s\n", - enableddisabled(bios_lvds_use_ssc), - enableddisabled(dev_priv->vbt.lvds_use_ssc)); + drm_dbg_kms(&dev_priv->drm, + "SSC %s by BIOS, overriding VBT which says %s\n", + enableddisabled(bios_lvds_use_ssc), + enableddisabled(dev_priv->vbt.lvds_use_ssc)); dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; } } @@ -8090,10 +8224,11 @@ static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); - I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); - I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); + intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe), + TU_SIZE(m_n->tu) | m_n->gmch_m); + intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); + intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe), m_n->link_m); + intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe), m_n->link_n); } static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, @@ -8119,33 +8254,42 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta enum transcoder transcoder = crtc_state->cpu_transcoder; if (INTEL_GEN(dev_priv) >= 5) { - I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); - I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); - I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); + intel_de_write(dev_priv, PIPE_DATA_M1(transcoder), + TU_SIZE(m_n->tu) | m_n->gmch_m); + intel_de_write(dev_priv, PIPE_DATA_N1(transcoder), + m_n->gmch_n); + intel_de_write(dev_priv, PIPE_LINK_M1(transcoder), + m_n->link_m); + intel_de_write(dev_priv, PIPE_LINK_N1(transcoder), + m_n->link_n); /* * M2_N2 registers are set only if DRRS is supported * (to make sure the registers are not unnecessarily accessed). */ if (m2_n2 && crtc_state->has_drrs && transcoder_has_m2_n2(dev_priv, transcoder)) { - I915_WRITE(PIPE_DATA_M2(transcoder), - TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); - I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); - I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); - I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); + intel_de_write(dev_priv, PIPE_DATA_M2(transcoder), + TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); + intel_de_write(dev_priv, PIPE_DATA_N2(transcoder), + m2_n2->gmch_n); + intel_de_write(dev_priv, PIPE_LINK_M2(transcoder), + m2_n2->link_m); + intel_de_write(dev_priv, PIPE_LINK_N2(transcoder), + m2_n2->link_n); } } else { - I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); - I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); - I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); - I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); + intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe), + TU_SIZE(m_n->tu) | m_n->gmch_m); + intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe), m_n->gmch_n); + intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe), m_n->link_m); + intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe), m_n->link_n); } } void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n) { const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); if (m_n == M1_N1) { dp_m_n = &crtc_state->dp_m_n; @@ -8158,7 +8302,7 @@ void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_s */ dp_m_n = &crtc_state->dp_m2_n2; } else { - DRM_ERROR("Unsupported divider value\n"); + drm_err(&i915->drm, "Unsupported divider value\n"); return; } @@ -8212,9 +8356,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc, u32 coreclk, reg_val; /* Enable Refclk */ - I915_WRITE(DPLL(pipe), - pipe_config->dpll_hw_state.dpll & - ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); + intel_de_write(dev_priv, DPLL(pipe), + pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); /* No need to actually set up the DPLL with DSI */ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) @@ -8314,8 +8457,8 @@ static void chv_prepare_pll(struct intel_crtc *crtc, int vco; /* Enable Refclk and SSC */ - I915_WRITE(DPLL(pipe), - pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); + intel_de_write(dev_priv, DPLL(pipe), + pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); /* No need to actually set up the DPLL with DSI */ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) @@ -8614,27 +8757,22 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) } if (INTEL_GEN(dev_priv) > 3) - I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); - - I915_WRITE(HTOTAL(cpu_transcoder), - (adjusted_mode->crtc_hdisplay - 1) | - ((adjusted_mode->crtc_htotal - 1) << 16)); - I915_WRITE(HBLANK(cpu_transcoder), - (adjusted_mode->crtc_hblank_start - 1) | - ((adjusted_mode->crtc_hblank_end - 1) << 16)); - I915_WRITE(HSYNC(cpu_transcoder), - (adjusted_mode->crtc_hsync_start - 1) | - ((adjusted_mode->crtc_hsync_end - 1) << 16)); - - I915_WRITE(VTOTAL(cpu_transcoder), - (adjusted_mode->crtc_vdisplay - 1) | - ((crtc_vtotal - 1) << 16)); - I915_WRITE(VBLANK(cpu_transcoder), - (adjusted_mode->crtc_vblank_start - 1) | - ((crtc_vblank_end - 1) << 16)); - I915_WRITE(VSYNC(cpu_transcoder), - (adjusted_mode->crtc_vsync_start - 1) | - ((adjusted_mode->crtc_vsync_end - 1) << 16)); + intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder), + vsyncshift); + + intel_de_write(dev_priv, HTOTAL(cpu_transcoder), + (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); + intel_de_write(dev_priv, HBLANK(cpu_transcoder), + (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); + intel_de_write(dev_priv, HSYNC(cpu_transcoder), + (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); + + intel_de_write(dev_priv, VTOTAL(cpu_transcoder), + (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); + intel_de_write(dev_priv, VBLANK(cpu_transcoder), + (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); + intel_de_write(dev_priv, VSYNC(cpu_transcoder), + (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); /* Workaround: when the EDP input selection is B, the VTOTAL_B must be * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is @@ -8642,7 +8780,8 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) * bits. */ if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && (pipe == PIPE_B || pipe == PIPE_C)) - I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); + intel_de_write(dev_priv, VTOTAL(pipe), + intel_de_read(dev_priv, VTOTAL(cpu_transcoder))); } @@ -8655,9 +8794,8 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. */ - I915_WRITE(PIPESRC(pipe), - ((crtc_state->pipe_src_w - 1) << 16) | - (crtc_state->pipe_src_h - 1)); + intel_de_write(dev_priv, PIPESRC(pipe), + ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1)); } static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) @@ -8670,9 +8808,9 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) - return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; + return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW; else - return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; + return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK; } static void intel_get_pipe_timings(struct intel_crtc *crtc, @@ -8683,33 +8821,33 @@ static void intel_get_pipe_timings(struct intel_crtc *crtc, enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; u32 tmp; - tmp = I915_READ(HTOTAL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)); pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; if (!transcoder_is_dsi(cpu_transcoder)) { - tmp = I915_READ(HBLANK(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)); pipe_config->hw.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; pipe_config->hw.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; } - tmp = I915_READ(HSYNC(cpu_transcoder)); + tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)); pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; - tmp = I915_READ(VTOTAL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)); pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; if (!transcoder_is_dsi(cpu_transcoder)) { - tmp = I915_READ(VBLANK(cpu_transcoder)); + tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)); pipe_config->hw.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; pipe_config->hw.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; } - tmp = I915_READ(VSYNC(cpu_transcoder)); + tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)); pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; @@ -8727,7 +8865,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); u32 tmp; - tmp = I915_READ(PIPESRC(crtc->pipe)); + tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); pipe_config->pipe_src_h = (tmp & 0xffff) + 1; pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; @@ -8768,7 +8906,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) /* we keep both pipes enabled on 830 */ if (IS_I830(dev_priv)) - pipeconf |= I915_READ(PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; + pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)) & PIPECONF_ENABLE; if (crtc_state->double_wide) pipeconf |= PIPECONF_DOUBLE_WIDE; @@ -8815,8 +8953,8 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) pipeconf |= PIPECONF_FRAME_START_DELAY(0); - I915_WRITE(PIPECONF(crtc->pipe), pipeconf); - POSTING_READ(PIPECONF(crtc->pipe)); + intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf); + intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)); } static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, @@ -8833,7 +8971,9 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(dev_priv)) { refclk = dev_priv->vbt.lvds_ssc_freq; - DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); + drm_dbg_kms(&dev_priv->drm, + "using SSC reference clock of %d kHz\n", + refclk); } limit = &intel_limits_i8xx_lvds; @@ -8846,7 +8986,8 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, if (!crtc_state->clock_set && !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, refclk, NULL, &crtc_state->dpll)) { - DRM_ERROR("Couldn't find PLL settings for mode!\n"); + drm_err(&dev_priv->drm, + "Couldn't find PLL settings for mode!\n"); return -EINVAL; } @@ -8868,7 +9009,9 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(dev_priv)) { refclk = dev_priv->vbt.lvds_ssc_freq; - DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); + drm_dbg_kms(&dev_priv->drm, + "using SSC reference clock of %d kHz\n", + refclk); } if (intel_is_dual_link_lvds(dev_priv)) @@ -8888,7 +9031,8 @@ static int g4x_crtc_compute_clock(struct intel_crtc *crtc, if (!crtc_state->clock_set && !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, refclk, NULL, &crtc_state->dpll)) { - DRM_ERROR("Couldn't find PLL settings for mode!\n"); + drm_err(&dev_priv->drm, + "Couldn't find PLL settings for mode!\n"); return -EINVAL; } @@ -8911,7 +9055,9 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(dev_priv)) { refclk = dev_priv->vbt.lvds_ssc_freq; - DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); + drm_dbg_kms(&dev_priv->drm, + "using SSC reference clock of %d kHz\n", + refclk); } limit = &pnv_limits_lvds; @@ -8922,7 +9068,8 @@ static int pnv_crtc_compute_clock(struct intel_crtc *crtc, if (!crtc_state->clock_set && !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, refclk, NULL, &crtc_state->dpll)) { - DRM_ERROR("Couldn't find PLL settings for mode!\n"); + drm_err(&dev_priv->drm, + "Couldn't find PLL settings for mode!\n"); return -EINVAL; } @@ -8945,7 +9092,9 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(dev_priv)) { refclk = dev_priv->vbt.lvds_ssc_freq; - DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); + drm_dbg_kms(&dev_priv->drm, + "using SSC reference clock of %d kHz\n", + refclk); } limit = &intel_limits_i9xx_lvds; @@ -8956,7 +9105,8 @@ static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, if (!crtc_state->clock_set && !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, refclk, NULL, &crtc_state->dpll)) { - DRM_ERROR("Couldn't find PLL settings for mode!\n"); + drm_err(&dev_priv->drm, + "Couldn't find PLL settings for mode!\n"); return -EINVAL; } @@ -8970,6 +9120,7 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc, { int refclk = 100000; const struct intel_limit *limit = &intel_limits_chv; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state)); @@ -8977,7 +9128,7 @@ static int chv_crtc_compute_clock(struct intel_crtc *crtc, if (!crtc_state->clock_set && !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, refclk, NULL, &crtc_state->dpll)) { - DRM_ERROR("Couldn't find PLL settings for mode!\n"); + drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); return -EINVAL; } @@ -8991,6 +9142,7 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc, { int refclk = 100000; const struct intel_limit *limit = &intel_limits_vlv; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state)); @@ -8998,7 +9150,7 @@ static int vlv_crtc_compute_clock(struct intel_crtc *crtc, if (!crtc_state->clock_set && !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, refclk, NULL, &crtc_state->dpll)) { - DRM_ERROR("Couldn't find PLL settings for mode!\n"); + drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); return -EINVAL; } @@ -9025,7 +9177,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, if (!i9xx_has_pfit(dev_priv)) return; - tmp = I915_READ(PFIT_CONTROL); + tmp = intel_de_read(dev_priv, PFIT_CONTROL); if (!(tmp & PFIT_ENABLE)) return; @@ -9039,7 +9191,8 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, } pipe_config->gmch_pfit.control = tmp; - pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); + pipe_config->gmch_pfit.pgm_ratios = intel_de_read(dev_priv, + PFIT_PGM_RATIOS); } static void vlv_crtc_clock_get(struct intel_crtc *crtc, @@ -9087,11 +9240,11 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - WARN_ON(pipe != crtc->pipe); + drm_WARN_ON(dev, pipe != crtc->pipe); intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { - DRM_DEBUG_KMS("failed to alloc fb\n"); + drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); return; } @@ -9099,7 +9252,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->dev = dev; - val = I915_READ(DSPCNTR(i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); if (INTEL_GEN(dev_priv) >= 4) { if (val & DISPPLANE_TILED) { @@ -9120,34 +9273,37 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->format = drm_format_info(fourcc); if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - offset = I915_READ(DSPOFFSET(i9xx_plane)); - base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; + offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; } else if (INTEL_GEN(dev_priv) >= 4) { if (plane_config->tiling) - offset = I915_READ(DSPTILEOFF(i9xx_plane)); + offset = intel_de_read(dev_priv, + DSPTILEOFF(i9xx_plane)); else - offset = I915_READ(DSPLINOFF(i9xx_plane)); - base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; + offset = intel_de_read(dev_priv, + DSPLINOFF(i9xx_plane)); + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000; } else { - base = I915_READ(DSPADDR(i9xx_plane)); + base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); } plane_config->base = base; - val = I915_READ(PIPESRC(pipe)); + val = intel_de_read(dev_priv, PIPESRC(pipe)); fb->width = ((val >> 16) & 0xfff) + 1; fb->height = ((val >> 0) & 0xfff) + 1; - val = I915_READ(DSPSTRIDE(i9xx_plane)); + val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); fb->pitches[0] = val & 0xffffffc0; aligned_height = intel_fb_align_height(fb, 0, fb->height); plane_config->size = fb->pitches[0] * aligned_height; - DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - crtc->base.name, plane->base.name, fb->width, fb->height, - fb->format->cpp[0] * 8, base, fb->pitches[0], - plane_config->size); + drm_dbg_kms(&dev_priv->drm, + "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.name, plane->base.name, fb->width, fb->height, + fb->format->cpp[0] * 8, base, fb->pitches[0], + plane_config->size); plane_config->fb = intel_fb; } @@ -9192,11 +9348,12 @@ bdw_get_pipemisc_output_format(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 tmp; - tmp = I915_READ(PIPEMISC(crtc->pipe)); + tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); if (tmp & PIPEMISC_YUV420_ENABLE) { /* We support 4:2:0 in full blend mode only */ - WARN_ON((tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); + drm_WARN_ON(&dev_priv->drm, + (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0); return INTEL_OUTPUT_FORMAT_YCBCR420; } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { @@ -9214,7 +9371,7 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; u32 tmp; - tmp = I915_READ(DSPCNTR(i9xx_plane)); + tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); if (tmp & DISPPLANE_GAMMA_ENABLE) crtc_state->gamma_enable = true; @@ -9245,7 +9402,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, ret = false; - tmp = I915_READ(PIPECONF(crtc->pipe)); + tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); if (!(tmp & PIPECONF_ENABLE)) goto out; @@ -9274,7 +9431,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, PIPECONF_GAMMA_MODE_SHIFT; if (IS_CHERRYVIEW(dev_priv)) - pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe)); + pipe_config->cgm_mode = intel_de_read(dev_priv, + CGM_PIPE_MODE(crtc->pipe)); i9xx_get_pipe_color_config(pipe_config); intel_color_get_config(pipe_config); @@ -9292,14 +9450,14 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) tmp = dev_priv->chv_dpll_md[crtc->pipe]; else - tmp = I915_READ(DPLL_MD(crtc->pipe)); + tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); pipe_config->pixel_multiplier = ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; pipe_config->dpll_hw_state.dpll_md = tmp; } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { - tmp = I915_READ(DPLL(crtc->pipe)); + tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)); pipe_config->pixel_multiplier = ((tmp & SDVO_MULTIPLIER_MASK) >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; @@ -9309,10 +9467,13 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, * function. */ pipe_config->pixel_multiplier = 1; } - pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); + pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, + DPLL(crtc->pipe)); if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { - pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); - pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); + pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, + FP0(crtc->pipe)); + pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, + FP1(crtc->pipe)); } else { /* Mask out read-only status bits. */ pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | @@ -9381,8 +9542,8 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } /* Check if any DPLLs are using the SSC source */ - for (i = 0; i < dev_priv->num_shared_dpll; i++) { - u32 temp = I915_READ(PCH_DPLL(i)); + for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { + u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); if (!(temp & DPLL_VCO_ENABLE)) continue; @@ -9394,15 +9555,16 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) } } - DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", - has_panel, has_lvds, has_ck505, using_ssc_source); + drm_dbg_kms(&dev_priv->drm, + "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", + has_panel, has_lvds, has_ck505, using_ssc_source); /* Ironlake: try to setup display ref clock before DPLL * enabling. This is only under driver's control after * PCH B stepping, previous chipset stepping should be * ignoring this setting. */ - val = I915_READ(PCH_DREF_CONTROL); + val = intel_de_read(dev_priv, PCH_DREF_CONTROL); /* As we must carefully and slowly disable/enable each source in turn, * compute the final state we want first and check if we need to @@ -9454,14 +9616,14 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) /* SSC must be turned on before enabling the CPU output */ if (intel_panel_use_ssc(dev_priv) && can_ssc) { - DRM_DEBUG_KMS("Using SSC on panel\n"); + drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n"); val |= DREF_SSC1_ENABLE; } else val &= ~DREF_SSC1_ENABLE; /* Get SSC going before enabling the outputs */ - I915_WRITE(PCH_DREF_CONTROL, val); - POSTING_READ(PCH_DREF_CONTROL); + intel_de_write(dev_priv, PCH_DREF_CONTROL, val); + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); udelay(200); val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; @@ -9469,30 +9631,31 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) /* Enable CPU source on CPU attached eDP */ if (has_cpu_edp) { if (intel_panel_use_ssc(dev_priv) && can_ssc) { - DRM_DEBUG_KMS("Using SSC on eDP\n"); + drm_dbg_kms(&dev_priv->drm, + "Using SSC on eDP\n"); val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; } else val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; } else val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; - I915_WRITE(PCH_DREF_CONTROL, val); - POSTING_READ(PCH_DREF_CONTROL); + intel_de_write(dev_priv, PCH_DREF_CONTROL, val); + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); udelay(200); } else { - DRM_DEBUG_KMS("Disabling CPU source output\n"); + drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n"); val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; /* Turn off CPU output */ val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; - I915_WRITE(PCH_DREF_CONTROL, val); - POSTING_READ(PCH_DREF_CONTROL); + intel_de_write(dev_priv, PCH_DREF_CONTROL, val); + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); udelay(200); if (!using_ssc_source) { - DRM_DEBUG_KMS("Disabling SSC source\n"); + drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n"); /* Turn off the SSC source */ val &= ~DREF_SSC_SOURCE_MASK; @@ -9501,8 +9664,8 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv) /* Turn off SSC1 */ val &= ~DREF_SSC1_ENABLE; - I915_WRITE(PCH_DREF_CONTROL, val); - POSTING_READ(PCH_DREF_CONTROL); + intel_de_write(dev_priv, PCH_DREF_CONTROL, val); + intel_de_posting_read(dev_priv, PCH_DREF_CONTROL); udelay(200); } } @@ -9514,21 +9677,21 @@ static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) { u32 tmp; - tmp = I915_READ(SOUTH_CHICKEN2); + tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); tmp |= FDI_MPHY_IOSFSB_RESET_CTL; - I915_WRITE(SOUTH_CHICKEN2, tmp); + intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); - if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & + if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & FDI_MPHY_IOSFSB_RESET_STATUS, 100)) - DRM_ERROR("FDI mPHY reset assert timeout\n"); + drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n"); - tmp = I915_READ(SOUTH_CHICKEN2); + tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2); tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; - I915_WRITE(SOUTH_CHICKEN2, tmp); + intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp); - if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & + if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) - DRM_ERROR("FDI mPHY reset de-assert timeout\n"); + drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n"); } /* WaMPhyProgramming:hsw */ @@ -9617,10 +9780,11 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, { u32 reg, tmp; - if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) + if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread, + "FDI requires downspread\n")) with_spread = true; - if (WARN(HAS_PCH_LPT_LP(dev_priv) && - with_fdi, "LP PCH doesn't have FDI\n")) + if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) && + with_fdi, "LP PCH doesn't have FDI\n")) with_fdi = false; mutex_lock(&dev_priv->sb_lock); @@ -9714,10 +9878,10 @@ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) u32 tmp; int idx = BEND_IDX(steps); - if (WARN_ON(steps % 5 != 0)) + if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0)) return; - if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) + if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))) return; mutex_lock(&dev_priv->sb_lock); @@ -9740,8 +9904,8 @@ static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv) { - u32 fuse_strap = I915_READ(FUSE_STRAP); - u32 ctl = I915_READ(SPLL_CTL); + u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); + u32 ctl = intel_de_read(dev_priv, SPLL_CTL); if ((ctl & SPLL_PLL_ENABLE) == 0) return false; @@ -9760,8 +9924,8 @@ static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv) static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv, enum intel_dpll_id id) { - u32 fuse_strap = I915_READ(FUSE_STRAP); - u32 ctl = I915_READ(WRPLL_CTL(id)); + u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); + u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); if ((ctl & WRPLL_PLL_ENABLE) == 0) return false; @@ -9810,17 +9974,17 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) dev_priv->pch_ssc_use = 0; if (spll_uses_pch_ssc(dev_priv)) { - DRM_DEBUG_KMS("SPLL using PCH SSC\n"); + drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n"); dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); } if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) { - DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n"); + drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n"); dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); } if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) { - DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n"); + drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n"); dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); } @@ -9885,8 +10049,8 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) * This would end up with an odd purple hue over * the entire display. Make sure we don't do it. */ - WARN_ON(crtc_state->limited_color_range && - crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); + drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->limited_color_range) val |= PIPECONF_COLOR_RANGE_SELECT; @@ -9898,8 +10062,8 @@ static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= PIPECONF_FRAME_START_DELAY(0); - I915_WRITE(PIPECONF(pipe), val); - POSTING_READ(PIPECONF(pipe)); + intel_de_write(dev_priv, PIPECONF(pipe), val); + intel_de_posting_read(dev_priv, PIPECONF(pipe)); } static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) @@ -9921,8 +10085,8 @@ static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW; - I915_WRITE(PIPECONF(cpu_transcoder), val); - POSTING_READ(PIPECONF(cpu_transcoder)); + intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); + intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)); } static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) @@ -9965,7 +10129,10 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) BIT(PLANE_CURSOR))) == 0) val |= PIPEMISC_HDR_MODE_PRECISION; - I915_WRITE(PIPEMISC(crtc->pipe), val); + if (INTEL_GEN(dev_priv) >= 12) + val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; + + intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); } int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) @@ -9973,7 +10140,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 tmp; - tmp = I915_READ(PIPEMISC(crtc->pipe)); + tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)); switch (tmp & PIPEMISC_DITHER_BPC_MASK) { case PIPEMISC_DITHER_6_BPC: @@ -10126,8 +10293,9 @@ static int ilk_crtc_compute_clock(struct intel_crtc *crtc, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { if (intel_panel_use_ssc(dev_priv)) { - DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", - dev_priv->vbt.lvds_ssc_freq); + drm_dbg_kms(&dev_priv->drm, + "using SSC reference clock of %d kHz\n", + dev_priv->vbt.lvds_ssc_freq); refclk = dev_priv->vbt.lvds_ssc_freq; } @@ -10149,15 +10317,17 @@ static int ilk_crtc_compute_clock(struct intel_crtc *crtc, if (!crtc_state->clock_set && !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, refclk, NULL, &crtc_state->dpll)) { - DRM_ERROR("Couldn't find PLL settings for mode!\n"); + drm_err(&dev_priv->drm, + "Couldn't find PLL settings for mode!\n"); return -EINVAL; } ilk_compute_dpll(crtc, crtc_state, NULL); if (!intel_reserve_shared_dplls(state, crtc, NULL)) { - DRM_DEBUG_KMS("failed to find PLL for pipe %c\n", - pipe_name(crtc->pipe)); + drm_dbg_kms(&dev_priv->drm, + "failed to find PLL for pipe %c\n", + pipe_name(crtc->pipe)); return -EINVAL; } @@ -10171,12 +10341,12 @@ static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); enum pipe pipe = crtc->pipe; - m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); - m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); - m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) + m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe)); + m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe)); + m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) & ~TU_SIZE_MASK; - m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); - m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) + m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe)); + m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; } @@ -10189,30 +10359,38 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; if (INTEL_GEN(dev_priv) >= 5) { - m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); - m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); - m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) + m_n->link_m = intel_de_read(dev_priv, + PIPE_LINK_M1(transcoder)); + m_n->link_n = intel_de_read(dev_priv, + PIPE_LINK_N1(transcoder)); + m_n->gmch_m = intel_de_read(dev_priv, + PIPE_DATA_M1(transcoder)) & ~TU_SIZE_MASK; - m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); - m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) + m_n->gmch_n = intel_de_read(dev_priv, + PIPE_DATA_N1(transcoder)); + m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder)) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) { - m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); - m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); - m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) + m2_n2->link_m = intel_de_read(dev_priv, + PIPE_LINK_M2(transcoder)); + m2_n2->link_n = intel_de_read(dev_priv, + PIPE_LINK_N2(transcoder)); + m2_n2->gmch_m = intel_de_read(dev_priv, + PIPE_DATA_M2(transcoder)) & ~TU_SIZE_MASK; - m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); - m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) + m2_n2->gmch_n = intel_de_read(dev_priv, + PIPE_DATA_N2(transcoder)); + m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder)) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; } } else { - m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); - m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); - m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) + m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe)); + m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe)); + m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) & ~TU_SIZE_MASK; - m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); - m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) + m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe)); + m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)) & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; } } @@ -10247,12 +10425,14 @@ static void skl_get_pfit_config(struct intel_crtc *crtc, /* find scaler attached to this pipe */ for (i = 0; i < crtc->num_scalers; i++) { - ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); + ps_ctrl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)); if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { id = i; pipe_config->pch_pfit.enabled = true; - pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); - pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); + pipe_config->pch_pfit.pos = intel_de_read(dev_priv, + SKL_PS_WIN_POS(crtc->pipe, i)); + pipe_config->pch_pfit.size = intel_de_read(dev_priv, + SKL_PS_WIN_SZ(crtc->pipe, i)); scaler_state->scalers[i].in_use = true; break; } @@ -10284,11 +10464,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, if (!plane->get_hw_state(plane, &pipe)) return; - WARN_ON(pipe != crtc->pipe); + drm_WARN_ON(dev, pipe != crtc->pipe); intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); if (!intel_fb) { - DRM_DEBUG_KMS("failed to alloc fb\n"); + drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n"); return; } @@ -10296,7 +10476,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, fb->dev = dev; - val = I915_READ(PLANE_CTL(pipe, plane_id)); + val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)); if (INTEL_GEN(dev_priv) >= 11) pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK; @@ -10304,7 +10484,8 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, pixel_format = val & PLANE_CTL_FORMAT_MASK; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { - alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id)); + alpha = intel_de_read(dev_priv, + PLANE_COLOR_CTL(pipe, plane_id)); alpha &= PLANE_COLOR_ALPHA_MASK; } else { alpha = val & PLANE_CTL_ALPHA_MASK; @@ -10368,16 +10549,16 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, val & PLANE_CTL_FLIP_HORIZONTAL) plane_config->rotation |= DRM_MODE_REFLECT_X; - base = I915_READ(PLANE_SURF(pipe, plane_id)) & 0xfffff000; + base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & 0xfffff000; plane_config->base = base; - offset = I915_READ(PLANE_OFFSET(pipe, plane_id)); + offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)); - val = I915_READ(PLANE_SIZE(pipe, plane_id)); + val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)); fb->height = ((val >> 16) & 0xffff) + 1; fb->width = ((val >> 0) & 0xffff) + 1; - val = I915_READ(PLANE_STRIDE(pipe, plane_id)); + val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)); stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0); fb->pitches[0] = (val & 0x3ff) * stride_mult; @@ -10385,10 +10566,11 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, plane_config->size = fb->pitches[0] * aligned_height; - DRM_DEBUG_KMS("%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", - crtc->base.name, plane->base.name, fb->width, fb->height, - fb->format->cpp[0] * 8, base, fb->pitches[0], - plane_config->size); + drm_dbg_kms(&dev_priv->drm, + "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", + crtc->base.name, plane->base.name, fb->width, fb->height, + fb->format->cpp[0] * 8, base, fb->pitches[0], + plane_config->size); plane_config->fb = intel_fb; return; @@ -10404,19 +10586,21 @@ static void ilk_get_pfit_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); u32 tmp; - tmp = I915_READ(PF_CTL(crtc->pipe)); + tmp = intel_de_read(dev_priv, PF_CTL(crtc->pipe)); if (tmp & PF_ENABLE) { pipe_config->pch_pfit.enabled = true; - pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); - pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); + pipe_config->pch_pfit.pos = intel_de_read(dev_priv, + PF_WIN_POS(crtc->pipe)); + pipe_config->pch_pfit.size = intel_de_read(dev_priv, + PF_WIN_SZ(crtc->pipe)); /* We currently do not free assignements of panel fitters on * ivb/hsw (since we don't use the higher upscaling modes which * differentiates them) so just WARN about this case for now. */ if (IS_GEN(dev_priv, 7)) { - WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != - PF_PIPE_SEL_IVB(crtc->pipe)); + drm_WARN_ON(dev, (tmp & PF_PIPE_SEL_MASK_IVB) != + PF_PIPE_SEL_IVB(crtc->pipe)); } } } @@ -10441,7 +10625,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, pipe_config->master_transcoder = INVALID_TRANSCODER; ret = false; - tmp = I915_READ(PIPECONF(crtc->pipe)); + tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)); if (!(tmp & PIPECONF_ENABLE)) goto out; @@ -10478,18 +10662,19 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >> PIPECONF_GAMMA_MODE_SHIFT; - pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); + pipe_config->csc_mode = intel_de_read(dev_priv, + PIPE_CSC_MODE(crtc->pipe)); i9xx_get_pipe_color_config(pipe_config); intel_color_get_config(pipe_config); - if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { + if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { struct intel_shared_dpll *pll; enum intel_dpll_id pll_id; pipe_config->has_pch_encoder = true; - tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); + tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe)); pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> FDI_DP_PORT_WIDTH_SHIFT) + 1; @@ -10502,7 +10687,7 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, */ pll_id = (enum intel_dpll_id) crtc->pipe; } else { - tmp = I915_READ(PCH_DPLL_SEL); + tmp = intel_de_read(dev_priv, PCH_DPLL_SEL); if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) pll_id = DPLL_ID_PCH_PLL_B; else @@ -10513,8 +10698,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, intel_get_shared_dpll_by_id(dev_priv, pll_id); pll = pipe_config->shared_dpll; - WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, - &pipe_config->dpll_hw_state)); + drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll, + &pipe_config->dpll_hw_state)); tmp = pipe_config->dpll_hw_state.dpll; pipe_config->pixel_multiplier = @@ -10552,8 +10737,9 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc, intel_get_crtc_new_encoder(state, crtc_state); if (!intel_reserve_shared_dplls(state, crtc, encoder)) { - DRM_DEBUG_KMS("failed to find PLL for pipe %c\n", - pipe_name(crtc->pipe)); + drm_dbg_kms(&dev_priv->drm, + "failed to find PLL for pipe %c\n", + pipe_name(crtc->pipe)); return -EINVAL; } } @@ -10567,10 +10753,10 @@ static void cnl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, enum intel_dpll_id id; u32 temp; - temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); + temp = intel_de_read(dev_priv, DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port); - if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) + if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2)) return; pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); @@ -10585,24 +10771,25 @@ static void icl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, u32 temp; if (intel_phy_is_combo(dev_priv, phy)) { - temp = I915_READ(ICL_DPCLKA_CFGCR0) & + temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0) & ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); id = temp >> ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy); port_dpll_id = ICL_PORT_DPLL_DEFAULT; } else if (intel_phy_is_tc(dev_priv, phy)) { - u32 clk_sel = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; + u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; if (clk_sel == DDI_CLK_SEL_MG) { id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, port)); port_dpll_id = ICL_PORT_DPLL_MG_PHY; } else { - WARN_ON(clk_sel < DDI_CLK_SEL_TBT_162); + drm_WARN_ON(&dev_priv->drm, + clk_sel < DDI_CLK_SEL_TBT_162); id = DPLL_ID_ICL_TBTPLL; port_dpll_id = ICL_PORT_DPLL_DEFAULT; } } else { - WARN(1, "Invalid port %x\n", port); + drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port); return; } @@ -10629,7 +10816,7 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, id = DPLL_ID_SKL_DPLL2; break; default: - DRM_ERROR("Incorrect port type\n"); + drm_err(&dev_priv->drm, "Incorrect port type\n"); return; } @@ -10642,10 +10829,10 @@ static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, enum intel_dpll_id id; u32 temp; - temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); + temp = intel_de_read(dev_priv, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); id = temp >> (port * 3 + 1); - if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) + if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3)) return; pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); @@ -10655,7 +10842,7 @@ static void hsw_get_ddi_pll(struct drm_i915_private *dev_priv, enum port port, struct intel_crtc_state *pipe_config) { enum intel_dpll_id id; - u32 ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); + u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port)); switch (ddi_pll_sel) { case PORT_CLK_SEL_WRPLL1: @@ -10723,7 +10910,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, bool force_thru = false; enum pipe trans_pipe; - tmp = I915_READ(TRANS_DDI_FUNC_CTL(panel_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(panel_transcoder)); if (!(tmp & TRANS_DDI_FUNC_ENABLE)) continue; @@ -10738,8 +10926,9 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: - WARN(1, "unknown pipe linked to transcoder %s\n", - transcoder_name(panel_transcoder)); + drm_WARN(dev, 1, + "unknown pipe linked to transcoder %s\n", + transcoder_name(panel_transcoder)); /* fall through */ case TRANS_DDI_EDP_INPUT_A_ONOFF: force_thru = true; @@ -10767,11 +10956,11 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, /* * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1 */ - WARN_ON((enabled_panel_transcoders & BIT(TRANSCODER_EDP)) && - enabled_panel_transcoders != BIT(TRANSCODER_EDP)); + drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) && + enabled_panel_transcoders != BIT(TRANSCODER_EDP)); power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); - WARN_ON(*power_domain_mask & BIT_ULL(power_domain)); + drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); wf = intel_display_power_get_if_enabled(dev_priv, power_domain); if (!wf) @@ -10780,7 +10969,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, wakerefs[power_domain] = wf; *power_domain_mask |= BIT_ULL(power_domain); - tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); + tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)); return tmp & PIPECONF_ENABLE; } @@ -10805,7 +10994,7 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, cpu_transcoder = TRANSCODER_DSI_C; power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); - WARN_ON(*power_domain_mask & BIT_ULL(power_domain)); + drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain)); wf = intel_display_power_get_if_enabled(dev_priv, power_domain); if (!wf) @@ -10825,11 +11014,11 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, break; /* XXX: this works for video mode only */ - tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); + tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); if (!(tmp & DPI_ENABLE)) continue; - tmp = I915_READ(MIPI_CTRL(port)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) continue; @@ -10853,7 +11042,8 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc, port = (cpu_transcoder == TRANSCODER_DSI_A) ? PORT_A : PORT_B; } else { - tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(cpu_transcoder)); if (INTEL_GEN(dev_priv) >= 12) port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp); else @@ -10873,7 +11063,8 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc, pll = pipe_config->shared_dpll; if (pll) { - WARN_ON(!pll->info->funcs->get_hw_state(dev_priv, pll, + drm_WARN_ON(&dev_priv->drm, + !pll->info->funcs->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)); } @@ -10883,10 +11074,10 @@ static void hsw_get_ddi_port_state(struct intel_crtc *crtc, * the PCH transcoder is on. */ if (INTEL_GEN(dev_priv) < 9 && - (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { + (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF) & TRANS_ENABLE) { pipe_config->has_pch_encoder = true; - tmp = I915_READ(FDI_RX_CTL(PIPE_A)); + tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)); pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> FDI_DP_PORT_WIDTH_SHIFT) + 1; @@ -10899,7 +11090,8 @@ static enum transcoder transcoder_master_readout(struct drm_i915_private *dev_pr { u32 trans_port_sync, master_select; - trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder)); + trans_port_sync = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL2(cpu_transcoder)); if ((trans_port_sync & PORT_SYNC_MODE_ENABLE) == 0) return INVALID_TRANSCODER; @@ -10943,8 +11135,9 @@ static void icl_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) intel_display_power_put(dev_priv, power_domain, trans_wakeref); } - WARN_ON(crtc_state->master_transcoder != INVALID_TRANSCODER && - crtc_state->sync_mode_slaves_mask); + drm_WARN_ON(&dev_priv->drm, + crtc_state->master_transcoder != INVALID_TRANSCODER && + crtc_state->sync_mode_slaves_mask); } static bool hsw_get_pipe_config(struct intel_crtc *crtc, @@ -10955,6 +11148,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, enum intel_display_power_domain power_domain; u64 power_domain_mask; bool active; + u32 tmp; pipe_config->master_transcoder = INVALID_TRANSCODER; @@ -10974,7 +11168,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, if (IS_GEN9_LP(dev_priv) && bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask, wakerefs)) { - WARN_ON(active); + drm_WARN_ON(&dev_priv->drm, active); active = true; } @@ -10990,7 +11184,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, intel_get_pipe_src_size(crtc, pipe_config); if (IS_HASWELL(dev_priv)) { - u32 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); + u32 tmp = intel_de_read(dev_priv, + PIPECONF(pipe_config->cpu_transcoder)); if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW) pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; @@ -11013,12 +11208,14 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444; } - pipe_config->gamma_mode = I915_READ(GAMMA_MODE(crtc->pipe)); + pipe_config->gamma_mode = intel_de_read(dev_priv, + GAMMA_MODE(crtc->pipe)); - pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); + pipe_config->csc_mode = intel_de_read(dev_priv, + PIPE_CSC_MODE(crtc->pipe)); if (INTEL_GEN(dev_priv) >= 9) { - u32 tmp = I915_READ(SKL_BOTTOM_COLOR(crtc->pipe)); + tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)); if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE) pipe_config->gamma_enable = true; @@ -11031,8 +11228,14 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, intel_color_get_config(pipe_config); + tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)); + pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp); + if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + pipe_config->ips_linetime = + REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp); + power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); - WARN_ON(power_domain_mask & BIT_ULL(power_domain)); + drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain)); wf = intel_display_power_get_if_enabled(dev_priv, power_domain); if (wf) { @@ -11047,7 +11250,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, if (hsw_crtc_supports_ips(crtc)) { if (IS_HASWELL(dev_priv)) - pipe_config->ips_enabled = I915_READ(IPS_CTL) & IPS_ENABLE; + pipe_config->ips_enabled = intel_de_read(dev_priv, + IPS_CTL) & IPS_ENABLE; else { /* * We cannot readout IPS state on broadwell, set to @@ -11061,7 +11265,8 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, if (pipe_config->cpu_transcoder != TRANSCODER_EDP && !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = - I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; + intel_de_read(dev_priv, + PIPE_MULT(pipe_config->cpu_transcoder)) + 1; } else { pipe_config->pixel_multiplier = 1; } @@ -11150,7 +11355,8 @@ static int intel_cursor_check_surface(struct intel_plane_state *plane_state) plane_state, 0); if (src_x != 0 || src_y != 0) { - DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); + drm_dbg_kms(&dev_priv->drm, + "Arbitrary cursor panning not supported\n"); return -EINVAL; } @@ -11181,10 +11387,11 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->hw.fb; + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); int ret; if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) { - DRM_DEBUG_KMS("cursor cannot be tiled\n"); + drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n"); return -EINVAL; } @@ -11255,6 +11462,7 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state) { const struct drm_framebuffer *fb = plane_state->hw.fb; + struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); int ret; ret = intel_check_cursor(crtc_state, plane_state); @@ -11267,14 +11475,15 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i845_cursor_size_ok(plane_state)) { - DRM_DEBUG("Cursor dimension %dx%d not supported\n", - drm_rect_width(&plane_state->uapi.dst), - drm_rect_height(&plane_state->uapi.dst)); + drm_dbg_kms(&i915->drm, + "Cursor dimension %dx%d not supported\n", + drm_rect_width(&plane_state->uapi.dst), + drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; } - WARN_ON(plane_state->uapi.visible && - plane_state->color_plane[0].stride != fb->pitches[0]); + drm_WARN_ON(&i915->drm, plane_state->uapi.visible && + plane_state->color_plane[0].stride != fb->pitches[0]); switch (fb->pitches[0]) { case 256: @@ -11283,8 +11492,8 @@ static int i845_check_cursor(struct intel_crtc_state *crtc_state, case 2048: break; default: - DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", - fb->pitches[0]); + drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n", + fb->pitches[0]); return -EINVAL; } @@ -11322,17 +11531,17 @@ static void i845_update_cursor(struct intel_plane *plane, if (plane->cursor.base != base || plane->cursor.size != size || plane->cursor.cntl != cntl) { - I915_WRITE_FW(CURCNTR(PIPE_A), 0); - I915_WRITE_FW(CURBASE(PIPE_A), base); - I915_WRITE_FW(CURSIZE, size); - I915_WRITE_FW(CURPOS(PIPE_A), pos); - I915_WRITE_FW(CURCNTR(PIPE_A), cntl); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); + intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); + intel_de_write_fw(dev_priv, CURSIZE, size); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -11357,7 +11566,7 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; + ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; *pipe = PIPE_A; @@ -11483,20 +11692,22 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, /* Check for which cursor types we support */ if (!i9xx_cursor_size_ok(plane_state)) { - DRM_DEBUG("Cursor dimension %dx%d not supported\n", - drm_rect_width(&plane_state->uapi.dst), - drm_rect_height(&plane_state->uapi.dst)); + drm_dbg(&dev_priv->drm, + "Cursor dimension %dx%d not supported\n", + drm_rect_width(&plane_state->uapi.dst), + drm_rect_height(&plane_state->uapi.dst)); return -EINVAL; } - WARN_ON(plane_state->uapi.visible && - plane_state->color_plane[0].stride != fb->pitches[0]); + drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible && + plane_state->color_plane[0].stride != fb->pitches[0]); if (fb->pitches[0] != drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { - DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", - fb->pitches[0], - drm_rect_width(&plane_state->uapi.dst)); + drm_dbg_kms(&dev_priv->drm, + "Invalid cursor stride (%u) (cursor width %d)\n", + fb->pitches[0], + drm_rect_width(&plane_state->uapi.dst)); return -EINVAL; } @@ -11512,7 +11723,8 @@ static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, */ if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { - DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); + drm_dbg_kms(&dev_priv->drm, + "CHV cursor C not allowed to straddle the left screen edge\n"); return -EINVAL; } @@ -11573,17 +11785,18 @@ static void i9xx_update_cursor(struct intel_plane *plane, plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { if (HAS_CUR_FBC(dev_priv)) - I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); - I915_WRITE_FW(CURCNTR(pipe), cntl); - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), + fbc_ctl); + intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { - I915_WRITE_FW(CURPOS(pipe), pos); - I915_WRITE_FW(CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURBASE(pipe), base); } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); @@ -11614,7 +11827,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = I915_READ(CURCNTR(plane->pipe)); + val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); ret = val & MCURSOR_MODE; @@ -11700,13 +11913,13 @@ int intel_get_load_detect_pipe(struct drm_connector *connector, struct intel_crtc_state *crtc_state; int ret, i = -1; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", - connector->base.id, connector->name, - encoder->base.id, encoder->name); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", + connector->base.id, connector->name, + encoder->base.id, encoder->name); old->restore_state = NULL; - WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); + drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); /* * Algorithm gets a little messy: @@ -11753,7 +11966,8 @@ int intel_get_load_detect_pipe(struct drm_connector *connector, * If we didn't find an unused CRTC, don't use any. */ if (!crtc) { - DRM_DEBUG_KMS("no pipe available for load-detect\n"); + drm_dbg_kms(&dev_priv->drm, + "no pipe available for load-detect\n"); ret = -ENODEV; goto fail; } @@ -11804,13 +12018,16 @@ found: if (!ret) ret = drm_atomic_add_affected_planes(restore_state, crtc); if (ret) { - DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); + drm_dbg_kms(&dev_priv->drm, + "Failed to create a copy of old state to restore: %i\n", + ret); goto fail; } ret = drm_atomic_commit(state); if (ret) { - DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); + drm_dbg_kms(&dev_priv->drm, + "failed to set mode on load-detect pipe\n"); goto fail; } @@ -11843,20 +12060,22 @@ void intel_release_load_detect_pipe(struct drm_connector *connector, { struct intel_encoder *intel_encoder = intel_attached_encoder(to_intel_connector(connector)); + struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); struct drm_encoder *encoder = &intel_encoder->base; struct drm_atomic_state *state = old->restore_state; int ret; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", - connector->base.id, connector->name, - encoder->base.id, encoder->name); + drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", + connector->base.id, connector->name, + encoder->base.id, encoder->name); if (!state) return; ret = drm_atomic_helper_commit_duplicated_state(state, ctx); if (ret) - DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); + drm_dbg_kms(&i915->drm, + "Couldn't release load detect pipe: %i\n", ret); drm_atomic_state_put(state); } @@ -11921,8 +12140,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, 7 : 14; break; default: - DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " - "mode\n", (int)(dpll & DPLL_MODE_MASK)); + drm_dbg_kms(&dev_priv->drm, + "Unknown DPLL mode %08x in programmed " + "mode\n", (int)(dpll & DPLL_MODE_MASK)); return; } @@ -11931,7 +12151,8 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, else port_clock = i9xx_calc_dpll_params(refclk, &clock); } else { - u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); + u32 lvds = IS_I830(dev_priv) ? 0 : intel_de_read(dev_priv, + LVDS); bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); if (is_lvds) { @@ -12142,7 +12363,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat was_visible = old_plane_state->uapi.visible; visible = plane_state->uapi.visible; - if (!was_crtc_enabled && WARN_ON(was_visible)) + if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)) was_visible = false; /* @@ -12168,11 +12389,12 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat turn_off = was_visible && (!visible || mode_changed); turn_on = visible && (!was_visible || mode_changed); - DRM_DEBUG_ATOMIC("[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", - crtc->base.base.id, crtc->base.name, - plane->base.base.id, plane->base.name, - was_visible, visible, - turn_off, turn_on, mode_changed); + drm_dbg_atomic(&dev_priv->drm, + "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", + crtc->base.base.id, crtc->base.name, + plane->base.base.id, plane->base.name, + was_visible, visible, + turn_off, turn_on, mode_changed); if (turn_on) { if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) @@ -12349,8 +12571,9 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) } if (!linked_state) { - DRM_DEBUG_KMS("Need %d free Y planes for planar YUV\n", - hweight8(crtc_state->nv12_planes)); + drm_dbg_kms(&dev_priv->drm, + "Need %d free Y planes for planar YUV\n", + hweight8(crtc_state->nv12_planes)); return -EINVAL; } @@ -12361,7 +12584,8 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) linked_state->planar_linked_plane = plane; crtc_state->active_planes |= BIT(linked->id); crtc_state->update_planes |= BIT(linked->id); - DRM_DEBUG_KMS("Using %s as Y plane for %s\n", linked->base.name, plane->base.name); + drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n", + linked->base.name, plane->base.name); /* Copy parameters to slave plane */ linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE; @@ -12398,120 +12622,74 @@ static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; } -static bool -intel_atomic_is_master_connector(struct intel_crtc_state *crtc_state) +static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) { - struct drm_crtc *crtc = crtc_state->uapi.crtc; - struct drm_atomic_state *state = crtc_state->uapi.state; - struct drm_connector *connector; - struct drm_connector_state *connector_state; - int i; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; - for_each_new_connector_in_state(state, connector, connector_state, i) { - if (connector_state->crtc != crtc) - continue; - if (connector->has_tile && - connector->tile_h_loc == connector->num_h_tile - 1 && - connector->tile_v_loc == connector->num_v_tile - 1) - return true; - } + if (!crtc_state->hw.enable) + return 0; - return false; + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + adjusted_mode->crtc_clock); } -static void reset_port_sync_mode_state(struct intel_crtc_state *crtc_state) +static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, + const struct intel_cdclk_state *cdclk_state) { - crtc_state->master_transcoder = INVALID_TRANSCODER; - crtc_state->sync_mode_slaves_mask = 0; + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + + if (!crtc_state->hw.enable) + return 0; + + return DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, + cdclk_state->logical.cdclk); } -static int icl_compute_port_sync_crtc_state(struct drm_connector *connector, - struct intel_crtc_state *crtc_state, - int num_tiled_conns) +static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) { - struct drm_crtc *crtc = crtc_state->uapi.crtc; - struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - struct drm_connector *master_connector; - struct drm_connector_list_iter conn_iter; - struct drm_crtc *master_crtc = NULL; - struct drm_crtc_state *master_crtc_state; - struct intel_crtc_state *master_pipe_config; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + u16 linetime_wm; - if (INTEL_GEN(dev_priv) < 11) + if (!crtc_state->hw.enable) return 0; - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) - return 0; + linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8, + crtc_state->pixel_rate); - /* - * In case of tiled displays there could be one or more slaves but there is - * only one master. Lets make the CRTC used by the connector corresponding - * to the last horizonal and last vertical tile a master/genlock CRTC. - * All the other CRTCs corresponding to other tiles of the same Tile group - * are the slave CRTCs and hold a pointer to their genlock CRTC. - * If all tiles not present do not make master slave assignments. - */ - if (!connector->has_tile || - crtc_state->hw.mode.hdisplay != connector->tile_h_size || - crtc_state->hw.mode.vdisplay != connector->tile_v_size || - num_tiled_conns < connector->num_h_tile * connector->num_v_tile) { - reset_port_sync_mode_state(crtc_state); - return 0; - } - /* Last Horizontal and last vertical tile connector is a master - * Master's crtc state is already populated in slave for port sync - */ - if (connector->tile_h_loc == connector->num_h_tile - 1 && - connector->tile_v_loc == connector->num_v_tile - 1) - return 0; + /* Display WA #1135: BXT:ALL GLK:ALL */ + if (IS_GEN9_LP(dev_priv) && dev_priv->ipc_enabled) + linetime_wm /= 2; - /* Loop through all connectors and configure the Slave crtc_state - * to point to the correct master. - */ - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); - drm_for_each_connector_iter(master_connector, &conn_iter) { - struct drm_connector_state *master_conn_state = NULL; + return linetime_wm; +} - if (!(master_connector->has_tile && - master_connector->tile_group->id == connector->tile_group->id)) - continue; - if (master_connector->tile_h_loc != master_connector->num_h_tile - 1 || - master_connector->tile_v_loc != master_connector->num_v_tile - 1) - continue; +static int hsw_compute_linetime_wm(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_cdclk_state *cdclk_state; - master_conn_state = drm_atomic_get_connector_state(&state->base, - master_connector); - if (IS_ERR(master_conn_state)) { - drm_connector_list_iter_end(&conn_iter); - return PTR_ERR(master_conn_state); - } - if (master_conn_state->crtc) { - master_crtc = master_conn_state->crtc; - break; - } - } - drm_connector_list_iter_end(&conn_iter); + if (INTEL_GEN(dev_priv) >= 9) + crtc_state->linetime = skl_linetime_wm(crtc_state); + else + crtc_state->linetime = hsw_linetime_wm(crtc_state); - if (!master_crtc) { - DRM_DEBUG_KMS("Could not find Master CRTC for Slave CRTC %d\n", - crtc->base.id); - return -EINVAL; - } + if (!hsw_crtc_supports_ips(crtc)) + return 0; - master_crtc_state = drm_atomic_get_crtc_state(&state->base, - master_crtc); - if (IS_ERR(master_crtc_state)) - return PTR_ERR(master_crtc_state); + cdclk_state = intel_atomic_get_cdclk_state(state); + if (IS_ERR(cdclk_state)) + return PTR_ERR(cdclk_state); - master_pipe_config = to_intel_crtc_state(master_crtc_state); - crtc_state->master_transcoder = master_pipe_config->cpu_transcoder; - master_pipe_config->sync_mode_slaves_mask |= - BIT(crtc_state->cpu_transcoder); - DRM_DEBUG_KMS("Master Transcoder = %s added for Slave CRTC = %d, slave transcoder bitmask = %d\n", - transcoder_name(crtc_state->master_transcoder), - crtc->base.id, - master_pipe_config->sync_mode_slaves_mask); + crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, + cdclk_state); return 0; } @@ -12531,7 +12709,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (mode_changed && crtc_state->hw.enable && dev_priv->display.crtc_compute_clock && - !WARN_ON(crtc_state->shared_dpll)) { + !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)) { ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state); if (ret) return ret; @@ -12551,17 +12729,18 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, return ret; } - ret = 0; if (dev_priv->display.compute_pipe_wm) { ret = dev_priv->display.compute_pipe_wm(crtc_state); if (ret) { - DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); + drm_dbg_kms(&dev_priv->drm, + "Target pipe watermarks are invalid\n"); return ret; } } if (dev_priv->display.compute_intermediate_wm) { - if (WARN_ON(!dev_priv->display.compute_pipe_wm)) + if (drm_WARN_ON(&dev_priv->drm, + !dev_priv->display.compute_pipe_wm)) return 0; /* @@ -12571,23 +12750,39 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, */ ret = dev_priv->display.compute_intermediate_wm(crtc_state); if (ret) { - DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); + drm_dbg_kms(&dev_priv->drm, + "No valid intermediate pipe watermarks are possible\n"); return ret; } } if (INTEL_GEN(dev_priv) >= 9) { - if (mode_changed || crtc_state->update_pipe) + if (mode_changed || crtc_state->update_pipe) { ret = skl_update_scaler_crtc(crtc_state); - if (!ret) - ret = intel_atomic_setup_scalers(dev_priv, crtc, - crtc_state); + if (ret) + return ret; + } + + ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); + if (ret) + return ret; } - if (HAS_IPS(dev_priv)) - crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state); + if (HAS_IPS(dev_priv)) { + ret = hsw_compute_ips_config(crtc_state); + if (ret) + return ret; + } - return ret; + if (INTEL_GEN(dev_priv) >= 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { + ret = hsw_compute_linetime_wm(state, crtc); + if (ret) + return ret; + + } + + return 0; } static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) @@ -12620,6 +12815,7 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, struct intel_crtc_state *pipe_config) { struct drm_connector *connector = conn_state->connector; + struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); const struct drm_display_info *info = &connector->display_info; int bpp; @@ -12641,11 +12837,13 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, } if (bpp < pipe_config->pipe_bpp) { - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " - "EDID bpp %d, requested bpp %d, max platform bpp %d\n", - connector->base.id, connector->name, - bpp, 3 * info->bpc, 3 * conn_state->max_requested_bpc, - pipe_config->pipe_bpp); + drm_dbg_kms(&i915->drm, + "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " + "EDID bpp %d, requested bpp %d, max platform bpp %d\n", + connector->base.id, connector->name, + bpp, 3 * info->bpc, + 3 * conn_state->max_requested_bpc, + pipe_config->pipe_bpp); pipe_config->pipe_bpp = bpp; } @@ -12705,10 +12903,13 @@ intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, const char *id, unsigned int lane_count, const struct intel_link_m_n *m_n) { - DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", - id, lane_count, - m_n->gmch_m, m_n->gmch_n, - m_n->link_m, m_n->link_n, m_n->tu); + struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); + + drm_dbg_kms(&i915->drm, + "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", + id, lane_count, + m_n->gmch_m, m_n->gmch_n, + m_n->link_m, m_n->link_n, m_n->tu); } static void @@ -12784,27 +12985,31 @@ static const char *output_formats(enum intel_output_format format) static void intel_dump_plane_state(const struct intel_plane_state *plane_state) { struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); + struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; struct drm_format_name_buf format_name; if (!fb) { - DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [NOFB], visible: %s\n", - plane->base.base.id, plane->base.name, - yesno(plane_state->uapi.visible)); + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] fb: [NOFB], visible: %s\n", + plane->base.base.id, plane->base.name, + yesno(plane_state->uapi.visible)); return; } - DRM_DEBUG_KMS("[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n", - plane->base.base.id, plane->base.name, - fb->base.id, fb->width, fb->height, - drm_get_format_name(fb->format->format, &format_name), - yesno(plane_state->uapi.visible)); - DRM_DEBUG_KMS("\trotation: 0x%x, scaler: %d\n", - plane_state->hw.rotation, plane_state->scaler_id); + drm_dbg_kms(&i915->drm, + "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n", + plane->base.base.id, plane->base.name, + fb->base.id, fb->width, fb->height, + drm_get_format_name(fb->format->format, &format_name), + yesno(plane_state->uapi.visible)); + drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n", + plane_state->hw.rotation, plane_state->scaler_id); if (plane_state->uapi.visible) - DRM_DEBUG_KMS("\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", - DRM_RECT_FP_ARG(&plane_state->uapi.src), - DRM_RECT_ARG(&plane_state->uapi.dst)); + drm_dbg_kms(&i915->drm, + "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n", + DRM_RECT_FP_ARG(&plane_state->uapi.src), + DRM_RECT_ARG(&plane_state->uapi.dst)); } static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, @@ -12818,22 +13023,24 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, char buf[64]; int i; - DRM_DEBUG_KMS("[CRTC:%d:%s] enable: %s %s\n", - crtc->base.base.id, crtc->base.name, - yesno(pipe_config->hw.enable), context); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n", + crtc->base.base.id, crtc->base.name, + yesno(pipe_config->hw.enable), context); if (!pipe_config->hw.enable) goto dump_planes; snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); - DRM_DEBUG_KMS("active: %s, output_types: %s (0x%x), output format: %s\n", - yesno(pipe_config->hw.active), - buf, pipe_config->output_types, - output_formats(pipe_config->output_format)); + drm_dbg_kms(&dev_priv->drm, + "active: %s, output_types: %s (0x%x), output format: %s\n", + yesno(pipe_config->hw.active), + buf, pipe_config->output_types, + output_formats(pipe_config->output_format)); - DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", - transcoder_name(pipe_config->cpu_transcoder), - pipe_config->pipe_bpp, pipe_config->dither); + drm_dbg_kms(&dev_priv->drm, + "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", + transcoder_name(pipe_config->cpu_transcoder), + pipe_config->pipe_bpp, pipe_config->dither); if (pipe_config->has_pch_encoder) intel_dump_m_n_config(pipe_config, "fdi", @@ -12849,13 +13056,15 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, &pipe_config->dp_m2_n2); } - DRM_DEBUG_KMS("audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", - pipe_config->has_audio, pipe_config->has_infoframe, - pipe_config->infoframes.enable); + drm_dbg_kms(&dev_priv->drm, + "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n", + pipe_config->has_audio, pipe_config->has_infoframe, + pipe_config->infoframes.enable); if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) - DRM_DEBUG_KMS("GCP: 0x%x\n", pipe_config->infoframes.gcp); + drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n", + pipe_config->infoframes.gcp); if (pipe_config->infoframes.enable & intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); @@ -12866,50 +13075,59 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); - DRM_DEBUG_KMS("requested mode:\n"); + drm_dbg_kms(&dev_priv->drm, "requested mode:\n"); drm_mode_debug_printmodeline(&pipe_config->hw.mode); - DRM_DEBUG_KMS("adjusted mode:\n"); + drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n"); drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); intel_dump_crtc_timings(&pipe_config->hw.adjusted_mode); - DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", - pipe_config->port_clock, - pipe_config->pipe_src_w, pipe_config->pipe_src_h, - pipe_config->pixel_rate); + drm_dbg_kms(&dev_priv->drm, + "port clock: %d, pipe src size: %dx%d, pixel rate %d\n", + pipe_config->port_clock, + pipe_config->pipe_src_w, pipe_config->pipe_src_h, + pipe_config->pixel_rate); + + drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n", + pipe_config->linetime, pipe_config->ips_linetime); if (INTEL_GEN(dev_priv) >= 9) - DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", - crtc->num_scalers, - pipe_config->scaler_state.scaler_users, - pipe_config->scaler_state.scaler_id); + drm_dbg_kms(&dev_priv->drm, + "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", + crtc->num_scalers, + pipe_config->scaler_state.scaler_users, + pipe_config->scaler_state.scaler_id); if (HAS_GMCH(dev_priv)) - DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", - pipe_config->gmch_pfit.control, - pipe_config->gmch_pfit.pgm_ratios, - pipe_config->gmch_pfit.lvds_border_bits); + drm_dbg_kms(&dev_priv->drm, + "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", + pipe_config->gmch_pfit.control, + pipe_config->gmch_pfit.pgm_ratios, + pipe_config->gmch_pfit.lvds_border_bits); else - DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n", - pipe_config->pch_pfit.pos, - pipe_config->pch_pfit.size, - enableddisabled(pipe_config->pch_pfit.enabled), - yesno(pipe_config->pch_pfit.force_thru)); + drm_dbg_kms(&dev_priv->drm, + "pch pfit: pos: 0x%08x, size: 0x%08x, %s, force thru: %s\n", + pipe_config->pch_pfit.pos, + pipe_config->pch_pfit.size, + enableddisabled(pipe_config->pch_pfit.enabled), + yesno(pipe_config->pch_pfit.force_thru)); - DRM_DEBUG_KMS("ips: %i, double wide: %i\n", - pipe_config->ips_enabled, pipe_config->double_wide); + drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n", + pipe_config->ips_enabled, pipe_config->double_wide); intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); if (IS_CHERRYVIEW(dev_priv)) - DRM_DEBUG_KMS("cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", - pipe_config->cgm_mode, pipe_config->gamma_mode, - pipe_config->gamma_enable, pipe_config->csc_enable); + drm_dbg_kms(&dev_priv->drm, + "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", + pipe_config->cgm_mode, pipe_config->gamma_mode, + pipe_config->gamma_enable, pipe_config->csc_enable); else - DRM_DEBUG_KMS("csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", - pipe_config->csc_mode, pipe_config->gamma_mode, - pipe_config->gamma_enable, pipe_config->csc_enable); + drm_dbg_kms(&dev_priv->drm, + "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n", + pipe_config->csc_mode, pipe_config->gamma_mode, + pipe_config->gamma_enable, pipe_config->csc_enable); - DRM_DEBUG_KMS("MST master transcoder: %s\n", - transcoder_name(pipe_config->mst_master_transcoder)); + drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n", + transcoder_name(pipe_config->mst_master_transcoder)); dump_planes: if (!state) @@ -12957,24 +13175,21 @@ static bool check_digital_port_conflicts(struct intel_atomic_state *state) encoder = to_intel_encoder(connector_state->best_encoder); - WARN_ON(!connector_state->crtc); + drm_WARN_ON(dev, !connector_state->crtc); switch (encoder->type) { - unsigned int port_mask; case INTEL_OUTPUT_DDI: - if (WARN_ON(!HAS_DDI(to_i915(dev)))) + if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))) break; /* else, fall through */ case INTEL_OUTPUT_DP: case INTEL_OUTPUT_HDMI: case INTEL_OUTPUT_EDP: - port_mask = 1 << encoder->port; - /* the same port mustn't appear more than once */ - if (used_ports & port_mask) + if (used_ports & BIT(encoder->port)) ret = false; - used_ports |= port_mask; + used_ports |= BIT(encoder->port); break; case INTEL_OUTPUT_DP_MST: used_mst_ports |= @@ -13055,15 +13270,6 @@ intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state) if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) saved_state->wm = crtc_state->wm; - /* - * Save the slave bitmask which gets filled for master crtc state during - * slave atomic check call. For all other CRTCs reset the port sync variables - * crtc_state->master_transcoder needs to be set to INVALID - */ - reset_port_sync_mode_state(saved_state); - if (intel_atomic_is_master_connector(crtc_state)) - saved_state->sync_mode_slaves_mask = - crtc_state->sync_mode_slaves_mask; memcpy(crtc_state, saved_state, sizeof(*crtc_state)); kfree(saved_state); @@ -13078,11 +13284,10 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config) { struct drm_crtc *crtc = pipe_config->uapi.crtc; struct drm_atomic_state *state = pipe_config->uapi.state; - struct intel_encoder *encoder; + struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev); struct drm_connector *connector; struct drm_connector_state *connector_state; - int base_bpp, ret; - int i, tile_group_id = -1, num_tiled_conns = 0; + int base_bpp, ret, i; bool retry = true; pipe_config->cpu_transcoder = @@ -13121,13 +13326,15 @@ intel_modeset_pipe_config(struct intel_crtc_state *pipe_config) &pipe_config->pipe_src_h); for_each_new_connector_in_state(state, connector, connector_state, i) { + struct intel_encoder *encoder = + to_intel_encoder(connector_state->best_encoder); + if (connector_state->crtc != crtc) continue; - encoder = to_intel_encoder(connector_state->best_encoder); - if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { - DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); + drm_dbg_kms(&i915->drm, + "rejecting invalid cloning configuration\n"); return -EINVAL; } @@ -13152,47 +13359,24 @@ encoder_retry: drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, CRTC_STEREO_DOUBLE); - /* Get tile_group_id of tiled connector */ - for_each_new_connector_in_state(state, connector, connector_state, i) { - if (connector_state->crtc == crtc && - connector->has_tile) { - tile_group_id = connector->tile_group->id; - break; - } - } - - /* Get total number of tiled connectors in state that belong to - * this tile group. - */ - for_each_new_connector_in_state(state, connector, connector_state, i) { - if (connector->has_tile && - connector->tile_group->id == tile_group_id) - num_tiled_conns++; - } - /* Pass our mode to the connectors and the CRTC to give them a chance to * adjust it according to limitations or connector properties, and also * a chance to reject the mode entirely. */ for_each_new_connector_in_state(state, connector, connector_state, i) { + struct intel_encoder *encoder = + to_intel_encoder(connector_state->best_encoder); + if (connector_state->crtc != crtc) continue; - ret = icl_compute_port_sync_crtc_state(connector, pipe_config, - num_tiled_conns); - if (ret) { - DRM_DEBUG_KMS("Cannot assign Sync Mode CRTCs: %d\n", - ret); - return ret; - } - - encoder = to_intel_encoder(connector_state->best_encoder); ret = encoder->compute_config(encoder, pipe_config, connector_state); if (ret < 0) { if (ret != -EDEADLK) - DRM_DEBUG_KMS("Encoder config failure: %d\n", - ret); + drm_dbg_kms(&i915->drm, + "Encoder config failure: %d\n", + ret); return ret; } } @@ -13207,15 +13391,16 @@ encoder_retry: if (ret == -EDEADLK) return ret; if (ret < 0) { - DRM_DEBUG_KMS("CRTC fixup failed\n"); + drm_dbg_kms(&i915->drm, "CRTC fixup failed\n"); return ret; } if (ret == RETRY) { - if (WARN(!retry, "loop in pipe configuration computation\n")) + if (drm_WARN(&i915->drm, !retry, + "loop in pipe configuration computation\n")) return -EINVAL; - DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); + drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n"); retry = false; goto encoder_retry; } @@ -13226,8 +13411,9 @@ encoder_retry: */ pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && !pipe_config->dither_force_disable; - DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", - base_bpp, pipe_config->pipe_bpp, pipe_config->dither); + drm_dbg_kms(&i915->drm, + "hw max bpp: %i, pipe bpp: %i, dithering: %i\n", + base_bpp, pipe_config->pipe_bpp, pipe_config->dither); /* * Make drm_calc_timestamping_constants in @@ -13238,6 +13424,35 @@ encoder_retry: return 0; } +static int +intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) +{ + struct intel_atomic_state *state = + to_intel_atomic_state(crtc_state->uapi.state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_connector_state *conn_state; + struct drm_connector *connector; + int i; + + for_each_new_connector_in_state(&state->base, connector, + conn_state, i) { + struct intel_encoder *encoder = + to_intel_encoder(conn_state->best_encoder); + int ret; + + if (conn_state->crtc != &crtc->base || + !encoder->compute_config_late) + continue; + + ret = encoder->compute_config_late(encoder, crtc_state, + conn_state); + if (ret) + return ret; + } + + return 0; +} + bool intel_fuzzy_clock_check(int clock1, int clock2) { int diff; @@ -13316,16 +13531,17 @@ pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv, if (!drm_debug_enabled(DRM_UT_KMS)) return; - DRM_DEBUG_KMS("fastset mismatch in %s infoframe\n", name); - DRM_DEBUG_KMS("expected:\n"); + drm_dbg_kms(&dev_priv->drm, + "fastset mismatch in %s infoframe\n", name); + drm_dbg_kms(&dev_priv->drm, "expected:\n"); hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a); - DRM_DEBUG_KMS("found:\n"); + drm_dbg_kms(&dev_priv->drm, "found:\n"); hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b); } else { - DRM_ERROR("mismatch in %s infoframe\n", name); - DRM_ERROR("expected:\n"); + drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name); + drm_err(&dev_priv->drm, "expected:\n"); hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a); - DRM_ERROR("found:\n"); + drm_err(&dev_priv->drm, "found:\n"); hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b); } } @@ -13334,6 +13550,7 @@ static void __printf(4, 5) pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, const char *name, const char *format, ...) { + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct va_format vaf; va_list args; @@ -13342,11 +13559,12 @@ pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc, vaf.va = &args; if (fastset) - DRM_DEBUG_KMS("[CRTC:%d:%s] fastset mismatch in %s %pV\n", - crtc->base.base.id, crtc->base.name, name, &vaf); + drm_dbg_kms(&i915->drm, + "[CRTC:%d:%s] fastset mismatch in %s %pV\n", + crtc->base.base.id, crtc->base.name, name, &vaf); else - DRM_ERROR("[CRTC:%d:%s] mismatch in %s %pV\n", - crtc->base.base.id, crtc->base.name, name, &vaf); + drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n", + crtc->base.base.id, crtc->base.name, name, &vaf); va_end(args); } @@ -13382,7 +13600,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, !(pipe_config->hw.mode.private_flags & I915_MODE_FLAG_INHERITED); if (fixup_inherited && !fastboot_enabled(dev_priv)) { - DRM_DEBUG_KMS("initial modeset and fastboot not set\n"); + drm_dbg_kms(&dev_priv->drm, + "initial modeset and fastboot not set\n"); ret = false; } @@ -13584,7 +13803,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(pixel_multiplier); PIPE_CONF_CHECK_I(output_format); - PIPE_CONF_CHECK_I(dc3co_exitline); PIPE_CONF_CHECK_BOOL(has_hdmi_sink); if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) @@ -13644,10 +13862,12 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_BOOL(gamma_enable); PIPE_CONF_CHECK_BOOL(csc_enable); + PIPE_CONF_CHECK_I(linetime); + PIPE_CONF_CHECK_I(ips_linetime); + bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); if (bp_gamma) PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); - } PIPE_CONF_CHECK_BOOL(double_wide); @@ -13703,7 +13923,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_INFOFRAME(hdmi); PIPE_CONF_CHECK_INFOFRAME(drm); - PIPE_CONF_CHECK_I(sync_mode_slaves_mask); + PIPE_CONF_CHECK_X(sync_mode_slaves_mask); PIPE_CONF_CHECK_I(master_transcoder); PIPE_CONF_CHECK_I(dsc.compression_enable); @@ -13737,9 +13957,10 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, * FDI already provided one idea for the dotclock. * Yell if the encoder disagrees. */ - WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), - "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", - fdi_dotclock, dotclock); + drm_WARN(&dev_priv->drm, + !intel_fuzzy_clock_check(fdi_dotclock, dotclock), + "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", + fdi_dotclock, dotclock); } } @@ -13750,12 +13971,11 @@ static void verify_wm_state(struct intel_crtc *crtc, struct skl_hw_state { struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; struct skl_ddb_entry ddb_uv[I915_MAX_PLANES]; - struct skl_ddb_allocation ddb; struct skl_pipe_wm wm; } *hw; - struct skl_ddb_allocation *sw_ddb; struct skl_pipe_wm *sw_wm; struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; + u8 hw_enabled_slices; const enum pipe pipe = crtc->pipe; int plane, level, max_level = ilk_wm_max_level(dev_priv); @@ -13771,14 +13991,14 @@ static void verify_wm_state(struct intel_crtc *crtc, skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); - skl_ddb_get_hw_state(dev_priv, &hw->ddb); - sw_ddb = &dev_priv->wm.skl_hw.ddb; + hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); if (INTEL_GEN(dev_priv) >= 11 && - hw->ddb.enabled_slices != sw_ddb->enabled_slices) - DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n", - sw_ddb->enabled_slices, - hw->ddb.enabled_slices); + hw_enabled_slices != dev_priv->enabled_dbuf_slices_mask) + drm_err(&dev_priv->drm, + "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n", + dev_priv->enabled_dbuf_slices_mask, + hw_enabled_slices); /* planes */ for_each_universal_plane(dev_priv, pipe, plane) { @@ -13793,26 +14013,28 @@ static void verify_wm_state(struct intel_crtc *crtc, &sw_plane_wm->wm[level])) continue; - DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - pipe_name(pipe), plane + 1, level, - sw_plane_wm->wm[level].plane_en, - sw_plane_wm->wm[level].plane_res_b, - sw_plane_wm->wm[level].plane_res_l, - hw_plane_wm->wm[level].plane_en, - hw_plane_wm->wm[level].plane_res_b, - hw_plane_wm->wm[level].plane_res_l); + drm_err(&dev_priv->drm, + "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", + pipe_name(pipe), plane + 1, level, + sw_plane_wm->wm[level].plane_en, + sw_plane_wm->wm[level].plane_res_b, + sw_plane_wm->wm[level].plane_res_l, + hw_plane_wm->wm[level].plane_en, + hw_plane_wm->wm[level].plane_res_b, + hw_plane_wm->wm[level].plane_res_l); } if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, &sw_plane_wm->trans_wm)) { - DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - pipe_name(pipe), plane + 1, - sw_plane_wm->trans_wm.plane_en, - sw_plane_wm->trans_wm.plane_res_b, - sw_plane_wm->trans_wm.plane_res_l, - hw_plane_wm->trans_wm.plane_en, - hw_plane_wm->trans_wm.plane_res_b, - hw_plane_wm->trans_wm.plane_res_l); + drm_err(&dev_priv->drm, + "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", + pipe_name(pipe), plane + 1, + sw_plane_wm->trans_wm.plane_en, + sw_plane_wm->trans_wm.plane_res_b, + sw_plane_wm->trans_wm.plane_res_l, + hw_plane_wm->trans_wm.plane_en, + hw_plane_wm->trans_wm.plane_res_b, + hw_plane_wm->trans_wm.plane_res_l); } /* DDB */ @@ -13820,10 +14042,11 @@ static void verify_wm_state(struct intel_crtc *crtc, sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane]; if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { - DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", - pipe_name(pipe), plane + 1, - sw_ddb_entry->start, sw_ddb_entry->end, - hw_ddb_entry->start, hw_ddb_entry->end); + drm_err(&dev_priv->drm, + "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", + pipe_name(pipe), plane + 1, + sw_ddb_entry->start, sw_ddb_entry->end, + hw_ddb_entry->start, hw_ddb_entry->end); } } @@ -13845,26 +14068,28 @@ static void verify_wm_state(struct intel_crtc *crtc, &sw_plane_wm->wm[level])) continue; - DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - pipe_name(pipe), level, - sw_plane_wm->wm[level].plane_en, - sw_plane_wm->wm[level].plane_res_b, - sw_plane_wm->wm[level].plane_res_l, - hw_plane_wm->wm[level].plane_en, - hw_plane_wm->wm[level].plane_res_b, - hw_plane_wm->wm[level].plane_res_l); + drm_err(&dev_priv->drm, + "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", + pipe_name(pipe), level, + sw_plane_wm->wm[level].plane_en, + sw_plane_wm->wm[level].plane_res_b, + sw_plane_wm->wm[level].plane_res_l, + hw_plane_wm->wm[level].plane_en, + hw_plane_wm->wm[level].plane_res_b, + hw_plane_wm->wm[level].plane_res_l); } if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, &sw_plane_wm->trans_wm)) { - DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", - pipe_name(pipe), - sw_plane_wm->trans_wm.plane_en, - sw_plane_wm->trans_wm.plane_res_b, - sw_plane_wm->trans_wm.plane_res_l, - hw_plane_wm->trans_wm.plane_en, - hw_plane_wm->trans_wm.plane_res_b, - hw_plane_wm->trans_wm.plane_res_l); + drm_err(&dev_priv->drm, + "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", + pipe_name(pipe), + sw_plane_wm->trans_wm.plane_en, + sw_plane_wm->trans_wm.plane_res_b, + sw_plane_wm->trans_wm.plane_res_l, + hw_plane_wm->trans_wm.plane_en, + hw_plane_wm->trans_wm.plane_res_b, + hw_plane_wm->trans_wm.plane_res_l); } /* DDB */ @@ -13872,10 +14097,11 @@ static void verify_wm_state(struct intel_crtc *crtc, sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { - DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", - pipe_name(pipe), - sw_ddb_entry->start, sw_ddb_entry->end, - hw_ddb_entry->start, hw_ddb_entry->end); + drm_err(&dev_priv->drm, + "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", + pipe_name(pipe), + sw_ddb_entry->start, sw_ddb_entry->end, + hw_ddb_entry->start, hw_ddb_entry->end); } } @@ -13919,9 +14145,9 @@ verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_stat bool enabled = false, found = false; enum pipe pipe; - DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", - encoder->base.base.id, - encoder->base.name); + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n", + encoder->base.base.id, + encoder->base.name); for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state, new_conn_state, i) { @@ -13973,7 +14199,8 @@ verify_crtc_state(struct intel_crtc *crtc, intel_crtc_state_reset(old_crtc_state, crtc); old_crtc_state->uapi.state = state; - DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.base.id, crtc->base.name); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id, + crtc->base.name); active = dev_priv->display.get_pipe_config(crtc, pipe_config); @@ -14048,7 +14275,7 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); - DRM_DEBUG_KMS("%s\n", pll->info->name); + drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name); active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); @@ -14075,11 +14302,11 @@ verify_single_dpll_state(struct drm_i915_private *dev_priv, if (new_crtc_state->hw.active) I915_STATE_WARN(!(pll->active_mask & crtc_mask), "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", - pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); + pipe_name(crtc->pipe), pll->active_mask); else I915_STATE_WARN(pll->active_mask & crtc_mask, "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", - pipe_name(drm_crtc_index(&crtc->base)), pll->active_mask); + pipe_name(crtc->pipe), pll->active_mask); I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", @@ -14108,10 +14335,10 @@ verify_shared_dpll_state(struct intel_crtc *crtc, I915_STATE_WARN(pll->active_mask & crtc_mask, "pll active mismatch (didn't expect pipe %c in active mask)\n", - pipe_name(drm_crtc_index(&crtc->base))); + pipe_name(crtc->pipe)); I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, "pll enabled crtcs mismatch (found %x in enabled mask)\n", - pipe_name(drm_crtc_index(&crtc->base))); + pipe_name(crtc->pipe)); } } @@ -14135,8 +14362,10 @@ verify_disabled_dpll_state(struct drm_i915_private *dev_priv) { int i; - for (i = 0; i < dev_priv->num_shared_dpll; i++) - verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); + for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) + verify_single_dpll_state(dev_priv, + &dev_priv->dpll.shared_dplls[i], + NULL, NULL); } static void @@ -14280,35 +14509,35 @@ static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) return 0; } -static int intel_modeset_checks(struct intel_atomic_state *state) +u8 intel_calc_active_pipes(struct intel_atomic_state *state, + u8 active_pipes) { - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct intel_crtc_state *old_crtc_state, *new_crtc_state; + const struct intel_crtc_state *crtc_state; struct intel_crtc *crtc; - int ret, i; + int i; - /* keep the current setting */ - if (!state->cdclk.force_min_cdclk_changed) - state->cdclk.force_min_cdclk = dev_priv->cdclk.force_min_cdclk; + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { + if (crtc_state->hw.active) + active_pipes |= BIT(crtc->pipe); + else + active_pipes &= ~BIT(crtc->pipe); + } - state->modeset = true; - state->active_pipes = dev_priv->active_pipes; - state->cdclk.logical = dev_priv->cdclk.logical; - state->cdclk.actual = dev_priv->cdclk.actual; + return active_pipes; +} - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { - if (new_crtc_state->hw.active) - state->active_pipes |= BIT(crtc->pipe); - else - state->active_pipes &= ~BIT(crtc->pipe); +static int intel_modeset_checks(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + int ret; - if (old_crtc_state->hw.active != new_crtc_state->hw.active) - state->active_pipe_changes |= BIT(crtc->pipe); - } + state->modeset = true; + state->active_pipes = intel_calc_active_pipes(state, dev_priv->active_pipes); + + state->active_pipe_changes = state->active_pipes ^ dev_priv->active_pipes; if (state->active_pipe_changes) { - ret = intel_atomic_lock_global_state(state); + ret = _intel_atomic_lock_global_state(state); if (ret) return ret; } @@ -14399,7 +14628,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) } static int intel_atomic_check_planes(struct intel_atomic_state *state, - bool *need_modeset) + bool *need_cdclk_calc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc_state *old_crtc_state, *new_crtc_state; @@ -14415,8 +14644,9 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state, for_each_new_intel_plane_in_state(state, plane, plane_state, i) { ret = intel_plane_atomic_check(state, plane); if (ret) { - DRM_DEBUG_ATOMIC("[PLANE:%d:%s] atomic driver check failed\n", - plane->base.base.id, plane->base.name); + drm_dbg_atomic(&dev_priv->drm, + "[PLANE:%d:%s] atomic driver check failed\n", + plane->base.base.id, plane->base.name); return ret; } } @@ -14453,8 +14683,11 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state, * affected planes are part of the state. We can now * compute the minimum cdclk for each plane. */ - for_each_new_intel_plane_in_state(state, plane, plane_state, i) - *need_modeset |= intel_plane_calc_min_cdclk(state, plane); + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); + if (ret) + return ret; + } return 0; } @@ -14467,9 +14700,11 @@ static int intel_atomic_check_crtcs(struct intel_atomic_state *state) for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret = intel_crtc_atomic_check(state, crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); if (ret) { - DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n", - crtc->base.base.id, crtc->base.name); + drm_dbg_atomic(&i915->drm, + "[CRTC:%d:%s] atomic driver check failed\n", + crtc->base.base.id, crtc->base.name); return ret; } } @@ -14494,76 +14729,6 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, return false; } -static int -intel_modeset_all_tiles(struct intel_atomic_state *state, int tile_grp_id) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct drm_connector *connector; - struct drm_connector_list_iter conn_iter; - int ret = 0; - - drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { - struct drm_connector_state *conn_state; - struct drm_crtc_state *crtc_state; - - if (!connector->has_tile || - connector->tile_group->id != tile_grp_id) - continue; - conn_state = drm_atomic_get_connector_state(&state->base, - connector); - if (IS_ERR(conn_state)) { - ret = PTR_ERR(conn_state); - break; - } - - if (!conn_state->crtc) - continue; - - crtc_state = drm_atomic_get_crtc_state(&state->base, - conn_state->crtc); - if (IS_ERR(crtc_state)) { - ret = PTR_ERR(crtc_state); - break; - } - crtc_state->mode_changed = true; - ret = drm_atomic_add_affected_connectors(&state->base, - conn_state->crtc); - if (ret) - break; - } - drm_connector_list_iter_end(&conn_iter); - - return ret; -} - -static int -intel_atomic_check_tiled_conns(struct intel_atomic_state *state) -{ - struct drm_i915_private *dev_priv = to_i915(state->base.dev); - struct drm_connector *connector; - struct drm_connector_state *old_conn_state, *new_conn_state; - int i, ret; - - if (INTEL_GEN(dev_priv) < 11) - return 0; - - /* Is tiled, mark all other tiled CRTCs as needing a modeset */ - for_each_oldnew_connector_in_state(&state->base, connector, - old_conn_state, new_conn_state, i) { - if (!connector->has_tile) - continue; - if (!intel_connector_needs_modeset(state, connector)) - continue; - - ret = intel_modeset_all_tiles(state, connector->tile_group->id); - if (ret) - return ret; - } - - return 0; -} - /** * intel_atomic_check - validate state object * @dev: drm device @@ -14575,6 +14740,7 @@ static int intel_atomic_check(struct drm_device *dev, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_atomic_state *state = to_intel_atomic_state(_state); struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_cdclk_state *new_cdclk_state; struct intel_crtc *crtc; int ret, i; bool any_ms = false; @@ -14582,8 +14748,8 @@ static int intel_atomic_check(struct drm_device *dev, /* Catch I915_MODE_FLAG_INHERITED */ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { - if (new_crtc_state->hw.mode.private_flags != - old_crtc_state->hw.mode.private_flags) + if (new_crtc_state->uapi.mode.private_flags != + old_crtc_state->uapi.mode.private_flags) new_crtc_state->uapi.mode_changed = true; } @@ -14591,21 +14757,6 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; - /** - * This check adds all the connectors in current state that belong to - * the same tile group to a full modeset. - * This function directly sets the mode_changed to true and we also call - * drm_atomic_add_affected_connectors(). Hence we are not explicitly - * calling drm_atomic_helper_check_modeset() after this. - * - * Fixme: Handle some corner cases where one of the - * tiled connectors gets disconnected and tile info is lost but since it - * was previously synced to other conn, we need to add that to the modeset. - */ - ret = intel_atomic_check_tiled_conns(state); - if (ret) - goto fail; - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (!needs_modeset(new_crtc_state)) { @@ -14615,18 +14766,26 @@ static int intel_atomic_check(struct drm_device *dev, continue; } - if (!new_crtc_state->uapi.enable) { - intel_crtc_copy_uapi_to_hw_state(new_crtc_state); - continue; - } - ret = intel_crtc_prepare_cleared_state(new_crtc_state); if (ret) goto fail; + if (!new_crtc_state->hw.enable) + continue; + ret = intel_modeset_pipe_config(new_crtc_state); if (ret) goto fail; + } + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (!needs_modeset(new_crtc_state)) + continue; + + ret = intel_modeset_pipe_config_late(new_crtc_state); + if (ret) + goto fail; intel_crtc_check_fastset(old_crtc_state, new_crtc_state); } @@ -14656,8 +14815,10 @@ static int intel_atomic_check(struct drm_device *dev, } if (is_trans_port_sync_mode(new_crtc_state)) { - u8 trans = new_crtc_state->sync_mode_slaves_mask | - BIT(new_crtc_state->master_transcoder); + u8 trans = new_crtc_state->sync_mode_slaves_mask; + + if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) + trans |= BIT(new_crtc_state->master_transcoder); if (intel_cpu_transcoders_need_modeset(state, trans)) { new_crtc_state->uapi.mode_changed = true; @@ -14680,7 +14841,8 @@ static int intel_atomic_check(struct drm_device *dev, } if (any_ms && !check_digital_port_conflicts(state)) { - DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); + drm_dbg_kms(&dev_priv->drm, + "rejecting conflicting digital port configuration\n"); ret = EINVAL; goto fail; } @@ -14689,18 +14851,32 @@ static int intel_atomic_check(struct drm_device *dev, if (ret) goto fail; - any_ms |= state->cdclk.force_min_cdclk_changed; - ret = intel_atomic_check_planes(state, &any_ms); if (ret) goto fail; + new_cdclk_state = intel_atomic_get_new_cdclk_state(state); + if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed) + any_ms = true; + + /* + * distrust_bios_wm will force a full dbuf recomputation + * but the hardware state will only get updated accordingly + * if state->modeset==true. Hence distrust_bios_wm==true && + * state->modeset==false is an invalid combination which + * would cause the hardware and software dbuf state to get + * out of sync. We must prevent that. + * + * FIXME clean up this mess and introduce better + * state tracking for dbuf. + */ + if (dev_priv->wm.distrust_bios_wm) + any_ms = true; + if (any_ms) { ret = intel_modeset_checks(state); if (ret) goto fail; - } else { - state->cdclk.logical = dev_priv->cdclk.logical; } ret = intel_atomic_check_crtcs(state); @@ -14806,6 +14982,18 @@ static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, ilk_pfit_disable(old_crtc_state); } + /* + * The register is supposedly single buffered so perhaps + * not 100% correct to do this here. But SKL+ calculate + * this based on the adjust pixel rate so pfit changes do + * affect it and so it must be updated for fastsets. + * HSW/BDW only really need this here for fastboot, after + * that the value should not change without a full modeset. + */ + if (INTEL_GEN(dev_priv) >= 9 || + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) + hsw_set_linetime_wm(new_crtc_state); + if (INTEL_GEN(dev_priv) >= 11) icl_set_pipe_chicken(crtc); } @@ -14848,9 +15036,6 @@ static void intel_update_crtc(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(state->base.dev); bool modeset = needs_modeset(new_crtc_state); - struct intel_plane_state *new_plane_state = - intel_atomic_get_new_plane_state(state, - to_intel_plane(crtc->base.primary)); if (modeset) { intel_crtc_update_active_timings(new_crtc_state); @@ -14873,8 +15058,8 @@ static void intel_update_crtc(struct intel_crtc *crtc, if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc) intel_fbc_disable(crtc); - else if (new_plane_state) - intel_fbc_enable(crtc, new_crtc_state, new_plane_state); + else + intel_fbc_enable(state, crtc); /* Perform vblank evasion around commit operation */ intel_pipe_update_start(new_crtc_state); @@ -14904,7 +15089,8 @@ static struct intel_crtc *intel_get_slave_crtc(const struct intel_crtc_state *ne struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); enum transcoder slave_transcoder; - WARN_ON(!is_power_of_2(new_crtc_state->sync_mode_slaves_mask)); + drm_WARN_ON(&dev_priv->drm, + !is_power_of_2(new_crtc_state->sync_mode_slaves_mask)); slave_transcoder = ffs(new_crtc_state->sync_mode_slaves_mask) - 1; return intel_get_crtc_for_pipe(dev_priv, @@ -15021,7 +15207,7 @@ static void intel_set_dp_tp_ctl_normal(struct intel_crtc *crtc, if (conn_state->crtc == &crtc->base) break; } - intel_dp = enc_to_intel_dp(intel_attached_encoder(to_intel_connector(conn))); + intel_dp = intel_attached_dp(to_intel_connector(conn)); intel_dp_stop_link_train(intel_dp); } @@ -15036,15 +15222,12 @@ static void intel_post_crtc_enable_updates(struct intel_crtc *crtc, intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); - struct intel_plane_state *new_plane_state = - intel_atomic_get_new_plane_state(state, - to_intel_plane(crtc->base.primary)); bool modeset = needs_modeset(new_crtc_state); if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc) intel_fbc_disable(crtc); - else if (new_plane_state) - intel_fbc_enable(crtc, new_crtc_state, new_plane_state); + else + intel_fbc_enable(state, crtc); /* Perform vblank evasion around commit operation */ intel_pipe_update_start(new_crtc_state); @@ -15068,18 +15251,20 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc, struct intel_crtc_state *old_crtc_state, struct intel_crtc_state *new_crtc_state) { + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_crtc *slave_crtc = intel_get_slave_crtc(new_crtc_state); struct intel_crtc_state *new_slave_crtc_state = intel_atomic_get_new_crtc_state(state, slave_crtc); struct intel_crtc_state *old_slave_crtc_state = intel_atomic_get_old_crtc_state(state, slave_crtc); - WARN_ON(!slave_crtc || !new_slave_crtc_state || - !old_slave_crtc_state); + drm_WARN_ON(&i915->drm, !slave_crtc || !new_slave_crtc_state || + !old_slave_crtc_state); - DRM_DEBUG_KMS("Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n", - crtc->base.base.id, crtc->base.name, slave_crtc->base.base.id, - slave_crtc->base.name); + drm_dbg_kms(&i915->drm, + "Updating Transcoder Port Sync Master CRTC = %d %s and Slave CRTC %d %s\n", + crtc->base.base.id, crtc->base.name, + slave_crtc->base.base.id, slave_crtc->base.name); /* Enable seq for slave with with DP_TP_CTL left Idle until the * master is ready @@ -15109,35 +15294,53 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc, state); } +static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask; + u8 required_slices = state->enabled_dbuf_slices_mask; + u8 slices_union = hw_enabled_slices | required_slices; + + /* If 2nd DBuf slice required, enable it here */ + if (INTEL_GEN(dev_priv) >= 11 && slices_union != hw_enabled_slices) + icl_dbuf_slices_update(dev_priv, slices_union); +} + +static void icl_dbuf_slice_post_update(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + u8 hw_enabled_slices = dev_priv->enabled_dbuf_slices_mask; + u8 required_slices = state->enabled_dbuf_slices_mask; + + /* If 2nd DBuf slice is no more required disable it */ + if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices) + icl_dbuf_slices_update(dev_priv, required_slices); +} + static void skl_commit_modeset_enables(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); struct intel_crtc *crtc; struct intel_crtc_state *old_crtc_state, *new_crtc_state; - u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; - u8 required_slices = state->wm_results.ddb.enabled_slices; struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; - const u8 num_pipes = INTEL_NUM_PIPES(dev_priv); u8 update_pipes = 0, modeset_pipes = 0; int i; for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + enum pipe pipe = crtc->pipe; + if (!new_crtc_state->hw.active) continue; /* ignore allocations for crtc's that have been turned off. */ if (!needs_modeset(new_crtc_state)) { - entries[i] = old_crtc_state->wm.skl.ddb; - update_pipes |= BIT(crtc->pipe); + entries[pipe] = old_crtc_state->wm.skl.ddb; + update_pipes |= BIT(pipe); } else { - modeset_pipes |= BIT(crtc->pipe); + modeset_pipes |= BIT(pipe); } } - /* If 2nd DBuf slice required, enable it here */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) - icl_dbuf_slices_update(dev_priv, required_slices); - /* * Whenever the number of active pipes changes, we need to make sure we * update the pipes in the right order so that their ddb allocations @@ -15156,10 +15359,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) continue; if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, num_pipes, i)) + entries, I915_MAX_PIPES, pipe)) continue; - entries[i] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_crtc_state->wm.skl.ddb; update_pipes &= ~BIT(pipe); intel_update_crtc(crtc, state, old_crtc_state, @@ -15193,10 +15396,10 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) is_trans_port_sync_slave(new_crtc_state)) continue; - WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, num_pipes, i)); + drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + entries, I915_MAX_PIPES, pipe)); - entries[i] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_crtc_state->wm.skl.ddb; modeset_pipes &= ~BIT(pipe); if (is_trans_port_sync_mode(new_crtc_state)) { @@ -15228,20 +15431,17 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - WARN_ON(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, - entries, num_pipes, i)); + drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, + entries, I915_MAX_PIPES, pipe)); - entries[i] = new_crtc_state->wm.skl.ddb; + entries[pipe] = new_crtc_state->wm.skl.ddb; modeset_pipes &= ~BIT(pipe); intel_update_crtc(crtc, state, old_crtc_state, new_crtc_state); } - WARN_ON(modeset_pipes); + drm_WARN_ON(&dev_priv->drm, modeset_pipes); - /* If 2nd DBuf slice is no more required disable it */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) - icl_dbuf_slices_update(dev_priv, required_slices); } static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) @@ -15338,10 +15538,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) { drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); - intel_set_cdclk_pre_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_pre_plane_update(state); /* * SKL workaround: bspec recommends we disable the SAGV when we @@ -15371,16 +15568,17 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) if (state->modeset) intel_encoders_update_prepare(state); + /* Enable all new slices, we might need */ + if (state->modeset) + icl_dbuf_slice_pre_update(state); + /* Now enable the clocks, plane, pipe, and connectors that we set up. */ dev_priv->display.commit_modeset_enables(state); if (state->modeset) { intel_encoders_update_complete(state); - intel_set_cdclk_post_plane_update(dev_priv, - &state->cdclk.actual, - &dev_priv->cdclk.actual, - state->cdclk.pipe); + intel_set_cdclk_post_plane_update(state); } /* FIXME: We should call drm_atomic_helper_commit_hw_done() here @@ -15427,6 +15625,10 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) dev_priv->display.optimize_watermarks(state, crtc); } + /* Disable all slices, we don't need */ + if (state->modeset) + icl_dbuf_slice_post_update(state); + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { intel_post_plane_update(state, crtc); @@ -15570,7 +15772,8 @@ static int intel_atomic_commit(struct drm_device *dev, ret = intel_atomic_prepare_commit(state); if (ret) { - DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); + drm_dbg_atomic(&dev_priv->drm, + "Preparing state failed with %i\n", ret); i915_sw_fence_commit(&state->commit_ready); intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); return ret; @@ -15579,6 +15782,8 @@ static int intel_atomic_commit(struct drm_device *dev, ret = drm_atomic_helper_setup_commit(&state->base, nonblock); if (!ret) ret = drm_atomic_helper_swap_state(&state->base, true); + if (!ret) + intel_atomic_swap_global_state(state); if (ret) { i915_sw_fence_commit(&state->commit_ready); @@ -15594,14 +15799,7 @@ static int intel_atomic_commit(struct drm_device *dev, if (state->global_state_changed) { assert_global_state_locked(dev_priv); - memcpy(dev_priv->min_cdclk, state->min_cdclk, - sizeof(state->min_cdclk)); - memcpy(dev_priv->min_voltage_level, state->min_voltage_level, - sizeof(state->min_voltage_level)); dev_priv->active_pipes = state->active_pipes; - dev_priv->cdclk.force_min_cdclk = state->cdclk.force_min_cdclk; - - intel_cdclk_swap_state(state); } drm_atomic_state_get(&state->base); @@ -15729,7 +15927,7 @@ static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj) /** * intel_prepare_plane_fb - Prepare fb for usage on plane - * @plane: drm plane to prepare for + * @_plane: drm plane to prepare for * @_new_plane_state: the plane state being prepared * * Prepares a framebuffer for usage on a display plane. Generally this @@ -15740,23 +15938,25 @@ static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj) * Returns 0 on success, negative error code on failure. */ int -intel_prepare_plane_fb(struct drm_plane *plane, +intel_prepare_plane_fb(struct drm_plane *_plane, struct drm_plane_state *_new_plane_state) { + struct intel_plane *plane = to_intel_plane(_plane); struct intel_plane_state *new_plane_state = to_intel_plane_state(_new_plane_state); - struct intel_atomic_state *intel_state = + struct intel_atomic_state *state = to_intel_atomic_state(new_plane_state->uapi.state); - struct drm_i915_private *dev_priv = to_i915(plane->dev); - struct drm_framebuffer *fb = new_plane_state->hw.fb; - struct drm_i915_gem_object *obj = intel_fb_obj(fb); - struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + const struct intel_plane_state *old_plane_state = + intel_atomic_get_old_plane_state(state, plane); + struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb); + struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb); int ret; if (old_obj) { - struct intel_crtc_state *crtc_state = - intel_atomic_get_new_crtc_state(intel_state, - to_intel_crtc(plane->state->crtc)); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, + to_intel_crtc(old_plane_state->hw.crtc)); /* Big Hammer, we also need to ensure that any pending * MI_WAIT_FOR_EVENT inside a user batch buffer on the @@ -15770,7 +15970,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, * can safely continue. */ if (needs_modeset(crtc_state)) { - ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, + ret = i915_sw_fence_await_reservation(&state->commit_ready, old_obj->base.resv, NULL, false, 0, GFP_KERNEL); @@ -15780,7 +15980,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, } if (new_plane_state->uapi.fence) { /* explicit fencing */ - ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, + ret = i915_sw_fence_await_dma_fence(&state->commit_ready, new_plane_state->uapi.fence, I915_FENCE_TIMEOUT, GFP_KERNEL); @@ -15807,12 +16007,12 @@ intel_prepare_plane_fb(struct drm_plane *plane, if (!new_plane_state->uapi.fence) { /* implicit fencing */ struct dma_fence *fence; - ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, + ret = i915_sw_fence_await_reservation(&state->commit_ready, obj->base.resv, NULL, false, I915_FENCE_TIMEOUT, GFP_KERNEL); if (ret < 0) - return ret; + goto unpin_fb; fence = dma_resv_get_excl_rcu(obj->base.resv); if (fence) { @@ -15833,12 +16033,17 @@ intel_prepare_plane_fb(struct drm_plane *plane, * that are not quite steady state without resorting to forcing * maximum clocks following a vblank miss (see do_rps_boost()). */ - if (!intel_state->rps_interactive) { + if (!state->rps_interactive) { intel_rps_mark_interactive(&dev_priv->gt.rps, true); - intel_state->rps_interactive = true; + state->rps_interactive = true; } return 0; + +unpin_fb: + intel_plane_unpin_fb(new_plane_state); + + return ret; } /** @@ -15854,13 +16059,17 @@ intel_cleanup_plane_fb(struct drm_plane *plane, { struct intel_plane_state *old_plane_state = to_intel_plane_state(_old_plane_state); - struct intel_atomic_state *intel_state = + struct intel_atomic_state *state = to_intel_atomic_state(old_plane_state->uapi.state); struct drm_i915_private *dev_priv = to_i915(plane->dev); + struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb); + + if (!obj) + return; - if (intel_state->rps_interactive) { + if (state->rps_interactive) { intel_rps_mark_interactive(&dev_priv->gt.rps, false); - intel_state->rps_interactive = false; + state->rps_interactive = false; } /* Should only be called after a successful intel_prepare_plane_fb()! */ @@ -16029,6 +16238,8 @@ intel_legacy_cursor_update(struct drm_plane *_plane, new_plane_state->uapi.crtc_w = crtc_w; new_plane_state->uapi.crtc_h = crtc_h; + intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state); + ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, old_plane_state, new_plane_state); if (ret) @@ -16113,7 +16324,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; unsigned int supported_rotations; - unsigned int possible_crtcs; const u32 *formats; int num_formats; int ret, zpos; @@ -16194,18 +16404,16 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->get_hw_state = i9xx_plane_get_hw_state; plane->check_plane = i9xx_plane_check; - possible_crtcs = BIT(pipe); - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, - possible_crtcs, plane_funcs, + 0, plane_funcs, formats, num_formats, i9xx_format_modifiers, DRM_PLANE_TYPE_PRIMARY, "primary %c", pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, - possible_crtcs, plane_funcs, + 0, plane_funcs, formats, num_formats, i9xx_format_modifiers, DRM_PLANE_TYPE_PRIMARY, @@ -16247,7 +16455,6 @@ static struct intel_plane * intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) { - unsigned int possible_crtcs; struct intel_plane *cursor; int ret, zpos; @@ -16280,10 +16487,8 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) cursor->cursor.size = ~0; - possible_crtcs = BIT(pipe); - ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, - possible_crtcs, &intel_cursor_plane_funcs, + 0, &intel_cursor_plane_funcs, intel_cursor_formats, ARRAY_SIZE(intel_cursor_formats), cursor_format_modifiers, @@ -16328,6 +16533,7 @@ static const struct drm_crtc_funcs bdw_crtc_funcs = { .get_vblank_counter = g4x_get_vblank_counter, .enable_vblank = bdw_enable_vblank, .disable_vblank = bdw_disable_vblank, + .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; static const struct drm_crtc_funcs ilk_crtc_funcs = { @@ -16336,6 +16542,7 @@ static const struct drm_crtc_funcs ilk_crtc_funcs = { .get_vblank_counter = g4x_get_vblank_counter, .enable_vblank = ilk_enable_vblank, .disable_vblank = ilk_disable_vblank, + .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; static const struct drm_crtc_funcs g4x_crtc_funcs = { @@ -16344,6 +16551,7 @@ static const struct drm_crtc_funcs g4x_crtc_funcs = { .get_vblank_counter = g4x_get_vblank_counter, .enable_vblank = i965_enable_vblank, .disable_vblank = i965_disable_vblank, + .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; static const struct drm_crtc_funcs i965_crtc_funcs = { @@ -16352,6 +16560,7 @@ static const struct drm_crtc_funcs i965_crtc_funcs = { .get_vblank_counter = i915_get_vblank_counter, .enable_vblank = i965_enable_vblank, .disable_vblank = i965_disable_vblank, + .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; static const struct drm_crtc_funcs i915gm_crtc_funcs = { @@ -16360,6 +16569,7 @@ static const struct drm_crtc_funcs i915gm_crtc_funcs = { .get_vblank_counter = i915_get_vblank_counter, .enable_vblank = i915gm_enable_vblank, .disable_vblank = i915gm_disable_vblank, + .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; static const struct drm_crtc_funcs i915_crtc_funcs = { @@ -16368,6 +16578,7 @@ static const struct drm_crtc_funcs i915_crtc_funcs = { .get_vblank_counter = i915_get_vblank_counter, .enable_vblank = i8xx_enable_vblank, .disable_vblank = i8xx_disable_vblank, + .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; static const struct drm_crtc_funcs i8xx_crtc_funcs = { @@ -16376,6 +16587,7 @@ static const struct drm_crtc_funcs i8xx_crtc_funcs = { /* no hw vblank counter */ .enable_vblank = i8xx_enable_vblank, .disable_vblank = i8xx_disable_vblank, + .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, }; static struct intel_crtc *intel_crtc_alloc(void) @@ -16405,6 +16617,18 @@ static void intel_crtc_free(struct intel_crtc *crtc) kfree(crtc); } +static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv) +{ + struct intel_plane *plane; + + for_each_intel_plane(&dev_priv->drm, plane) { + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, + plane->pipe); + + plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); + } +} + static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) { struct intel_plane *primary, *cursor; @@ -16483,7 +16707,9 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) intel_color_init(crtc); - WARN_ON(drm_crtc_index(&crtc->base) != crtc->pipe); + intel_crtc_crc_init(crtc); + + drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe); return 0; @@ -16543,10 +16769,10 @@ static bool ilk_has_edp_a(struct drm_i915_private *dev_priv) if (!IS_MOBILE(dev_priv)) return false; - if ((I915_READ(DP_A) & DP_DETECTED) == 0) + if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0) return false; - if (IS_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) + if (IS_GEN(dev_priv, 5) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE)) return false; return true; @@ -16561,11 +16787,11 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv) return false; if (HAS_PCH_LPT_H(dev_priv) && - I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) + intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) return false; /* DDI E can't be used if DDI A requires 4 lanes */ - if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) + if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) return false; if (!dev_priv->vbt.int_crt_support) @@ -16591,10 +16817,10 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) pps_num = 1; for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { - u32 val = I915_READ(PP_CONTROL(pps_idx)); + u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)); val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; - I915_WRITE(PP_CONTROL(pps_idx), val); + intel_de_write(dev_priv, PP_CONTROL(pps_idx), val); } } @@ -16674,14 +16900,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) * On SKL pre-D0 the strap isn't connected, so we assume * it's there. */ - found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; + found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; /* WaIgnoreDDIAStrap: skl */ if (found || IS_GEN9_BC(dev_priv)) intel_ddi_init(dev_priv, PORT_A); /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP * register */ - found = I915_READ(SFUSE_STRAP); + found = intel_de_read(dev_priv, SFUSE_STRAP); if (found & SFUSE_STRAP_DDIB_DETECTED) intel_ddi_init(dev_priv, PORT_B); @@ -16714,25 +16940,25 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (ilk_has_edp_a(dev_priv)) intel_dp_init(dev_priv, DP_A, PORT_A); - if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { + if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) { /* PCH SDVOB multiplex with HDMIB */ found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); if (!found) intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); - if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) + if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED)) intel_dp_init(dev_priv, PCH_DP_B, PORT_B); } - if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) + if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED) intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); - if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) + if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED) intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); - if (I915_READ(PCH_DP_C) & DP_DETECTED) + if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED) intel_dp_init(dev_priv, PCH_DP_C, PORT_C); - if (I915_READ(PCH_DP_D) & DP_DETECTED) + if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED) intel_dp_init(dev_priv, PCH_DP_D, PORT_D); } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { bool has_edp, has_port; @@ -16757,16 +16983,16 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) */ has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); has_port = intel_bios_is_port_present(dev_priv, PORT_B); - if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) + if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port) has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); - if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) + if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); has_port = intel_bios_is_port_present(dev_priv, PORT_C); - if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) + if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port) has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); - if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) + if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); if (IS_CHERRYVIEW(dev_priv)) { @@ -16775,9 +17001,9 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) * so no need to worry about it */ has_port = intel_bios_is_port_present(dev_priv, PORT_D); - if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) + if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port) intel_dp_init(dev_priv, CHV_DP_D, PORT_D); - if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) + if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port) intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); } @@ -16793,11 +17019,12 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_crt_init(dev_priv); - if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { - DRM_DEBUG_KMS("probing SDVOB\n"); + if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { + drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n"); found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); if (!found && IS_G4X(dev_priv)) { - DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); + drm_dbg_kms(&dev_priv->drm, + "probing HDMI on SDVOB\n"); intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); } @@ -16807,22 +17034,23 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) /* Before G4X SDVOC doesn't have its own detect register */ - if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { - DRM_DEBUG_KMS("probing SDVOC\n"); + if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) { + drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n"); found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); } - if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { + if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) { if (IS_G4X(dev_priv)) { - DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); + drm_dbg_kms(&dev_priv->drm, + "probing HDMI on SDVOC\n"); intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); } if (IS_G4X(dev_priv)) intel_dp_init(dev_priv, DP_C, PORT_C); } - if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) + if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED)) intel_dp_init(dev_priv, DP_D, PORT_D); if (SUPPORTS_TV(dev_priv)) @@ -16864,9 +17092,11 @@ static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, unsigned int *handle) { struct drm_i915_gem_object *obj = intel_fb_obj(fb); + struct drm_i915_private *i915 = to_i915(obj->base.dev); if (obj->userptr.mm) { - DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); + drm_dbg(&i915->drm, + "attempting to use a userptr for a framebuffer, denied\n"); return -EINVAL; } @@ -16920,14 +17150,16 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, */ if (tiling != I915_TILING_NONE && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { - DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); + drm_dbg_kms(&dev_priv->drm, + "tiling_mode doesn't match fb modifier\n"); goto err; } } else { if (tiling == I915_TILING_X) { mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; } else if (tiling == I915_TILING_Y) { - DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); + drm_dbg_kms(&dev_priv->drm, + "No Y tiling for legacy addfb\n"); goto err; } } @@ -16937,10 +17169,11 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, mode_cmd->modifier[0])) { struct drm_format_name_buf format_name; - DRM_DEBUG_KMS("unsupported pixel format %s / modifier 0x%llx\n", - drm_get_format_name(mode_cmd->pixel_format, - &format_name), - mode_cmd->modifier[0]); + drm_dbg_kms(&dev_priv->drm, + "unsupported pixel format %s / modifier 0x%llx\n", + drm_get_format_name(mode_cmd->pixel_format, + &format_name), + mode_cmd->modifier[0]); goto err; } @@ -16950,17 +17183,19 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, */ if (INTEL_GEN(dev_priv) < 4 && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { - DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); + drm_dbg_kms(&dev_priv->drm, + "tiling_mode must match fb modifier exactly on gen2/3\n"); goto err; } max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, mode_cmd->modifier[0]); if (mode_cmd->pitches[0] > max_stride) { - DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", - mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? - "tiled" : "linear", - mode_cmd->pitches[0], max_stride); + drm_dbg_kms(&dev_priv->drm, + "%s pitch (%u) must be at most %d\n", + mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? + "tiled" : "linear", + mode_cmd->pitches[0], max_stride); goto err; } @@ -16969,15 +17204,17 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, * the fb pitch and fence stride match. */ if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { - DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", - mode_cmd->pitches[0], stride); + drm_dbg_kms(&dev_priv->drm, + "pitch (%d) must match tiling stride (%d)\n", + mode_cmd->pitches[0], stride); goto err; } /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ if (mode_cmd->offsets[0] != 0) { - DRM_DEBUG_KMS("plane 0 offset (0x%08x) must be 0\n", - mode_cmd->offsets[0]); + drm_dbg_kms(&dev_priv->drm, + "plane 0 offset (0x%08x) must be 0\n", + mode_cmd->offsets[0]); goto err; } @@ -16987,14 +17224,16 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, u32 stride_alignment; if (mode_cmd->handles[i] != mode_cmd->handles[0]) { - DRM_DEBUG_KMS("bad plane %d handle\n", i); + drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", + i); goto err; } stride_alignment = intel_fb_stride_alignment(fb, i); if (fb->pitches[i] & (stride_alignment - 1)) { - DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", - i, fb->pitches[i], stride_alignment); + drm_dbg_kms(&dev_priv->drm, + "plane %d pitch (%d) must be at least %u byte aligned\n", + i, fb->pitches[i], stride_alignment); goto err; } @@ -17002,9 +17241,10 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, int ccs_aux_stride = gen12_ccs_aux_stride(fb, i); if (fb->pitches[i] != ccs_aux_stride) { - DRM_DEBUG_KMS("ccs aux plane %d pitch (%d) must be %d\n", - i, - fb->pitches[i], ccs_aux_stride); + drm_dbg_kms(&dev_priv->drm, + "ccs aux plane %d pitch (%d) must be %d\n", + i, + fb->pitches[i], ccs_aux_stride); goto err; } } @@ -17018,7 +17258,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); if (ret) { - DRM_ERROR("framebuffer init failed %d\n", ret); + drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret); goto err; } @@ -17048,17 +17288,6 @@ intel_user_framebuffer_create(struct drm_device *dev, return fb; } -static void intel_atomic_state_free(struct drm_atomic_state *state) -{ - struct intel_atomic_state *intel_state = to_intel_atomic_state(state); - - drm_atomic_state_default_release(state); - - i915_sw_fence_fini(&intel_state->commit_ready); - - kfree(state); -} - static enum drm_mode_status intel_mode_valid(struct drm_device *dev, const struct drm_display_mode *mode) @@ -17290,9 +17519,36 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) void intel_modeset_init_hw(struct drm_i915_private *i915) { + struct intel_cdclk_state *cdclk_state = + to_intel_cdclk_state(i915->cdclk.obj.state); + intel_update_cdclk(i915); - intel_dump_cdclk_state(&i915->cdclk.hw, "Current CDCLK"); - i915->cdclk.logical = i915->cdclk.actual = i915->cdclk.hw; + intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); + cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; +} + +static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) +{ + struct drm_plane *plane; + struct drm_crtc *crtc; + + drm_for_each_crtc(crtc, state->dev) { + struct drm_crtc_state *crtc_state; + + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + drm_for_each_plane(plane, state->dev) { + struct drm_plane_state *plane_state; + + plane_state = drm_atomic_get_plane_state(state, plane); + if (IS_ERR(plane_state)) + return PTR_ERR(plane_state); + } + + return 0; } /* @@ -17305,9 +17561,8 @@ void intel_modeset_init_hw(struct drm_i915_private *i915) * through the atomic check code to calculate new watermark values in the * state object. */ -static void sanitize_watermarks(struct drm_device *dev) +static void sanitize_watermarks(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(dev); struct drm_atomic_state *state; struct intel_atomic_state *intel_state; struct intel_crtc *crtc; @@ -17320,26 +17575,17 @@ static void sanitize_watermarks(struct drm_device *dev) if (!dev_priv->display.optimize_watermarks) return; - /* - * We need to hold connection_mutex before calling duplicate_state so - * that the connector loop is protected. - */ - drm_modeset_acquire_init(&ctx, 0); -retry: - ret = drm_modeset_lock_all_ctx(dev, &ctx); - if (ret == -EDEADLK) { - drm_modeset_backoff(&ctx); - goto retry; - } else if (WARN_ON(ret)) { - goto fail; - } - - state = drm_atomic_helper_duplicate_state(dev, &ctx); - if (WARN_ON(IS_ERR(state))) - goto fail; + state = drm_atomic_state_alloc(&dev_priv->drm); + if (drm_WARN_ON(&dev_priv->drm, !state)) + return; intel_state = to_intel_atomic_state(state); + drm_modeset_acquire_init(&ctx, 0); + +retry: + state->acquire_ctx = &ctx; + /* * Hardware readout is the only time we don't want to calculate * intermediate watermarks (since we don't trust the current @@ -17348,22 +17594,13 @@ retry: if (!HAS_GMCH(dev_priv)) intel_state->skip_intermediate_wm = true; - ret = intel_atomic_check(dev, state); - if (ret) { - /* - * If we fail here, it means that the hardware appears to be - * programmed in a way that shouldn't be possible, given our - * understanding of watermark requirements. This might mean a - * mistake in the hardware readout code or a mistake in the - * watermark calculations for a given platform. Raise a WARN - * so that this is noticeable. - * - * If this actually happens, we'll have to just leave the - * BIOS-programmed watermarks untouched and hope for the best. - */ - WARN(true, "Could not determine valid watermarks for inherited state\n"); - goto put_state; - } + ret = sanitize_watermarks_add_affected(state); + if (ret) + goto fail; + + ret = intel_atomic_check(&dev_priv->drm, state); + if (ret) + goto fail; /* Write calculated watermark values back */ for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { @@ -17373,9 +17610,29 @@ retry: to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; } -put_state: - drm_atomic_state_put(state); fail: + if (ret == -EDEADLK) { + drm_atomic_state_clear(state); + drm_modeset_backoff(&ctx); + goto retry; + } + + /* + * If we fail here, it means that the hardware appears to be + * programmed in a way that shouldn't be possible, given our + * understanding of watermark requirements. This might mean a + * mistake in the hardware readout code or a mistake in the + * watermark calculations for a given platform. Raise a WARN + * so that this is noticeable. + * + * If this actually happens, we'll have to just leave the + * BIOS-programmed watermarks untouched and hope for the best. + */ + drm_WARN(&dev_priv->drm, ret, + "Could not determine valid watermarks for inherited state\n"); + + drm_atomic_state_put(state); + drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); } @@ -17384,7 +17641,7 @@ static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) { if (IS_GEN(dev_priv, 5)) { u32 fdi_pll_clk = - I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; + intel_de_read(dev_priv, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; } else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) { @@ -17393,7 +17650,7 @@ static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) return; } - DRM_DEBUG_DRIVER("FDI PLL freq=%d\n", dev_priv->fdi_pll_freq); + drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq); } static int intel_initial_commit(struct drm_device *dev) @@ -17476,6 +17733,7 @@ static void intel_mode_config_init(struct drm_i915_private *i915) struct drm_mode_config *mode_config = &i915->drm.mode_config; drm_mode_config_init(&i915->drm); + INIT_LIST_HEAD(&i915->global_obj_list); mode_config->min_width = 0; mode_config->min_height = 0; @@ -17517,11 +17775,31 @@ static void intel_mode_config_init(struct drm_i915_private *i915) } } -int intel_modeset_init(struct drm_i915_private *i915) +static void intel_mode_config_cleanup(struct drm_i915_private *i915) +{ + intel_atomic_global_obj_cleanup(i915); + drm_mode_config_cleanup(&i915->drm); +} + +static void plane_config_fini(struct intel_initial_plane_config *plane_config) +{ + if (plane_config->fb) { + struct drm_framebuffer *fb = &plane_config->fb->base; + + /* We may only have the stub and not a full framebuffer */ + if (drm_framebuffer_read_refcount(fb)) + drm_framebuffer_put(fb); + else + kfree(fb); + } + + if (plane_config->vma) + i915_vma_put(plane_config->vma); +} + +/* part #1: call before irq install */ +int intel_modeset_init_noirq(struct drm_i915_private *i915) { - struct drm_device *dev = &i915->drm; - enum pipe pipe; - struct intel_crtc *crtc; int ret; i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); @@ -17530,6 +17808,10 @@ int intel_modeset_init(struct drm_i915_private *i915) intel_mode_config_init(i915); + ret = intel_cdclk_init(i915); + if (ret) + return ret; + ret = intel_bw_init(i915); if (ret) return ret; @@ -17542,26 +17824,38 @@ int intel_modeset_init(struct drm_i915_private *i915) intel_fbc_init(i915); + return 0; +} + +/* part #2: call after irq install */ +int intel_modeset_init(struct drm_i915_private *i915) +{ + struct drm_device *dev = &i915->drm; + enum pipe pipe; + struct intel_crtc *crtc; + int ret; + intel_init_pm(i915); intel_panel_sanitize_ssc(i915); intel_gmbus_setup(i915); - DRM_DEBUG_KMS("%d display pipe%s available.\n", - INTEL_NUM_PIPES(i915), - INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); + drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n", + INTEL_NUM_PIPES(i915), + INTEL_NUM_PIPES(i915) > 1 ? "s" : ""); if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) { for_each_pipe(i915, pipe) { ret = intel_crtc_init(i915, pipe); if (ret) { - drm_mode_config_cleanup(dev); + intel_mode_config_cleanup(i915); return ret; } } } + intel_plane_possible_crtcs_init(i915); intel_shared_dpll_init(dev); intel_update_fdi_pll_freq(i915); @@ -17601,6 +17895,8 @@ int intel_modeset_init(struct drm_i915_private *i915) * just get the first one. */ intel_find_initial_plane_obj(crtc, &plane_config); + + plane_config_fini(&plane_config); } /* @@ -17609,7 +17905,7 @@ int intel_modeset_init(struct drm_i915_private *i915) * since the watermark calculation done here will use pstate->fb. */ if (!HAS_GMCH(i915)) - sanitize_watermarks(dev); + sanitize_watermarks(i915); /* * Force all active planes to recompute their states. So that on @@ -17619,7 +17915,7 @@ int intel_modeset_init(struct drm_i915_private *i915) */ ret = intel_initial_commit(dev); if (ret) - DRM_DEBUG_KMS("Initial commit in probe failed.\n"); + drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n"); return 0; } @@ -17638,10 +17934,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) u32 dpll, fp; int i; - WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); + drm_WARN_ON(&dev_priv->drm, + i9xx_calc_dpll_params(48000, &clock) != 25154); - DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n", - pipe_name(pipe), clock.vco, clock.dot); + drm_dbg_kms(&dev_priv->drm, + "enabling pipe %c due to force quirk (vco=%d dot=%d)\n", + pipe_name(pipe), clock.vco, clock.dot); fp = i9xx_dpll_compute_fp(&clock); dpll = DPLL_DVO_2X_MODE | @@ -17651,27 +17949,27 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) PLL_REF_INPUT_DREFCLK | DPLL_VCO_ENABLE; - I915_WRITE(FP0(pipe), fp); - I915_WRITE(FP1(pipe), fp); + intel_de_write(dev_priv, FP0(pipe), fp); + intel_de_write(dev_priv, FP1(pipe), fp); - I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); - I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); - I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); - I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); - I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); - I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); - I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); + intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); + intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); + intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); + intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); + intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); + intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); + intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); /* * Apparently we need to have VGA mode enabled prior to changing * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); - I915_WRITE(DPLL(pipe), dpll); + intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); + intel_de_write(dev_priv, DPLL(pipe), dpll); /* Wait for the clocks to stabilize. */ - POSTING_READ(DPLL(pipe)); + intel_de_posting_read(dev_priv, DPLL(pipe)); udelay(150); /* The pixel multiplier can only be updated once the @@ -17679,17 +17977,18 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) * * So write it again. */ - I915_WRITE(DPLL(pipe), dpll); + intel_de_write(dev_priv, DPLL(pipe), dpll); /* We do this three times for luck */ for (i = 0; i < 3 ; i++) { - I915_WRITE(DPLL(pipe), dpll); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), dpll); + intel_de_posting_read(dev_priv, DPLL(pipe)); udelay(150); /* wait for warmup */ } - I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); - POSTING_READ(PIPECONF(pipe)); + intel_de_write(dev_priv, PIPECONF(pipe), + PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); + intel_de_posting_read(dev_priv, PIPECONF(pipe)); intel_wait_for_pipe_scanline_moving(crtc); } @@ -17698,22 +17997,30 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", - pipe_name(pipe)); - - WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); - WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); - WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); - WARN_ON(I915_READ(CURCNTR(PIPE_A)) & MCURSOR_MODE); - WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE); - - I915_WRITE(PIPECONF(pipe), 0); - POSTING_READ(PIPECONF(pipe)); + drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n", + pipe_name(pipe)); + + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & + DISPLAY_PLANE_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & + DISPLAY_PLANE_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & + DISPLAY_PLANE_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE); + + intel_de_write(dev_priv, PIPECONF(pipe), 0); + intel_de_posting_read(dev_priv, PIPECONF(pipe)); intel_wait_for_pipe_scanline_stopped(crtc); - I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); - POSTING_READ(DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); + intel_de_posting_read(dev_priv, DPLL(pipe)); } static void @@ -17736,8 +18043,9 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) if (pipe == crtc->pipe) continue; - DRM_DEBUG_KMS("[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", - plane->base.base.id, plane->base.name); + drm_dbg_kms(&dev_priv->drm, + "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n", + plane->base.base.id, plane->base.name); plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe); intel_plane_disable_noatomic(plane_crtc, plane); @@ -17787,18 +18095,18 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc if (transcoder_is_dsi(cpu_transcoder)) return; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~HSW_FRAME_START_DELAY_MASK; val |= HSW_FRAME_START_DELAY(0); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } else { i915_reg_t reg = PIPECONF(cpu_transcoder); u32 val; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~PIPECONF_FRAME_START_DELAY_MASK; val |= PIPECONF_FRAME_START_DELAY(0); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } if (!crtc_state->has_pch_encoder) @@ -17808,19 +18116,19 @@ static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc i915_reg_t reg = PCH_TRANSCONF(crtc->pipe); u32 val; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~TRANS_FRAME_START_DELAY_MASK; val |= TRANS_FRAME_START_DELAY(0); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } else { enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc); i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder); u32 val; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; val |= TRANS_CHICKEN2_FRAME_START_DELAY(0); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } } @@ -17852,9 +18160,8 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc, * gamma and CSC to match how we program our planes. */ if (INTEL_GEN(dev_priv) >= 9) - I915_WRITE(SKL_BOTTOM_COLOR(crtc->pipe), - SKL_BOTTOM_COLOR_GAMMA_ENABLE | - SKL_BOTTOM_COLOR_CSC_ENABLE); + intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe), + SKL_BOTTOM_COLOR_GAMMA_ENABLE | SKL_BOTTOM_COLOR_CSC_ENABLE); } /* Adjust the state of the output pipe according to whether we @@ -17926,16 +18233,18 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) crtc_state->hw.active; if (crtc_state && has_bogus_dpll_config(crtc_state)) { - DRM_DEBUG_KMS("BIOS has misprogrammed the hardware. Disabling pipe %c\n", - pipe_name(crtc->pipe)); + drm_dbg_kms(&dev_priv->drm, + "BIOS has misprogrammed the hardware. Disabling pipe %c\n", + pipe_name(crtc->pipe)); has_active_crtc = false; } connector = intel_encoder_find_connector(encoder); if (connector && !has_active_crtc) { - DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", - encoder->base.base.id, - encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] has active connectors but no active pipe!\n", + encoder->base.base.id, + encoder->base.name); /* Connector is active, but has no active pipe. This is * fallout from our resume register restoring. Disable @@ -17943,9 +18252,10 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) if (crtc_state) { struct drm_encoder *best_encoder; - DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", - encoder->base.base.id, - encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] manually disabled\n", + encoder->base.base.id, + encoder->base.name); /* avoid oopsing in case the hooks consult best_encoder */ best_encoder = connector->base.state->best_encoder; @@ -17998,9 +18308,10 @@ static void readout_plane_state(struct drm_i915_private *dev_priv) intel_set_plane_visible(crtc_state, plane_state, visible); - DRM_DEBUG_KMS("[PLANE:%d:%s] hw state readout: %s, pipe %c\n", - plane->base.base.id, plane->base.name, - enableddisabled(visible), pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, + "[PLANE:%d:%s] hw state readout: %s, pipe %c\n", + plane->base.base.id, plane->base.name, + enableddisabled(visible), pipe_name(pipe)); } for_each_intel_crtc(&dev_priv->drm, crtc) { @@ -18014,14 +18325,14 @@ static void readout_plane_state(struct drm_i915_private *dev_priv) static void intel_modeset_readout_hw_state(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + struct intel_cdclk_state *cdclk_state = + to_intel_cdclk_state(dev_priv->cdclk.obj.state); enum pipe pipe; struct intel_crtc *crtc; struct intel_encoder *encoder; struct intel_connector *connector; struct drm_connector_list_iter conn_iter; - int i; - - dev_priv->active_pipes = 0; + u8 active_pipes = 0; for_each_intel_crtc(dev, crtc) { struct intel_crtc_state *crtc_state = @@ -18038,41 +18349,19 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) crtc->active = crtc_state->hw.active; if (crtc_state->hw.active) - dev_priv->active_pipes |= BIT(crtc->pipe); + active_pipes |= BIT(crtc->pipe); - DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", - crtc->base.base.id, crtc->base.name, - enableddisabled(crtc_state->hw.active)); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] hw state readout: %s\n", + crtc->base.base.id, crtc->base.name, + enableddisabled(crtc_state->hw.active)); } - readout_plane_state(dev_priv); - - for (i = 0; i < dev_priv->num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; + dev_priv->active_pipes = cdclk_state->active_pipes = active_pipes; - pll->on = pll->info->funcs->get_hw_state(dev_priv, pll, - &pll->state.hw_state); - - if (IS_ELKHARTLAKE(dev_priv) && pll->on && - pll->info->id == DPLL_ID_EHL_DPLL4) { - pll->wakeref = intel_display_power_get(dev_priv, - POWER_DOMAIN_DPLL_DC_OFF); - } - - pll->state.crtc_mask = 0; - for_each_intel_crtc(dev, crtc) { - struct intel_crtc_state *crtc_state = - to_intel_crtc_state(crtc->base.state); - - if (crtc_state->hw.active && - crtc_state->shared_dpll == pll) - pll->state.crtc_mask |= 1 << crtc->pipe; - } - pll->active_mask = pll->state.crtc_mask; + readout_plane_state(dev_priv); - DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", - pll->info->name, pll->state.crtc_mask, pll->on); - } + intel_dpll_readout_hw_state(dev_priv); for_each_intel_encoder(dev, encoder) { pipe = 0; @@ -18089,10 +18378,11 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) encoder->base.crtc = NULL; } - DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", - encoder->base.base.id, encoder->base.name, - enableddisabled(encoder->base.crtc), - pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", + encoder->base.base.id, encoder->base.name, + enableddisabled(encoder->base.crtc), + pipe_name(pipe)); } drm_connector_list_iter_begin(dev, &conn_iter); @@ -18103,7 +18393,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) connector->base.dpms = DRM_MODE_DPMS_ON; - encoder = connector->encoder; + encoder = intel_attached_encoder(connector); connector->base.encoder = &encoder->base; crtc = to_intel_crtc(encoder->base.crtc); @@ -18124,9 +18414,10 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) connector->base.dpms = DRM_MODE_DPMS_OFF; connector->base.encoder = NULL; } - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", - connector->base.base.id, connector->base.name, - enableddisabled(connector->base.encoder)); + drm_dbg_kms(&dev_priv->drm, + "[CONNECTOR:%d:%s] hw state readout: %s\n", + connector->base.base.id, connector->base.name, + enableddisabled(connector->base.encoder)); } drm_connector_list_iter_end(&conn_iter); @@ -18190,19 +18481,20 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) crtc_state->min_cdclk[plane->id] = crtc_state->pixel_rate; } - DRM_DEBUG_KMS("[PLANE:%d:%s] min_cdclk %d kHz\n", - plane->base.base.id, plane->base.name, - crtc_state->min_cdclk[plane->id]); + drm_dbg_kms(&dev_priv->drm, + "[PLANE:%d:%s] min_cdclk %d kHz\n", + plane->base.base.id, plane->base.name, + crtc_state->min_cdclk[plane->id]); } if (crtc_state->hw.active) { min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); - if (WARN_ON(min_cdclk < 0)) + if (drm_WARN_ON(dev, min_cdclk < 0)) min_cdclk = 0; } - dev_priv->min_cdclk[crtc->pipe] = min_cdclk; - dev_priv->min_voltage_level[crtc->pipe] = + cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; + cdclk_state->min_voltage_level[crtc->pipe] = crtc_state->min_voltage_level; intel_bw_crtc_update(bw_state, crtc_state); @@ -18241,53 +18533,55 @@ static void intel_early_display_was(struct drm_i915_private *dev_priv) * Also known as Wa_14010480278. */ if (IS_GEN_RANGE(dev_priv, 10, 12) || IS_GEMINILAKE(dev_priv)) - I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | - DARBF_GATING_DIS); + intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0, + intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0) | DARBF_GATING_DIS); if (IS_HASWELL(dev_priv)) { /* * WaRsPkgCStateDisplayPMReq:hsw * System hang if this isn't done before disabling all planes! */ - I915_WRITE(CHICKEN_PAR1_1, - I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); + intel_de_write(dev_priv, CHICKEN_PAR1_1, + intel_de_read(dev_priv, CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); } } static void ibx_sanitize_pch_hdmi_port(struct drm_i915_private *dev_priv, enum port port, i915_reg_t hdmi_reg) { - u32 val = I915_READ(hdmi_reg); + u32 val = intel_de_read(dev_priv, hdmi_reg); if (val & SDVO_ENABLE || (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) return; - DRM_DEBUG_KMS("Sanitizing transcoder select for HDMI %c\n", - port_name(port)); + drm_dbg_kms(&dev_priv->drm, + "Sanitizing transcoder select for HDMI %c\n", + port_name(port)); val &= ~SDVO_PIPE_SEL_MASK; val |= SDVO_PIPE_SEL(PIPE_A); - I915_WRITE(hdmi_reg, val); + intel_de_write(dev_priv, hdmi_reg, val); } static void ibx_sanitize_pch_dp_port(struct drm_i915_private *dev_priv, enum port port, i915_reg_t dp_reg) { - u32 val = I915_READ(dp_reg); + u32 val = intel_de_read(dev_priv, dp_reg); if (val & DP_PORT_EN || (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) return; - DRM_DEBUG_KMS("Sanitizing transcoder select for DP %c\n", - port_name(port)); + drm_dbg_kms(&dev_priv->drm, + "Sanitizing transcoder select for DP %c\n", + port_name(port)); val &= ~DP_PIPE_SEL_MASK; val |= DP_PIPE_SEL(PIPE_A); - I915_WRITE(dp_reg, val); + intel_de_write(dev_priv, dp_reg, val); } static void ibx_sanitize_pch_ports(struct drm_i915_private *dev_priv) @@ -18324,7 +18618,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev, struct intel_encoder *encoder; struct intel_crtc *crtc; intel_wakeref_t wakeref; - int i; wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); @@ -18377,18 +18670,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, intel_modeset_update_connector_atomic_state(dev); - for (i = 0; i < dev_priv->num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; - - if (!pll->on || pll->active_mask) - continue; - - DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", - pll->info->name); - - pll->info->funcs->disable(dev_priv, pll); - pll->on = false; - } + intel_dpll_sanitize_state(dev_priv); if (IS_G4X(dev_priv)) { g4x_wm_get_hw_state(dev_priv); @@ -18408,7 +18690,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, u64 put_domains; put_domains = modeset_get_crtc_power_domains(crtc_state); - if (WARN_ON(put_domains)) + if (drm_WARN_ON(dev, put_domains)) modeset_put_power_domains(dev_priv, put_domains); } @@ -18444,7 +18726,8 @@ void intel_display_resume(struct drm_device *dev) drm_modeset_acquire_fini(&ctx); if (ret) - DRM_ERROR("Restoring old state failed with %i\n", ret); + drm_err(&dev_priv->drm, + "Restoring old state failed with %i\n", ret); if (state) drm_atomic_state_put(state); } @@ -18467,21 +18750,19 @@ static void intel_hpd_poll_fini(struct drm_i915_private *i915) drm_connector_list_iter_end(&conn_iter); } +/* part #1: call before irq uninstall */ void intel_modeset_driver_remove(struct drm_i915_private *i915) { flush_workqueue(i915->flip_wq); flush_workqueue(i915->modeset_wq); flush_work(&i915->atomic_helper.free_work); - WARN_ON(!llist_empty(&i915->atomic_helper.free_list)); - - /* - * Interrupts and polling as the first thing to avoid creating havoc. - * Too much stuff here (turning of connectors, ...) would - * experience fancy races otherwise. - */ - intel_irq_uninstall(i915); + drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list)); +} +/* part #2: call after irq uninstall */ +void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915) +{ /* * Due to the hpd irq storm handling the hotplug work can re-arm the * poll handlers. Hence disable polling after hpd handling is shut down. @@ -18507,14 +18788,12 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) intel_hdcp_component_fini(i915); - drm_mode_config_cleanup(&i915->drm); + intel_mode_config_cleanup(i915); intel_overlay_cleanup(i915); intel_gmbus_teardown(i915); - intel_bw_cleanup(i915); - destroy_workqueue(i915->flip_wq); destroy_workqueue(i915->modeset_wq); @@ -18523,6 +18802,15 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915) #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) +static bool +has_transcoder(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) +{ + if (cpu_transcoder == TRANSCODER_EDP) + return HAS_TRANSCODER_EDP(dev_priv); + else + return INTEL_INFO(dev_priv)->pipe_mask & BIT(cpu_transcoder); +} + struct intel_display_error_state { u32 power_well_driver; @@ -18589,7 +18877,8 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) return NULL; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - error->power_well_driver = I915_READ(HSW_PWR_WELL_CTL2); + error->power_well_driver = intel_de_read(dev_priv, + HSW_PWR_WELL_CTL2); for_each_pipe(dev_priv, i) { error->pipe[i].power_domain_on = @@ -18598,33 +18887,39 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) if (!error->pipe[i].power_domain_on) continue; - error->cursor[i].control = I915_READ(CURCNTR(i)); - error->cursor[i].position = I915_READ(CURPOS(i)); - error->cursor[i].base = I915_READ(CURBASE(i)); + error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i)); + error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i)); + error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i)); - error->plane[i].control = I915_READ(DSPCNTR(i)); - error->plane[i].stride = I915_READ(DSPSTRIDE(i)); + error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i)); + error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i)); if (INTEL_GEN(dev_priv) <= 3) { - error->plane[i].size = I915_READ(DSPSIZE(i)); - error->plane[i].pos = I915_READ(DSPPOS(i)); + error->plane[i].size = intel_de_read(dev_priv, + DSPSIZE(i)); + error->plane[i].pos = intel_de_read(dev_priv, + DSPPOS(i)); } if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) - error->plane[i].addr = I915_READ(DSPADDR(i)); + error->plane[i].addr = intel_de_read(dev_priv, + DSPADDR(i)); if (INTEL_GEN(dev_priv) >= 4) { - error->plane[i].surface = I915_READ(DSPSURF(i)); - error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); + error->plane[i].surface = intel_de_read(dev_priv, + DSPSURF(i)); + error->plane[i].tile_offset = intel_de_read(dev_priv, + DSPTILEOFF(i)); } - error->pipe[i].source = I915_READ(PIPESRC(i)); + error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i)); if (HAS_GMCH(dev_priv)) - error->pipe[i].stat = I915_READ(PIPESTAT(i)); + error->pipe[i].stat = intel_de_read(dev_priv, + PIPESTAT(i)); } for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) { enum transcoder cpu_transcoder = transcoders[i]; - if (!INTEL_INFO(dev_priv)->trans_offsets[cpu_transcoder]) + if (!has_transcoder(dev_priv, cpu_transcoder)) continue; error->transcoder[i].available = true; @@ -18636,13 +18931,20 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) error->transcoder[i].cpu_transcoder = cpu_transcoder; - error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); - error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); - error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); - error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); - error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); - error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); - error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); + error->transcoder[i].conf = intel_de_read(dev_priv, + PIPECONF(cpu_transcoder)); + error->transcoder[i].htotal = intel_de_read(dev_priv, + HTOTAL(cpu_transcoder)); + error->transcoder[i].hblank = intel_de_read(dev_priv, + HBLANK(cpu_transcoder)); + error->transcoder[i].hsync = intel_de_read(dev_priv, + HSYNC(cpu_transcoder)); + error->transcoder[i].vtotal = intel_de_read(dev_priv, + VTOTAL(cpu_transcoder)); + error->transcoder[i].vblank = intel_de_read(dev_priv, + VBLANK(cpu_transcoder)); + error->transcoder[i].vsync = intel_de_read(dev_priv, + VSYNC(cpu_transcoder)); } return error; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 028aab728514..adb1225a3480 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -26,7 +26,6 @@ #define _INTEL_DISPLAY_H_ #include <drm/drm_util.h> -#include <drm/i915_drm.h> enum link_m_n_set; struct dpll; @@ -40,12 +39,15 @@ struct drm_framebuffer; struct drm_i915_error_state_buf; struct drm_i915_gem_object; struct drm_i915_private; +struct drm_mode_fb_cmd2; struct drm_modeset_acquire_ctx; struct drm_plane; struct drm_plane_state; struct i915_ggtt_view; +struct intel_atomic_state; struct intel_crtc; struct intel_crtc_state; +struct intel_crtc_state; struct intel_digital_port; struct intel_dp; struct intel_encoder; @@ -54,7 +56,6 @@ struct intel_plane; struct intel_plane_state; struct intel_remapped_info; struct intel_rotation_info; -struct intel_crtc_state; enum i915_gpio { GPIOA, @@ -312,10 +313,11 @@ enum phy_fia { }; #define for_each_pipe(__dev_priv, __p) \ - for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) + for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \ + for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p)) #define for_each_pipe_masked(__dev_priv, __p, __mask) \ - for ((__p) = 0; (__p) < INTEL_NUM_PIPES(__dev_priv); (__p)++) \ + for_each_pipe(__dev_priv, __p) \ for_each_if((__mask) & BIT(__p)) #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \ @@ -469,6 +471,8 @@ enum phy_fia { ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \ (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1)) +u8 intel_calc_active_pipes(struct intel_atomic_state *state, + u8 active_pipes); void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, @@ -486,6 +490,7 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); void intel_plane_destroy(struct drm_plane *plane); +void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state); void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state); void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe); @@ -495,6 +500,7 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv, const char *name, u32 reg, int ref_freq); int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, const char *name, u32 reg); +void lpt_pch_enable(const struct intel_crtc_state *crtc_state); void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv); void lpt_disable_iclkip(struct drm_i915_private *dev_priv); void intel_init_display_hooks(struct drm_i915_private *dev_priv); @@ -520,6 +526,7 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc); +void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state); void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state); int ilk_get_lanes_required(int target_clock, int link_bw, int bpp); @@ -608,8 +615,10 @@ intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, /* modesetting */ void intel_modeset_init_hw(struct drm_i915_private *i915); +int intel_modeset_init_noirq(struct drm_i915_private *i915); int intel_modeset_init(struct drm_i915_private *i915); void intel_modeset_driver_remove(struct drm_i915_private *i915); +void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915); void intel_display_resume(struct drm_device *dev); void intel_init_pch_refclk(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c new file mode 100644 index 000000000000..1e6eb7f2f72d --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -0,0 +1,2134 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2020 Intel Corporation + */ + +#include <drm/drm_debugfs.h> +#include <drm/drm_fourcc.h> + +#include "i915_debugfs.h" +#include "intel_csr.h" +#include "intel_display_debugfs.h" +#include "intel_display_types.h" +#include "intel_dp.h" +#include "intel_fbc.h" +#include "intel_hdcp.h" +#include "intel_hdmi.h" +#include "intel_pm.h" +#include "intel_psr.h" +#include "intel_sideband.h" + +static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node) +{ + return to_i915(node->minor->dev); +} + +static int i915_frontbuffer_tracking(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + + seq_printf(m, "FB tracking busy bits: 0x%08x\n", + dev_priv->fb_tracking.busy_bits); + + seq_printf(m, "FB tracking flip bits: 0x%08x\n", + dev_priv->fb_tracking.flip_bits); + + return 0; +} + +static int i915_fbc_status(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_fbc *fbc = &dev_priv->fbc; + intel_wakeref_t wakeref; + + if (!HAS_FBC(dev_priv)) + return -ENODEV; + + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); + mutex_lock(&fbc->lock); + + if (intel_fbc_is_active(dev_priv)) + seq_puts(m, "FBC enabled\n"); + else + seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); + + if (intel_fbc_is_active(dev_priv)) { + u32 mask; + + if (INTEL_GEN(dev_priv) >= 8) + mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; + else if (INTEL_GEN(dev_priv) >= 7) + mask = intel_de_read(dev_priv, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; + else if (INTEL_GEN(dev_priv) >= 5) + mask = intel_de_read(dev_priv, ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; + else if (IS_G4X(dev_priv)) + mask = intel_de_read(dev_priv, DPFC_STATUS) & DPFC_COMP_SEG_MASK; + else + mask = intel_de_read(dev_priv, FBC_STATUS) & + (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); + + seq_printf(m, "Compressing: %s\n", yesno(mask)); + } + + mutex_unlock(&fbc->lock); + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + + return 0; +} + +static int i915_fbc_false_color_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) + return -ENODEV; + + *val = dev_priv->fbc.false_color; + + return 0; +} + +static int i915_fbc_false_color_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + u32 reg; + + if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) + return -ENODEV; + + mutex_lock(&dev_priv->fbc.lock); + + reg = intel_de_read(dev_priv, ILK_DPFC_CONTROL); + dev_priv->fbc.false_color = val; + + intel_de_write(dev_priv, ILK_DPFC_CONTROL, + val ? (reg | FBC_CTL_FALSE_COLOR) : (reg & ~FBC_CTL_FALSE_COLOR)); + + mutex_unlock(&dev_priv->fbc.lock); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_false_color_fops, + i915_fbc_false_color_get, i915_fbc_false_color_set, + "%llu\n"); + +static int i915_ips_status(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + intel_wakeref_t wakeref; + + if (!HAS_IPS(dev_priv)) + return -ENODEV; + + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); + + seq_printf(m, "Enabled by kernel parameter: %s\n", + yesno(i915_modparams.enable_ips)); + + if (INTEL_GEN(dev_priv) >= 8) { + seq_puts(m, "Currently: unknown\n"); + } else { + if (intel_de_read(dev_priv, IPS_CTL) & IPS_ENABLE) + seq_puts(m, "Currently: enabled\n"); + else + seq_puts(m, "Currently: disabled\n"); + } + + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + + return 0; +} + +static int i915_sr_status(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + intel_wakeref_t wakeref; + bool sr_enabled = false; + + wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); + + if (INTEL_GEN(dev_priv) >= 9) + /* no global SR status; inspect per-plane WM */; + else if (HAS_PCH_SPLIT(dev_priv)) + sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN; + else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) || + IS_I945G(dev_priv) || IS_I945GM(dev_priv)) + sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN; + else if (IS_I915GM(dev_priv)) + sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; + else if (IS_PINEVIEW(dev_priv)) + sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN; + else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; + + intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); + + seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); + + return 0; +} + +static int i915_opregion(struct seq_file *m, void *unused) +{ + struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; + + if (opregion->header) + seq_write(m, opregion->header, OPREGION_SIZE); + + return 0; +} + +static int i915_vbt(struct seq_file *m, void *unused) +{ + struct intel_opregion *opregion = &node_to_i915(m->private)->opregion; + + if (opregion->vbt) + seq_write(m, opregion->vbt, opregion->vbt_size); + + return 0; +} + +static int i915_gem_framebuffer_info(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_device *dev = &dev_priv->drm; + struct intel_framebuffer *fbdev_fb = NULL; + struct drm_framebuffer *drm_fb; + +#ifdef CONFIG_DRM_FBDEV_EMULATION + if (dev_priv->fbdev && dev_priv->fbdev->helper.fb) { + fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb); + + seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", + fbdev_fb->base.width, + fbdev_fb->base.height, + fbdev_fb->base.format->depth, + fbdev_fb->base.format->cpp[0] * 8, + fbdev_fb->base.modifier, + drm_framebuffer_read_refcount(&fbdev_fb->base)); + i915_debugfs_describe_obj(m, intel_fb_obj(&fbdev_fb->base)); + seq_putc(m, '\n'); + } +#endif + + mutex_lock(&dev->mode_config.fb_lock); + drm_for_each_fb(drm_fb, dev) { + struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb); + if (fb == fbdev_fb) + continue; + + seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", + fb->base.width, + fb->base.height, + fb->base.format->depth, + fb->base.format->cpp[0] * 8, + fb->base.modifier, + drm_framebuffer_read_refcount(&fb->base)); + i915_debugfs_describe_obj(m, intel_fb_obj(&fb->base)); + seq_putc(m, '\n'); + } + mutex_unlock(&dev->mode_config.fb_lock); + + return 0; +} + +static int i915_psr_sink_status_show(struct seq_file *m, void *data) +{ + u8 val; + static const char * const sink_status[] = { + "inactive", + "transition to active, capture and display", + "active, display from RFB", + "active, capture and display on sink device timings", + "transition to inactive, capture and display, timing re-sync", + "reserved", + "reserved", + "sink internal error", + }; + struct drm_connector *connector = m->private; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + struct intel_dp *intel_dp = + intel_attached_dp(to_intel_connector(connector)); + int ret; + + if (!CAN_PSR(dev_priv)) { + seq_puts(m, "PSR Unsupported\n"); + return -ENODEV; + } + + if (connector->status != connector_status_connected) + return -ENODEV; + + ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val); + + if (ret == 1) { + const char *str = "unknown"; + + val &= DP_PSR_SINK_STATE_MASK; + if (val < ARRAY_SIZE(sink_status)) + str = sink_status[val]; + seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str); + } else { + return ret; + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_psr_sink_status); + +static void +psr_source_status(struct drm_i915_private *dev_priv, struct seq_file *m) +{ + u32 val, status_val; + const char *status = "unknown"; + + if (dev_priv->psr.psr2_enabled) { + static const char * const live_status[] = { + "IDLE", + "CAPTURE", + "CAPTURE_FS", + "SLEEP", + "BUFON_FW", + "ML_UP", + "SU_STANDBY", + "FAST_SLEEP", + "DEEP_SLEEP", + "BUF_ON", + "TG_ON" + }; + val = intel_de_read(dev_priv, + EDP_PSR2_STATUS(dev_priv->psr.transcoder)); + status_val = (val & EDP_PSR2_STATUS_STATE_MASK) >> + EDP_PSR2_STATUS_STATE_SHIFT; + if (status_val < ARRAY_SIZE(live_status)) + status = live_status[status_val]; + } else { + static const char * const live_status[] = { + "IDLE", + "SRDONACK", + "SRDENT", + "BUFOFF", + "BUFON", + "AUXACK", + "SRDOFFACK", + "SRDENT_ON", + }; + val = intel_de_read(dev_priv, + EDP_PSR_STATUS(dev_priv->psr.transcoder)); + status_val = (val & EDP_PSR_STATUS_STATE_MASK) >> + EDP_PSR_STATUS_STATE_SHIFT; + if (status_val < ARRAY_SIZE(live_status)) + status = live_status[status_val]; + } + + seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val); +} + +static int i915_edp_psr_status(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct i915_psr *psr = &dev_priv->psr; + intel_wakeref_t wakeref; + const char *status; + bool enabled; + u32 val; + + if (!HAS_PSR(dev_priv)) + return -ENODEV; + + seq_printf(m, "Sink support: %s", yesno(psr->sink_support)); + if (psr->dp) + seq_printf(m, " [0x%02x]", psr->dp->psr_dpcd[0]); + seq_puts(m, "\n"); + + if (!psr->sink_support) + return 0; + + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); + mutex_lock(&psr->lock); + + if (psr->enabled) + status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; + else + status = "disabled"; + seq_printf(m, "PSR mode: %s\n", status); + + if (!psr->enabled) { + seq_printf(m, "PSR sink not reliable: %s\n", + yesno(psr->sink_not_reliable)); + + goto unlock; + } + + if (psr->psr2_enabled) { + val = intel_de_read(dev_priv, + EDP_PSR2_CTL(dev_priv->psr.transcoder)); + enabled = val & EDP_PSR2_ENABLE; + } else { + val = intel_de_read(dev_priv, + EDP_PSR_CTL(dev_priv->psr.transcoder)); + enabled = val & EDP_PSR_ENABLE; + } + seq_printf(m, "Source PSR ctl: %s [0x%08x]\n", + enableddisabled(enabled), val); + psr_source_status(dev_priv, m); + seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", + psr->busy_frontbuffer_bits); + + /* + * SKL+ Perf counter is reset to 0 everytime DC state is entered + */ + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { + val = intel_de_read(dev_priv, + EDP_PSR_PERF_CNT(dev_priv->psr.transcoder)); + val &= EDP_PSR_PERF_CNT_MASK; + seq_printf(m, "Performance counter: %u\n", val); + } + + if (psr->debug & I915_PSR_DEBUG_IRQ) { + seq_printf(m, "Last attempted entry at: %lld\n", + psr->last_entry_attempt); + seq_printf(m, "Last exit at: %lld\n", psr->last_exit); + } + + if (psr->psr2_enabled) { + u32 su_frames_val[3]; + int frame; + + /* + * Reading all 3 registers before hand to minimize crossing a + * frame boundary between register reads + */ + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { + val = intel_de_read(dev_priv, + PSR2_SU_STATUS(dev_priv->psr.transcoder, frame)); + su_frames_val[frame / 3] = val; + } + + seq_puts(m, "Frame:\tPSR2 SU blocks:\n"); + + for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame++) { + u32 su_blocks; + + su_blocks = su_frames_val[frame / 3] & + PSR2_SU_STATUS_MASK(frame); + su_blocks = su_blocks >> PSR2_SU_STATUS_SHIFT(frame); + seq_printf(m, "%d\t%d\n", frame, su_blocks); + } + } + +unlock: + mutex_unlock(&psr->lock); + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + + return 0; +} + +static int +i915_edp_psr_debug_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + intel_wakeref_t wakeref; + int ret; + + if (!CAN_PSR(dev_priv)) + return -ENODEV; + + drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val); + + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); + + ret = intel_psr_debug_set(dev_priv, val); + + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + + return ret; +} + +static int +i915_edp_psr_debug_get(void *data, u64 *val) +{ + struct drm_i915_private *dev_priv = data; + + if (!CAN_PSR(dev_priv)) + return -ENODEV; + + *val = READ_ONCE(dev_priv->psr.debug); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_edp_psr_debug_fops, + i915_edp_psr_debug_get, i915_edp_psr_debug_set, + "%llu\n"); + +static int i915_power_domain_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct i915_power_domains *power_domains = &dev_priv->power_domains; + int i; + + mutex_lock(&power_domains->lock); + + seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); + for (i = 0; i < power_domains->power_well_count; i++) { + struct i915_power_well *power_well; + enum intel_display_power_domain power_domain; + + power_well = &power_domains->power_wells[i]; + seq_printf(m, "%-25s %d\n", power_well->desc->name, + power_well->count); + + for_each_power_domain(power_domain, power_well->desc->domains) + seq_printf(m, " %-23s %d\n", + intel_display_power_domain_str(power_domain), + power_domains->domain_use_count[power_domain]); + } + + mutex_unlock(&power_domains->lock); + + return 0; +} + +static int i915_dmc_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + intel_wakeref_t wakeref; + struct intel_csr *csr; + i915_reg_t dc5_reg, dc6_reg = {}; + + if (!HAS_CSR(dev_priv)) + return -ENODEV; + + csr = &dev_priv->csr; + + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); + + seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); + seq_printf(m, "path: %s\n", csr->fw_path); + + if (!csr->dmc_payload) + goto out; + + seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), + CSR_VERSION_MINOR(csr->version)); + + if (INTEL_GEN(dev_priv) >= 12) { + dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; + dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; + /* + * NOTE: DMC_DEBUG3 is a general purpose reg. + * According to B.Specs:49196 DMC f/w reuses DC5/6 counter + * reg for DC3CO debugging and validation, + * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter. + */ + seq_printf(m, "DC3CO count: %d\n", + intel_de_read(dev_priv, DMC_DEBUG3)); + } else { + dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : + SKL_CSR_DC3_DC5_COUNT; + if (!IS_GEN9_LP(dev_priv)) + dc6_reg = SKL_CSR_DC5_DC6_COUNT; + } + + seq_printf(m, "DC3 -> DC5 count: %d\n", + intel_de_read(dev_priv, dc5_reg)); + if (dc6_reg.reg) + seq_printf(m, "DC5 -> DC6 count: %d\n", + intel_de_read(dev_priv, dc6_reg)); + +out: + seq_printf(m, "program base: 0x%08x\n", + intel_de_read(dev_priv, CSR_PROGRAM(0))); + seq_printf(m, "ssp base: 0x%08x\n", + intel_de_read(dev_priv, CSR_SSP_BASE)); + seq_printf(m, "htp: 0x%08x\n", intel_de_read(dev_priv, CSR_HTP_SKL)); + + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + + return 0; +} + +static void intel_seq_print_mode(struct seq_file *m, int tabs, + const struct drm_display_mode *mode) +{ + int i; + + for (i = 0; i < tabs; i++) + seq_putc(m, '\t'); + + seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); +} + +static void intel_encoder_info(struct seq_file *m, + struct intel_crtc *crtc, + struct intel_encoder *encoder) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_connector_list_iter conn_iter; + struct drm_connector *connector; + + seq_printf(m, "\t[ENCODER:%d:%s]: connectors:\n", + encoder->base.base.id, encoder->base.name); + + drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + const struct drm_connector_state *conn_state = + connector->state; + + if (conn_state->best_encoder != &encoder->base) + continue; + + seq_printf(m, "\t\t[CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + } + drm_connector_list_iter_end(&conn_iter); +} + +static void intel_panel_info(struct seq_file *m, struct intel_panel *panel) +{ + const struct drm_display_mode *mode = panel->fixed_mode; + + seq_printf(m, "\tfixed mode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); +} + +static void intel_hdcp_info(struct seq_file *m, + struct intel_connector *intel_connector) +{ + bool hdcp_cap, hdcp2_cap; + + hdcp_cap = intel_hdcp_capable(intel_connector); + hdcp2_cap = intel_hdcp2_capable(intel_connector); + + if (hdcp_cap) + seq_puts(m, "HDCP1.4 "); + if (hdcp2_cap) + seq_puts(m, "HDCP2.2 "); + + if (!hdcp_cap && !hdcp2_cap) + seq_puts(m, "None"); + + seq_puts(m, "\n"); +} + +static void intel_dp_info(struct seq_file *m, + struct intel_connector *intel_connector) +{ + struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); + struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); + + seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); + seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); + if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) + intel_panel_info(m, &intel_connector->panel); + + drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, + &intel_dp->aux); + if (intel_connector->hdcp.shim) { + seq_puts(m, "\tHDCP version: "); + intel_hdcp_info(m, intel_connector); + } +} + +static void intel_dp_mst_info(struct seq_file *m, + struct intel_connector *intel_connector) +{ + struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); + struct intel_dp_mst_encoder *intel_mst = + enc_to_mst(intel_encoder); + struct intel_digital_port *intel_dig_port = intel_mst->primary; + struct intel_dp *intel_dp = &intel_dig_port->dp; + bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr, + intel_connector->port); + + seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); +} + +static void intel_hdmi_info(struct seq_file *m, + struct intel_connector *intel_connector) +{ + struct intel_encoder *intel_encoder = intel_attached_encoder(intel_connector); + struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(intel_encoder); + + seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); + if (intel_connector->hdcp.shim) { + seq_puts(m, "\tHDCP version: "); + intel_hdcp_info(m, intel_connector); + } +} + +static void intel_lvds_info(struct seq_file *m, + struct intel_connector *intel_connector) +{ + intel_panel_info(m, &intel_connector->panel); +} + +static void intel_connector_info(struct seq_file *m, + struct drm_connector *connector) +{ + struct intel_connector *intel_connector = to_intel_connector(connector); + const struct drm_connector_state *conn_state = connector->state; + struct intel_encoder *encoder = + to_intel_encoder(conn_state->best_encoder); + const struct drm_display_mode *mode; + + seq_printf(m, "[CONNECTOR:%d:%s]: status: %s\n", + connector->base.id, connector->name, + drm_get_connector_status_name(connector->status)); + + if (connector->status == connector_status_disconnected) + return; + + seq_printf(m, "\tphysical dimensions: %dx%dmm\n", + connector->display_info.width_mm, + connector->display_info.height_mm); + seq_printf(m, "\tsubpixel order: %s\n", + drm_get_subpixel_order_name(connector->display_info.subpixel_order)); + seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); + + if (!encoder) + return; + + switch (connector->connector_type) { + case DRM_MODE_CONNECTOR_DisplayPort: + case DRM_MODE_CONNECTOR_eDP: + if (encoder->type == INTEL_OUTPUT_DP_MST) + intel_dp_mst_info(m, intel_connector); + else + intel_dp_info(m, intel_connector); + break; + case DRM_MODE_CONNECTOR_LVDS: + if (encoder->type == INTEL_OUTPUT_LVDS) + intel_lvds_info(m, intel_connector); + break; + case DRM_MODE_CONNECTOR_HDMIA: + if (encoder->type == INTEL_OUTPUT_HDMI || + encoder->type == INTEL_OUTPUT_DDI) + intel_hdmi_info(m, intel_connector); + break; + default: + break; + } + + seq_printf(m, "\tmodes:\n"); + list_for_each_entry(mode, &connector->modes, head) + intel_seq_print_mode(m, 2, mode); +} + +static const char *plane_type(enum drm_plane_type type) +{ + switch (type) { + case DRM_PLANE_TYPE_OVERLAY: + return "OVL"; + case DRM_PLANE_TYPE_PRIMARY: + return "PRI"; + case DRM_PLANE_TYPE_CURSOR: + return "CUR"; + /* + * Deliberately omitting default: to generate compiler warnings + * when a new drm_plane_type gets added. + */ + } + + return "unknown"; +} + +static void plane_rotation(char *buf, size_t bufsize, unsigned int rotation) +{ + /* + * According to doc only one DRM_MODE_ROTATE_ is allowed but this + * will print them all to visualize if the values are misused + */ + snprintf(buf, bufsize, + "%s%s%s%s%s%s(0x%08x)", + (rotation & DRM_MODE_ROTATE_0) ? "0 " : "", + (rotation & DRM_MODE_ROTATE_90) ? "90 " : "", + (rotation & DRM_MODE_ROTATE_180) ? "180 " : "", + (rotation & DRM_MODE_ROTATE_270) ? "270 " : "", + (rotation & DRM_MODE_REFLECT_X) ? "FLIPX " : "", + (rotation & DRM_MODE_REFLECT_Y) ? "FLIPY " : "", + rotation); +} + +static void intel_plane_uapi_info(struct seq_file *m, struct intel_plane *plane) +{ + const struct intel_plane_state *plane_state = + to_intel_plane_state(plane->base.state); + const struct drm_framebuffer *fb = plane_state->uapi.fb; + struct drm_format_name_buf format_name; + struct drm_rect src, dst; + char rot_str[48]; + + src = drm_plane_state_src(&plane_state->uapi); + dst = drm_plane_state_dest(&plane_state->uapi); + + if (fb) + drm_get_format_name(fb->format->format, &format_name); + + plane_rotation(rot_str, sizeof(rot_str), + plane_state->uapi.rotation); + + seq_printf(m, "\t\tuapi: fb=%d,%s,%dx%d, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", + fb ? fb->base.id : 0, fb ? format_name.str : "n/a", + fb ? fb->width : 0, fb ? fb->height : 0, + DRM_RECT_FP_ARG(&src), + DRM_RECT_ARG(&dst), + rot_str); +} + +static void intel_plane_hw_info(struct seq_file *m, struct intel_plane *plane) +{ + const struct intel_plane_state *plane_state = + to_intel_plane_state(plane->base.state); + const struct drm_framebuffer *fb = plane_state->hw.fb; + struct drm_format_name_buf format_name; + char rot_str[48]; + + if (!fb) + return; + + drm_get_format_name(fb->format->format, &format_name); + + plane_rotation(rot_str, sizeof(rot_str), + plane_state->hw.rotation); + + seq_printf(m, "\t\thw: fb=%d,%s,%dx%d, visible=%s, src=" DRM_RECT_FP_FMT ", dst=" DRM_RECT_FMT ", rotation=%s\n", + fb->base.id, format_name.str, + fb->width, fb->height, + yesno(plane_state->uapi.visible), + DRM_RECT_FP_ARG(&plane_state->uapi.src), + DRM_RECT_ARG(&plane_state->uapi.dst), + rot_str); +} + +static void intel_plane_info(struct seq_file *m, struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct intel_plane *plane; + + for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) { + seq_printf(m, "\t[PLANE:%d:%s]: type=%s\n", + plane->base.base.id, plane->base.name, + plane_type(plane->base.type)); + intel_plane_uapi_info(m, plane); + intel_plane_hw_info(m, plane); + } +} + +static void intel_scaler_info(struct seq_file *m, struct intel_crtc *crtc) +{ + const struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + int num_scalers = crtc->num_scalers; + int i; + + /* Not all platformas have a scaler */ + if (num_scalers) { + seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", + num_scalers, + crtc_state->scaler_state.scaler_users, + crtc_state->scaler_state.scaler_id); + + for (i = 0; i < num_scalers; i++) { + const struct intel_scaler *sc = + &crtc_state->scaler_state.scalers[i]; + + seq_printf(m, ", scalers[%d]: use=%s, mode=%x", + i, yesno(sc->in_use), sc->mode); + } + seq_puts(m, "\n"); + } else { + seq_puts(m, "\tNo scalers available on this platform\n"); + } +} + +static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + const struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + struct intel_encoder *encoder; + + seq_printf(m, "[CRTC:%d:%s]:\n", + crtc->base.base.id, crtc->base.name); + + seq_printf(m, "\tuapi: enable=%s, active=%s, mode=" DRM_MODE_FMT "\n", + yesno(crtc_state->uapi.enable), + yesno(crtc_state->uapi.active), + DRM_MODE_ARG(&crtc_state->uapi.mode)); + + if (crtc_state->hw.enable) { + seq_printf(m, "\thw: active=%s, adjusted_mode=" DRM_MODE_FMT "\n", + yesno(crtc_state->hw.active), + DRM_MODE_ARG(&crtc_state->hw.adjusted_mode)); + + seq_printf(m, "\tpipe src size=%dx%d, dither=%s, bpp=%d\n", + crtc_state->pipe_src_w, crtc_state->pipe_src_h, + yesno(crtc_state->dither), crtc_state->pipe_bpp); + + intel_scaler_info(m, crtc); + } + + for_each_intel_encoder_mask(&dev_priv->drm, encoder, + crtc_state->uapi.encoder_mask) + intel_encoder_info(m, crtc, encoder); + + intel_plane_info(m, crtc); + + seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s\n", + yesno(!crtc->cpu_fifo_underrun_disabled), + yesno(!crtc->pch_fifo_underrun_disabled)); +} + +static int i915_display_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_device *dev = &dev_priv->drm; + struct intel_crtc *crtc; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + intel_wakeref_t wakeref; + + wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); + + drm_modeset_lock_all(dev); + + seq_printf(m, "CRTC info\n"); + seq_printf(m, "---------\n"); + for_each_intel_crtc(dev, crtc) + intel_crtc_info(m, crtc); + + seq_printf(m, "\n"); + seq_printf(m, "Connector info\n"); + seq_printf(m, "--------------\n"); + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) + intel_connector_info(m, connector); + drm_connector_list_iter_end(&conn_iter); + + drm_modeset_unlock_all(dev); + + intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); + + return 0; +} + +static int i915_shared_dplls_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_device *dev = &dev_priv->drm; + int i; + + drm_modeset_lock_all(dev); + + seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n", + dev_priv->dpll.ref_clks.nssc, + dev_priv->dpll.ref_clks.ssc); + + for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { + struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; + + seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, + pll->info->id); + seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", + pll->state.crtc_mask, pll->active_mask, yesno(pll->on)); + seq_printf(m, " tracked hardware state:\n"); + seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); + seq_printf(m, " dpll_md: 0x%08x\n", + pll->state.hw_state.dpll_md); + seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); + seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); + seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); + seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); + seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); + seq_printf(m, " mg_refclkin_ctl: 0x%08x\n", + pll->state.hw_state.mg_refclkin_ctl); + seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n", + pll->state.hw_state.mg_clktop2_coreclkctl1); + seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", + pll->state.hw_state.mg_clktop2_hsclkctl); + seq_printf(m, " mg_pll_div0: 0x%08x\n", + pll->state.hw_state.mg_pll_div0); + seq_printf(m, " mg_pll_div1: 0x%08x\n", + pll->state.hw_state.mg_pll_div1); + seq_printf(m, " mg_pll_lf: 0x%08x\n", + pll->state.hw_state.mg_pll_lf); + seq_printf(m, " mg_pll_frac_lock: 0x%08x\n", + pll->state.hw_state.mg_pll_frac_lock); + seq_printf(m, " mg_pll_ssc: 0x%08x\n", + pll->state.hw_state.mg_pll_ssc); + seq_printf(m, " mg_pll_bias: 0x%08x\n", + pll->state.hw_state.mg_pll_bias); + seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n", + pll->state.hw_state.mg_pll_tdc_coldst_bias); + } + drm_modeset_unlock_all(dev); + + return 0; +} + +static int i915_ipc_status_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + + seq_printf(m, "Isochronous Priority Control: %s\n", + yesno(dev_priv->ipc_enabled)); + return 0; +} + +static int i915_ipc_status_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + if (!HAS_IPC(dev_priv)) + return -ENODEV; + + return single_open(file, i915_ipc_status_show, dev_priv); +} + +static ssize_t i915_ipc_status_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + intel_wakeref_t wakeref; + bool enable; + int ret; + + ret = kstrtobool_from_user(ubuf, len, &enable); + if (ret < 0) + return ret; + + with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) { + if (!dev_priv->ipc_enabled && enable) + drm_info(&dev_priv->drm, + "Enabling IPC: WM will be proper only after next commit\n"); + dev_priv->wm.distrust_bios_wm = true; + dev_priv->ipc_enabled = enable; + intel_enable_ipc(dev_priv); + } + + return len; +} + +static const struct file_operations i915_ipc_status_fops = { + .owner = THIS_MODULE, + .open = i915_ipc_status_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_ipc_status_write +}; + +static int i915_ddb_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_device *dev = &dev_priv->drm; + struct skl_ddb_entry *entry; + struct intel_crtc *crtc; + + if (INTEL_GEN(dev_priv) < 9) + return -ENODEV; + + drm_modeset_lock_all(dev); + + seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); + + for_each_intel_crtc(&dev_priv->drm, crtc) { + struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + enum pipe pipe = crtc->pipe; + enum plane_id plane_id; + + seq_printf(m, "Pipe %c\n", pipe_name(pipe)); + + for_each_plane_id_on_crtc(crtc, plane_id) { + entry = &crtc_state->wm.skl.plane_ddb_y[plane_id]; + seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, + entry->start, entry->end, + skl_ddb_entry_size(entry)); + } + + entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; + seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, + entry->end, skl_ddb_entry_size(entry)); + } + + drm_modeset_unlock_all(dev); + + return 0; +} + +static void drrs_status_per_crtc(struct seq_file *m, + struct drm_device *dev, + struct intel_crtc *intel_crtc) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + struct i915_drrs *drrs = &dev_priv->drrs; + int vrefresh = 0; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + if (connector->state->crtc != &intel_crtc->base) + continue; + + seq_printf(m, "%s:\n", connector->name); + } + drm_connector_list_iter_end(&conn_iter); + + seq_puts(m, "\n"); + + if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { + struct intel_panel *panel; + + mutex_lock(&drrs->mutex); + /* DRRS Supported */ + seq_puts(m, "\tDRRS Supported: Yes\n"); + + /* disable_drrs() will make drrs->dp NULL */ + if (!drrs->dp) { + seq_puts(m, "Idleness DRRS: Disabled\n"); + if (dev_priv->psr.enabled) + seq_puts(m, + "\tAs PSR is enabled, DRRS is not enabled\n"); + mutex_unlock(&drrs->mutex); + return; + } + + panel = &drrs->dp->attached_connector->panel; + seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", + drrs->busy_frontbuffer_bits); + + seq_puts(m, "\n\t\t"); + if (drrs->refresh_rate_type == DRRS_HIGH_RR) { + seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n"); + vrefresh = panel->fixed_mode->vrefresh; + } else if (drrs->refresh_rate_type == DRRS_LOW_RR) { + seq_puts(m, "DRRS_State: DRRS_LOW_RR\n"); + vrefresh = panel->downclock_mode->vrefresh; + } else { + seq_printf(m, "DRRS_State: Unknown(%d)\n", + drrs->refresh_rate_type); + mutex_unlock(&drrs->mutex); + return; + } + seq_printf(m, "\t\tVrefresh: %d", vrefresh); + + seq_puts(m, "\n\t\t"); + mutex_unlock(&drrs->mutex); + } else { + /* DRRS not supported. Print the VBT parameter*/ + seq_puts(m, "\tDRRS Supported : No"); + } + seq_puts(m, "\n"); +} + +static int i915_drrs_status(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_device *dev = &dev_priv->drm; + struct intel_crtc *intel_crtc; + int active_crtc_cnt = 0; + + drm_modeset_lock_all(dev); + for_each_intel_crtc(dev, intel_crtc) { + if (intel_crtc->base.state->active) { + active_crtc_cnt++; + seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); + + drrs_status_per_crtc(m, dev, intel_crtc); + } + } + drm_modeset_unlock_all(dev); + + if (!active_crtc_cnt) + seq_puts(m, "No active crtc found\n"); + + return 0; +} + +static int i915_dp_mst_info(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + struct drm_device *dev = &dev_priv->drm; + struct intel_encoder *intel_encoder; + struct intel_digital_port *intel_dig_port; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) + continue; + + intel_encoder = intel_attached_encoder(to_intel_connector(connector)); + if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST) + continue; + + intel_dig_port = enc_to_dig_port(intel_encoder); + if (!intel_dig_port->dp.can_mst) + continue; + + seq_printf(m, "MST Source Port [ENCODER:%d:%s]\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); + drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr); + } + drm_connector_list_iter_end(&conn_iter); + + return 0; +} + +static ssize_t i915_displayport_test_active_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + char *input_buffer; + int status = 0; + struct drm_device *dev; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + struct intel_dp *intel_dp; + int val = 0; + + dev = ((struct seq_file *)file->private_data)->private; + + if (len == 0) + return 0; + + input_buffer = memdup_user_nul(ubuf, len); + if (IS_ERR(input_buffer)) + return PTR_ERR(input_buffer); + + drm_dbg(&to_i915(dev)->drm, + "Copied %d bytes from user\n", (unsigned int)len); + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + struct intel_encoder *encoder; + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + encoder = to_intel_encoder(connector->encoder); + if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) + continue; + + if (encoder && connector->status == connector_status_connected) { + intel_dp = enc_to_intel_dp(encoder); + status = kstrtoint(input_buffer, 10, &val); + if (status < 0) + break; + drm_dbg(&to_i915(dev)->drm, + "Got %d for test active\n", val); + /* To prevent erroneous activation of the compliance + * testing code, only accept an actual value of 1 here + */ + if (val == 1) + intel_dp->compliance.test_active = true; + else + intel_dp->compliance.test_active = false; + } + } + drm_connector_list_iter_end(&conn_iter); + kfree(input_buffer); + if (status < 0) + return status; + + *offp += len; + return len; +} + +static int i915_displayport_test_active_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + struct drm_device *dev = &dev_priv->drm; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + struct intel_dp *intel_dp; + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + struct intel_encoder *encoder; + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + encoder = to_intel_encoder(connector->encoder); + if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) + continue; + + if (encoder && connector->status == connector_status_connected) { + intel_dp = enc_to_intel_dp(encoder); + if (intel_dp->compliance.test_active) + seq_puts(m, "1"); + else + seq_puts(m, "0"); + } else + seq_puts(m, "0"); + } + drm_connector_list_iter_end(&conn_iter); + + return 0; +} + +static int i915_displayport_test_active_open(struct inode *inode, + struct file *file) +{ + return single_open(file, i915_displayport_test_active_show, + inode->i_private); +} + +static const struct file_operations i915_displayport_test_active_fops = { + .owner = THIS_MODULE, + .open = i915_displayport_test_active_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_displayport_test_active_write +}; + +static int i915_displayport_test_data_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + struct drm_device *dev = &dev_priv->drm; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + struct intel_dp *intel_dp; + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + struct intel_encoder *encoder; + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + encoder = to_intel_encoder(connector->encoder); + if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) + continue; + + if (encoder && connector->status == connector_status_connected) { + intel_dp = enc_to_intel_dp(encoder); + if (intel_dp->compliance.test_type == + DP_TEST_LINK_EDID_READ) + seq_printf(m, "%lx", + intel_dp->compliance.test_data.edid); + else if (intel_dp->compliance.test_type == + DP_TEST_LINK_VIDEO_PATTERN) { + seq_printf(m, "hdisplay: %d\n", + intel_dp->compliance.test_data.hdisplay); + seq_printf(m, "vdisplay: %d\n", + intel_dp->compliance.test_data.vdisplay); + seq_printf(m, "bpc: %u\n", + intel_dp->compliance.test_data.bpc); + } + } else + seq_puts(m, "0"); + } + drm_connector_list_iter_end(&conn_iter); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_data); + +static int i915_displayport_test_type_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + struct drm_device *dev = &dev_priv->drm; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + struct intel_dp *intel_dp; + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + struct intel_encoder *encoder; + + if (connector->connector_type != + DRM_MODE_CONNECTOR_DisplayPort) + continue; + + encoder = to_intel_encoder(connector->encoder); + if (encoder && encoder->type == INTEL_OUTPUT_DP_MST) + continue; + + if (encoder && connector->status == connector_status_connected) { + intel_dp = enc_to_intel_dp(encoder); + seq_printf(m, "%02lx", intel_dp->compliance.test_type); + } else + seq_puts(m, "0"); + } + drm_connector_list_iter_end(&conn_iter); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_displayport_test_type); + +static void wm_latency_show(struct seq_file *m, const u16 wm[8]) +{ + struct drm_i915_private *dev_priv = m->private; + struct drm_device *dev = &dev_priv->drm; + int level; + int num_levels; + + if (IS_CHERRYVIEW(dev_priv)) + num_levels = 3; + else if (IS_VALLEYVIEW(dev_priv)) + num_levels = 1; + else if (IS_G4X(dev_priv)) + num_levels = 3; + else + num_levels = ilk_wm_max_level(dev_priv) + 1; + + drm_modeset_lock_all(dev); + + for (level = 0; level < num_levels; level++) { + unsigned int latency = wm[level]; + + /* + * - WM1+ latency values in 0.5us units + * - latencies are in us on gen9/vlv/chv + */ + if (INTEL_GEN(dev_priv) >= 9 || + IS_VALLEYVIEW(dev_priv) || + IS_CHERRYVIEW(dev_priv) || + IS_G4X(dev_priv)) + latency *= 10; + else if (level > 0) + latency *= 5; + + seq_printf(m, "WM%d %u (%u.%u usec)\n", + level, wm[level], latency / 10, latency % 10); + } + + drm_modeset_unlock_all(dev); +} + +static int pri_wm_latency_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + const u16 *latencies; + + if (INTEL_GEN(dev_priv) >= 9) + latencies = dev_priv->wm.skl_latency; + else + latencies = dev_priv->wm.pri_latency; + + wm_latency_show(m, latencies); + + return 0; +} + +static int spr_wm_latency_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + const u16 *latencies; + + if (INTEL_GEN(dev_priv) >= 9) + latencies = dev_priv->wm.skl_latency; + else + latencies = dev_priv->wm.spr_latency; + + wm_latency_show(m, latencies); + + return 0; +} + +static int cur_wm_latency_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + const u16 *latencies; + + if (INTEL_GEN(dev_priv) >= 9) + latencies = dev_priv->wm.skl_latency; + else + latencies = dev_priv->wm.cur_latency; + + wm_latency_show(m, latencies); + + return 0; +} + +static int pri_wm_latency_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + return -ENODEV; + + return single_open(file, pri_wm_latency_show, dev_priv); +} + +static int spr_wm_latency_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + if (HAS_GMCH(dev_priv)) + return -ENODEV; + + return single_open(file, spr_wm_latency_show, dev_priv); +} + +static int cur_wm_latency_open(struct inode *inode, struct file *file) +{ + struct drm_i915_private *dev_priv = inode->i_private; + + if (HAS_GMCH(dev_priv)) + return -ENODEV; + + return single_open(file, cur_wm_latency_show, dev_priv); +} + +static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp, u16 wm[8]) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + struct drm_device *dev = &dev_priv->drm; + u16 new[8] = { 0 }; + int num_levels; + int level; + int ret; + char tmp[32]; + + if (IS_CHERRYVIEW(dev_priv)) + num_levels = 3; + else if (IS_VALLEYVIEW(dev_priv)) + num_levels = 1; + else if (IS_G4X(dev_priv)) + num_levels = 3; + else + num_levels = ilk_wm_max_level(dev_priv) + 1; + + if (len >= sizeof(tmp)) + return -EINVAL; + + if (copy_from_user(tmp, ubuf, len)) + return -EFAULT; + + tmp[len] = '\0'; + + ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu", + &new[0], &new[1], &new[2], &new[3], + &new[4], &new[5], &new[6], &new[7]); + if (ret != num_levels) + return -EINVAL; + + drm_modeset_lock_all(dev); + + for (level = 0; level < num_levels; level++) + wm[level] = new[level]; + + drm_modeset_unlock_all(dev); + + return len; +} + + +static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + u16 *latencies; + + if (INTEL_GEN(dev_priv) >= 9) + latencies = dev_priv->wm.skl_latency; + else + latencies = dev_priv->wm.pri_latency; + + return wm_latency_write(file, ubuf, len, offp, latencies); +} + +static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + u16 *latencies; + + if (INTEL_GEN(dev_priv) >= 9) + latencies = dev_priv->wm.skl_latency; + else + latencies = dev_priv->wm.spr_latency; + + return wm_latency_write(file, ubuf, len, offp, latencies); +} + +static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + u16 *latencies; + + if (INTEL_GEN(dev_priv) >= 9) + latencies = dev_priv->wm.skl_latency; + else + latencies = dev_priv->wm.cur_latency; + + return wm_latency_write(file, ubuf, len, offp, latencies); +} + +static const struct file_operations i915_pri_wm_latency_fops = { + .owner = THIS_MODULE, + .open = pri_wm_latency_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = pri_wm_latency_write +}; + +static const struct file_operations i915_spr_wm_latency_fops = { + .owner = THIS_MODULE, + .open = spr_wm_latency_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = spr_wm_latency_write +}; + +static const struct file_operations i915_cur_wm_latency_fops = { + .owner = THIS_MODULE, + .open = cur_wm_latency_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = cur_wm_latency_write +}; + +static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + struct i915_hotplug *hotplug = &dev_priv->hotplug; + + /* Synchronize with everything first in case there's been an HPD + * storm, but we haven't finished handling it in the kernel yet + */ + intel_synchronize_irq(dev_priv); + flush_work(&dev_priv->hotplug.dig_port_work); + flush_delayed_work(&dev_priv->hotplug.hotplug_work); + + seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); + seq_printf(m, "Detected: %s\n", + yesno(delayed_work_pending(&hotplug->reenable_work))); + + return 0; +} + +static ssize_t i915_hpd_storm_ctl_write(struct file *file, + const char __user *ubuf, size_t len, + loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + struct i915_hotplug *hotplug = &dev_priv->hotplug; + unsigned int new_threshold; + int i; + char *newline; + char tmp[16]; + + if (len >= sizeof(tmp)) + return -EINVAL; + + if (copy_from_user(tmp, ubuf, len)) + return -EFAULT; + + tmp[len] = '\0'; + + /* Strip newline, if any */ + newline = strchr(tmp, '\n'); + if (newline) + *newline = '\0'; + + if (strcmp(tmp, "reset") == 0) + new_threshold = HPD_STORM_DEFAULT_THRESHOLD; + else if (kstrtouint(tmp, 10, &new_threshold) != 0) + return -EINVAL; + + if (new_threshold > 0) + drm_dbg_kms(&dev_priv->drm, + "Setting HPD storm detection threshold to %d\n", + new_threshold); + else + drm_dbg_kms(&dev_priv->drm, "Disabling HPD storm detection\n"); + + spin_lock_irq(&dev_priv->irq_lock); + hotplug->hpd_storm_threshold = new_threshold; + /* Reset the HPD storm stats so we don't accidentally trigger a storm */ + for_each_hpd_pin(i) + hotplug->stats[i].count = 0; + spin_unlock_irq(&dev_priv->irq_lock); + + /* Re-enable hpd immediately if we were in an irq storm */ + flush_delayed_work(&dev_priv->hotplug.reenable_work); + + return len; +} + +static int i915_hpd_storm_ctl_open(struct inode *inode, struct file *file) +{ + return single_open(file, i915_hpd_storm_ctl_show, inode->i_private); +} + +static const struct file_operations i915_hpd_storm_ctl_fops = { + .owner = THIS_MODULE, + .open = i915_hpd_storm_ctl_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_hpd_storm_ctl_write +}; + +static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data) +{ + struct drm_i915_private *dev_priv = m->private; + + seq_printf(m, "Enabled: %s\n", + yesno(dev_priv->hotplug.hpd_short_storm_enabled)); + + return 0; +} + +static int +i915_hpd_short_storm_ctl_open(struct inode *inode, struct file *file) +{ + return single_open(file, i915_hpd_short_storm_ctl_show, + inode->i_private); +} + +static ssize_t i915_hpd_short_storm_ctl_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct drm_i915_private *dev_priv = m->private; + struct i915_hotplug *hotplug = &dev_priv->hotplug; + char *newline; + char tmp[16]; + int i; + bool new_state; + + if (len >= sizeof(tmp)) + return -EINVAL; + + if (copy_from_user(tmp, ubuf, len)) + return -EFAULT; + + tmp[len] = '\0'; + + /* Strip newline, if any */ + newline = strchr(tmp, '\n'); + if (newline) + *newline = '\0'; + + /* Reset to the "default" state for this system */ + if (strcmp(tmp, "reset") == 0) + new_state = !HAS_DP_MST(dev_priv); + else if (kstrtobool(tmp, &new_state) != 0) + return -EINVAL; + + drm_dbg_kms(&dev_priv->drm, "%sabling HPD short storm detection\n", + new_state ? "En" : "Dis"); + + spin_lock_irq(&dev_priv->irq_lock); + hotplug->hpd_short_storm_enabled = new_state; + /* Reset the HPD storm stats so we don't accidentally trigger a storm */ + for_each_hpd_pin(i) + hotplug->stats[i].count = 0; + spin_unlock_irq(&dev_priv->irq_lock); + + /* Re-enable hpd immediately if we were in an irq storm */ + flush_delayed_work(&dev_priv->hotplug.reenable_work); + + return len; +} + +static const struct file_operations i915_hpd_short_storm_ctl_fops = { + .owner = THIS_MODULE, + .open = i915_hpd_short_storm_ctl_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_hpd_short_storm_ctl_write, +}; + +static int i915_drrs_ctl_set(void *data, u64 val) +{ + struct drm_i915_private *dev_priv = data; + struct drm_device *dev = &dev_priv->drm; + struct intel_crtc *crtc; + + if (INTEL_GEN(dev_priv) < 7) + return -ENODEV; + + for_each_intel_crtc(dev, crtc) { + struct drm_connector_list_iter conn_iter; + struct intel_crtc_state *crtc_state; + struct drm_connector *connector; + struct drm_crtc_commit *commit; + int ret; + + ret = drm_modeset_lock_single_interruptible(&crtc->base.mutex); + if (ret) + return ret; + + crtc_state = to_intel_crtc_state(crtc->base.state); + + if (!crtc_state->hw.active || + !crtc_state->has_drrs) + goto out; + + commit = crtc_state->uapi.commit; + if (commit) { + ret = wait_for_completion_interruptible(&commit->hw_done); + if (ret) + goto out; + } + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + struct intel_encoder *encoder; + struct intel_dp *intel_dp; + + if (!(crtc_state->uapi.connector_mask & + drm_connector_mask(connector))) + continue; + + encoder = intel_attached_encoder(to_intel_connector(connector)); + if (encoder->type != INTEL_OUTPUT_EDP) + continue; + + drm_dbg(&dev_priv->drm, + "Manually %sabling DRRS. %llu\n", + val ? "en" : "dis", val); + + intel_dp = enc_to_intel_dp(encoder); + if (val) + intel_edp_drrs_enable(intel_dp, + crtc_state); + else + intel_edp_drrs_disable(intel_dp, + crtc_state); + } + drm_connector_list_iter_end(&conn_iter); + +out: + drm_modeset_unlock(&crtc->base.mutex); + if (ret) + return ret; + } + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(i915_drrs_ctl_fops, NULL, i915_drrs_ctl_set, "%llu\n"); + +static ssize_t +i915_fifo_underrun_reset_write(struct file *filp, + const char __user *ubuf, + size_t cnt, loff_t *ppos) +{ + struct drm_i915_private *dev_priv = filp->private_data; + struct intel_crtc *intel_crtc; + struct drm_device *dev = &dev_priv->drm; + int ret; + bool reset; + + ret = kstrtobool_from_user(ubuf, cnt, &reset); + if (ret) + return ret; + + if (!reset) + return cnt; + + for_each_intel_crtc(dev, intel_crtc) { + struct drm_crtc_commit *commit; + struct intel_crtc_state *crtc_state; + + ret = drm_modeset_lock_single_interruptible(&intel_crtc->base.mutex); + if (ret) + return ret; + + crtc_state = to_intel_crtc_state(intel_crtc->base.state); + commit = crtc_state->uapi.commit; + if (commit) { + ret = wait_for_completion_interruptible(&commit->hw_done); + if (!ret) + ret = wait_for_completion_interruptible(&commit->flip_done); + } + + if (!ret && crtc_state->hw.active) { + drm_dbg_kms(&dev_priv->drm, + "Re-arming FIFO underruns on pipe %c\n", + pipe_name(intel_crtc->pipe)); + + intel_crtc_arm_fifo_underrun(intel_crtc, crtc_state); + } + + drm_modeset_unlock(&intel_crtc->base.mutex); + + if (ret) + return ret; + } + + ret = intel_fbc_reset_underrun(dev_priv); + if (ret) + return ret; + + return cnt; +} + +static const struct file_operations i915_fifo_underrun_reset_ops = { + .owner = THIS_MODULE, + .open = simple_open, + .write = i915_fifo_underrun_reset_write, + .llseek = default_llseek, +}; + +static const struct drm_info_list intel_display_debugfs_list[] = { + {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0}, + {"i915_fbc_status", i915_fbc_status, 0}, + {"i915_ips_status", i915_ips_status, 0}, + {"i915_sr_status", i915_sr_status, 0}, + {"i915_opregion", i915_opregion, 0}, + {"i915_vbt", i915_vbt, 0}, + {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, + {"i915_edp_psr_status", i915_edp_psr_status, 0}, + {"i915_power_domain_info", i915_power_domain_info, 0}, + {"i915_dmc_info", i915_dmc_info, 0}, + {"i915_display_info", i915_display_info, 0}, + {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, + {"i915_dp_mst_info", i915_dp_mst_info, 0}, + {"i915_ddb_info", i915_ddb_info, 0}, + {"i915_drrs_status", i915_drrs_status, 0}, +}; + +static const struct { + const char *name; + const struct file_operations *fops; +} intel_display_debugfs_files[] = { + {"i915_fifo_underrun_reset", &i915_fifo_underrun_reset_ops}, + {"i915_pri_wm_latency", &i915_pri_wm_latency_fops}, + {"i915_spr_wm_latency", &i915_spr_wm_latency_fops}, + {"i915_cur_wm_latency", &i915_cur_wm_latency_fops}, + {"i915_fbc_false_color", &i915_fbc_false_color_fops}, + {"i915_dp_test_data", &i915_displayport_test_data_fops}, + {"i915_dp_test_type", &i915_displayport_test_type_fops}, + {"i915_dp_test_active", &i915_displayport_test_active_fops}, + {"i915_hpd_storm_ctl", &i915_hpd_storm_ctl_fops}, + {"i915_hpd_short_storm_ctl", &i915_hpd_short_storm_ctl_fops}, + {"i915_ipc_status", &i915_ipc_status_fops}, + {"i915_drrs_ctl", &i915_drrs_ctl_fops}, + {"i915_edp_psr_debug", &i915_edp_psr_debug_fops}, +}; + +int intel_display_debugfs_register(struct drm_i915_private *i915) +{ + struct drm_minor *minor = i915->drm.primary; + int i; + + for (i = 0; i < ARRAY_SIZE(intel_display_debugfs_files); i++) { + debugfs_create_file(intel_display_debugfs_files[i].name, + S_IRUGO | S_IWUSR, + minor->debugfs_root, + to_i915(minor->dev), + intel_display_debugfs_files[i].fops); + } + + return drm_debugfs_create_files(intel_display_debugfs_list, + ARRAY_SIZE(intel_display_debugfs_list), + minor->debugfs_root, minor); +} + +static int i915_panel_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct intel_dp *intel_dp = + intel_attached_dp(to_intel_connector(connector)); + + if (connector->status != connector_status_connected) + return -ENODEV; + + seq_printf(m, "Panel power up delay: %d\n", + intel_dp->panel_power_up_delay); + seq_printf(m, "Panel power down delay: %d\n", + intel_dp->panel_power_down_delay); + seq_printf(m, "Backlight on delay: %d\n", + intel_dp->backlight_on_delay); + seq_printf(m, "Backlight off delay: %d\n", + intel_dp->backlight_off_delay); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_panel); + +static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct intel_connector *intel_connector = to_intel_connector(connector); + + if (connector->status != connector_status_connected) + return -ENODEV; + + /* HDCP is supported by connector */ + if (!intel_connector->hdcp.shim) + return -EINVAL; + + seq_printf(m, "%s:%d HDCP version: ", connector->name, + connector->base.id); + intel_hdcp_info(m, intel_connector); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_hdcp_sink_capability); + +static int i915_dsc_fec_support_show(struct seq_file *m, void *data) +{ + struct drm_connector *connector = m->private; + struct drm_device *dev = connector->dev; + struct drm_crtc *crtc; + struct intel_dp *intel_dp; + struct drm_modeset_acquire_ctx ctx; + struct intel_crtc_state *crtc_state = NULL; + int ret = 0; + bool try_again = false; + + drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); + + do { + try_again = false; + ret = drm_modeset_lock(&dev->mode_config.connection_mutex, + &ctx); + if (ret) { + if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { + try_again = true; + continue; + } + break; + } + crtc = connector->state->crtc; + if (connector->status != connector_status_connected || !crtc) { + ret = -ENODEV; + break; + } + ret = drm_modeset_lock(&crtc->mutex, &ctx); + if (ret == -EDEADLK) { + ret = drm_modeset_backoff(&ctx); + if (!ret) { + try_again = true; + continue; + } + break; + } else if (ret) { + break; + } + intel_dp = intel_attached_dp(to_intel_connector(connector)); + crtc_state = to_intel_crtc_state(crtc->state); + seq_printf(m, "DSC_Enabled: %s\n", + yesno(crtc_state->dsc.compression_enable)); + seq_printf(m, "DSC_Sink_Support: %s\n", + yesno(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); + seq_printf(m, "Force_DSC_Enable: %s\n", + yesno(intel_dp->force_dsc_en)); + if (!intel_dp_is_edp(intel_dp)) + seq_printf(m, "FEC_Sink_Support: %s\n", + yesno(drm_dp_sink_supports_fec(intel_dp->fec_capable))); + } while (try_again); + + drm_modeset_drop_locks(&ctx); + drm_modeset_acquire_fini(&ctx); + + return ret; +} + +static ssize_t i915_dsc_fec_support_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + bool dsc_enable = false; + int ret; + struct drm_connector *connector = + ((struct seq_file *)file->private_data)->private; + struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector)); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + if (len == 0) + return 0; + + drm_dbg(&i915->drm, + "Copied %zu bytes from user to force DSC\n", len); + + ret = kstrtobool_from_user(ubuf, len, &dsc_enable); + if (ret < 0) + return ret; + + drm_dbg(&i915->drm, "Got %s for DSC Enable\n", + (dsc_enable) ? "true" : "false"); + intel_dp->force_dsc_en = dsc_enable; + + *offp += len; + return len; +} + +static int i915_dsc_fec_support_open(struct inode *inode, + struct file *file) +{ + return single_open(file, i915_dsc_fec_support_show, + inode->i_private); +} + +static const struct file_operations i915_dsc_fec_support_fops = { + .owner = THIS_MODULE, + .open = i915_dsc_fec_support_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = i915_dsc_fec_support_write +}; + +/** + * intel_connector_debugfs_add - add i915 specific connector debugfs files + * @connector: pointer to a registered drm_connector + * + * Cleanup will be done by drm_connector_unregister() through a call to + * drm_debugfs_connector_remove(). + * + * Returns 0 on success, negative error codes on error. + */ +int intel_connector_debugfs_add(struct drm_connector *connector) +{ + struct dentry *root = connector->debugfs_entry; + struct drm_i915_private *dev_priv = to_i915(connector->dev); + + /* The connector must have been registered beforehands. */ + if (!root) + return -ENODEV; + + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { + debugfs_create_file("i915_panel_timings", S_IRUGO, root, + connector, &i915_panel_fops); + debugfs_create_file("i915_psr_sink_status", S_IRUGO, root, + connector, &i915_psr_sink_status_fops); + } + + if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || + connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || + connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) { + debugfs_create_file("i915_hdcp_sink_capability", S_IRUGO, root, + connector, &i915_hdcp_sink_capability_fops); + } + + if (INTEL_GEN(dev_priv) >= 10 && + (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || + connector->connector_type == DRM_MODE_CONNECTOR_eDP)) + debugfs_create_file("i915_dsc_fec_support", S_IRUGO, root, + connector, &i915_dsc_fec_support_fops); + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.h b/drivers/gpu/drm/i915/display/intel_display_debugfs.h new file mode 100644 index 000000000000..a3bea1ce04c2 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef __INTEL_DISPLAY_DEBUGFS_H__ +#define __INTEL_DISPLAY_DEBUGFS_H__ + +struct drm_connector; +struct drm_i915_private; + +#ifdef CONFIG_DEBUG_FS +int intel_display_debugfs_register(struct drm_i915_private *i915); +int intel_connector_debugfs_add(struct drm_connector *connector); +#else +static inline int intel_display_debugfs_register(struct drm_i915_private *i915) { return 0; } +static inline int intel_connector_debugfs_add(struct drm_connector *connector) { return 0; } +#endif + +#endif /* __INTEL_DISPLAY_DEBUGFS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 46c40db992dd..246e406bb385 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -15,6 +15,7 @@ #include "intel_display_types.h" #include "intel_dpio_phy.h" #include "intel_hotplug.h" +#include "intel_pm.h" #include "intel_sideband.h" #include "intel_tc.h" #include "intel_vga.h" @@ -159,7 +160,7 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) static void intel_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name); + drm_dbg_kms(&dev_priv->drm, "enabling %s\n", power_well->desc->name); power_well->desc->ops->enable(dev_priv, power_well); power_well->hw_enabled = true; } @@ -167,7 +168,7 @@ static void intel_power_well_enable(struct drm_i915_private *dev_priv, static void intel_power_well_disable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name); + drm_dbg_kms(&dev_priv->drm, "disabling %s\n", power_well->desc->name); power_well->hw_enabled = false; power_well->desc->ops->disable(dev_priv, power_well); } @@ -182,8 +183,9 @@ static void intel_power_well_get(struct drm_i915_private *dev_priv, static void intel_power_well_put(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - WARN(!power_well->count, "Use count on power well %s is already zero", - power_well->desc->name); + drm_WARN(&dev_priv->drm, !power_well->count, + "Use count on power well %s is already zero", + power_well->desc->name); if (!--power_well->count) intel_power_well_disable(dev_priv, power_well); @@ -289,11 +291,11 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */ if (intel_de_wait_for_set(dev_priv, regs->driver, HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) { - DRM_DEBUG_KMS("%s power well enable timeout\n", - power_well->desc->name); + drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n", + power_well->desc->name); /* An AUX timeout is expected if the TBT DP tunnel is down. */ - WARN_ON(!power_well->desc->hsw.is_tc_tbt); + drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt); } } @@ -304,11 +306,11 @@ static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); u32 ret; - ret = I915_READ(regs->bios) & req_mask ? 1 : 0; - ret |= I915_READ(regs->driver) & req_mask ? 2 : 0; + ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; + ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; if (regs->kvmr.reg) - ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0; - ret |= I915_READ(regs->debug) & req_mask ? 8 : 0; + ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; + ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; return ret; } @@ -330,23 +332,25 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, * Skip the wait in case any of the request bits are set and print a * diagnostic message. */ - wait_for((disabled = !(I915_READ(regs->driver) & + wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & HSW_PWR_WELL_CTL_STATE(pw_idx))) || (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); if (disabled) return; - DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", - power_well->desc->name, - !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); + drm_dbg_kms(&dev_priv->drm, + "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n", + power_well->desc->name, + !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8)); } static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, enum skl_power_gate pg) { /* Timeout 5us for PG#0, for other PGs 1us */ - WARN_ON(intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, - SKL_FUSE_PG_DIST_STATUS(pg), 1)); + drm_WARN_ON(&dev_priv->drm, + intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS, + SKL_FUSE_PG_DIST_STATUS(pg), 1)); } static void hsw_power_well_enable(struct drm_i915_private *dev_priv, @@ -372,17 +376,18 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); } - val = I915_READ(regs->driver); - I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); + val = intel_de_read(dev_priv, regs->driver); + intel_de_write(dev_priv, regs->driver, + val | HSW_PWR_WELL_CTL_REQ(pw_idx)); hsw_wait_for_power_well_enable(dev_priv, power_well); /* Display WA #1178: cnl */ if (IS_CANNONLAKE(dev_priv) && pw_idx >= GLK_PW_CTL_IDX_AUX_B && pw_idx <= CNL_PW_CTL_IDX_AUX_F) { - val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx)); + val = intel_de_read(dev_priv, CNL_AUX_ANAOVRD1(pw_idx)); val |= CNL_AUX_ANAOVRD1_ENABLE | CNL_AUX_ANAOVRD1_LDO_BYPASS; - I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val); + intel_de_write(dev_priv, CNL_AUX_ANAOVRD1(pw_idx), val); } if (wait_fuses) @@ -403,8 +408,9 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv, hsw_power_well_pre_disable(dev_priv, power_well->desc->hsw.irq_pipe_mask); - val = I915_READ(regs->driver); - I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); + val = intel_de_read(dev_priv, regs->driver); + intel_de_write(dev_priv, regs->driver, + val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); hsw_wait_for_power_well_disable(dev_priv, power_well); } @@ -419,14 +425,16 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); u32 val; - WARN_ON(!IS_ICELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); - val = I915_READ(regs->driver); - I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); + val = intel_de_read(dev_priv, regs->driver); + intel_de_write(dev_priv, regs->driver, + val | HSW_PWR_WELL_CTL_REQ(pw_idx)); if (INTEL_GEN(dev_priv) < 12) { - val = I915_READ(ICL_PORT_CL_DW12(phy)); - I915_WRITE(ICL_PORT_CL_DW12(phy), val | ICL_LANE_ENABLE_AUX); + val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); + intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), + val | ICL_LANE_ENABLE_AUX); } hsw_wait_for_power_well_enable(dev_priv, power_well); @@ -434,9 +442,9 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, /* Display WA #1178: icl */ if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B && !intel_bios_is_port_edp(dev_priv, (enum port)phy)) { - val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); + val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx)); val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS; - I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); + intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val); } } @@ -449,13 +457,15 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); u32 val; - WARN_ON(!IS_ICELAKE(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); - val = I915_READ(ICL_PORT_CL_DW12(phy)); - I915_WRITE(ICL_PORT_CL_DW12(phy), val & ~ICL_LANE_ENABLE_AUX); + val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy)); + intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy), + val & ~ICL_LANE_ENABLE_AUX); - val = I915_READ(regs->driver); - I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); + val = intel_de_read(dev_priv, regs->driver); + intel_de_write(dev_priv, regs->driver, + val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); hsw_wait_for_power_well_disable(dev_priv, power_well); } @@ -485,7 +495,7 @@ static int power_well_async_ref_count(struct drm_i915_private *dev_priv, int refs = hweight64(power_well->desc->domains & async_put_domains_mask(&dev_priv->power_domains)); - WARN_ON(refs > power_well->count); + drm_WARN_ON(&dev_priv->drm, refs > power_well->count); return refs; } @@ -515,7 +525,7 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, continue; dig_port = enc_to_dig_port(encoder); - if (WARN_ON(!dig_port)) + if (drm_WARN_ON(&dev_priv->drm, !dig_port)) continue; if (dig_port->aux_ch != aux_ch) { @@ -526,10 +536,10 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv, break; } - if (WARN_ON(!dig_port)) + if (drm_WARN_ON(&dev_priv->drm, !dig_port)) return; - WARN_ON(!intel_tc_port_ref_held(dig_port)); + drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port)); } #else @@ -552,11 +562,11 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, icl_tc_port_assert_ref_held(dev_priv, power_well); - val = I915_READ(DP_AUX_CH_CTL(aux_ch)); + val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch)); val &= ~DP_AUX_CH_CTL_TBT_IO; if (power_well->desc->hsw.is_tc_tbt) val |= DP_AUX_CH_CTL_TBT_IO; - I915_WRITE(DP_AUX_CH_CTL(aux_ch), val); + intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val); hsw_power_well_enable(dev_priv, power_well); @@ -564,11 +574,13 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, enum tc_port tc_port; tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx); - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x2)); if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port), DKL_CMN_UC_DW27_UC_HEALTH, 1)) - DRM_WARN("Timeout waiting TC uC health\n"); + drm_warn(&dev_priv->drm, + "Timeout waiting TC uC health\n"); } } @@ -596,7 +608,7 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, HSW_PWR_WELL_CTL_STATE(pw_idx); u32 val; - val = I915_READ(regs->driver); + val = intel_de_read(dev_priv, regs->driver); /* * On GEN9 big core due to a DMC bug the driver's request bits for PW1 @@ -606,22 +618,26 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, */ if (IS_GEN(dev_priv, 9) && !IS_GEN9_LP(dev_priv) && (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO)) - val |= I915_READ(regs->bios); + val |= intel_de_read(dev_priv, regs->bios); return (val & mask) == mask; } static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) { - WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), - "DC9 already programmed to be enabled.\n"); - WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, - "DC5 still not disabled to enable DC9.\n"); - WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL2) & - HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), - "Power well 2 on.\n"); - WARN_ONCE(intel_irqs_enabled(dev_priv), - "Interrupts not disabled yet.\n"); + drm_WARN_ONCE(&dev_priv->drm, + (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), + "DC9 already programmed to be enabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC5, + "DC5 still not disabled to enable DC9.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & + HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2), + "Power well 2 on.\n"); + drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), + "Interrupts not disabled yet.\n"); /* * TODO: check for the following to verify the conditions to enter DC9 @@ -634,10 +650,12 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) { - WARN_ONCE(intel_irqs_enabled(dev_priv), - "Interrupts not disabled yet.\n"); - WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, - "DC5 still not disabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), + "Interrupts not disabled yet.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC5, + "DC5 still not disabled.\n"); /* * TODO: check for the following to verify DC9 state was indeed @@ -655,7 +673,7 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, int rereads = 0; u32 v; - I915_WRITE(DC_STATE_EN, state); + intel_de_write(dev_priv, DC_STATE_EN, state); /* It has been observed that disabling the dc6 state sometimes * doesn't stick and dmc keeps returning old value. Make sure @@ -663,10 +681,10 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, * we are confident that state is exactly what we want. */ do { - v = I915_READ(DC_STATE_EN); + v = intel_de_read(dev_priv, DC_STATE_EN); if (v != state) { - I915_WRITE(DC_STATE_EN, state); + intel_de_write(dev_priv, DC_STATE_EN, state); rewrites++; rereads = 0; } else if (rereads++ > 5) { @@ -676,13 +694,15 @@ static void gen9_write_dc_state(struct drm_i915_private *dev_priv, } while (rewrites < 100); if (v != state) - DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", - state, v); + drm_err(&dev_priv->drm, + "Writing dc state to 0x%x failed, now 0x%x\n", + state, v); /* Most of the times we need one retry, avoid spam */ if (rewrites > 1) - DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", - state, rewrites); + drm_dbg_kms(&dev_priv->drm, + "Rewrote dc state to 0x%x %d times\n", + state, rewrites); } static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) @@ -708,10 +728,11 @@ static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) { u32 val; - val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); + val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv); - DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", - dev_priv->csr.dc_state, val); + drm_dbg_kms(&dev_priv->drm, + "Resetting DC state tracking from %02x to %02x\n", + dev_priv->csr.dc_state, val); dev_priv->csr.dc_state = val; } @@ -743,18 +764,19 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state) u32 val; u32 mask; - if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, + state & ~dev_priv->csr.allowed_dc_mask)) state &= dev_priv->csr.allowed_dc_mask; - val = I915_READ(DC_STATE_EN); + val = intel_de_read(dev_priv, DC_STATE_EN); mask = gen9_dc_mask(dev_priv); - DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", - val & mask, state); + drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n", + val & mask, state); /* Check if DMC is ignoring our DC state requests */ if ((val & mask) != dev_priv->csr.dc_state) - DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", - dev_priv->csr.dc_state, val & mask); + drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n", + dev_priv->csr.dc_state, val & mask); val &= ~mask; val |= state; @@ -791,7 +813,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv, static void tgl_enable_dc3co(struct drm_i915_private *dev_priv) { - DRM_DEBUG_KMS("Enabling DC3CO\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n"); gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO); } @@ -799,10 +821,10 @@ static void tgl_disable_dc3co(struct drm_i915_private *dev_priv) { u32 val; - DRM_DEBUG_KMS("Disabling DC3CO\n"); - val = I915_READ(DC_STATE_EN); + drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n"); + val = intel_de_read(dev_priv, DC_STATE_EN); val &= ~DC_STATE_DC3CO_STATUS; - I915_WRITE(DC_STATE_EN, val); + intel_de_write(dev_priv, DC_STATE_EN, val); gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); /* * Delay of 200us DC3CO Exit time B.Spec 49196 @@ -814,7 +836,7 @@ static void bxt_enable_dc9(struct drm_i915_private *dev_priv) { assert_can_enable_dc9(dev_priv); - DRM_DEBUG_KMS("Enabling DC9\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n"); /* * Power sequencer reset is not needed on * platforms with South Display Engine on PCH, @@ -829,7 +851,7 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv) { assert_can_disable_dc9(dev_priv); - DRM_DEBUG_KMS("Disabling DC9\n"); + drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n"); gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); @@ -838,10 +860,13 @@ static void bxt_disable_dc9(struct drm_i915_private *dev_priv) static void assert_csr_loaded(struct drm_i915_private *dev_priv) { - WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), - "CSR program storage start is NULL\n"); - WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); - WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); + drm_WARN_ONCE(&dev_priv->drm, + !intel_de_read(dev_priv, CSR_PROGRAM(0)), + "CSR program storage start is NULL\n"); + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_SSP_BASE), + "CSR SSP Base Not fine\n"); + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, CSR_HTP_SKL), + "CSR HTP Not fine\n"); } static struct i915_power_well * @@ -861,7 +886,9 @@ lookup_power_well(struct drm_i915_private *dev_priv, * the first power well and hope the WARN gets reported so we can fix * our driver. */ - WARN(1, "Power well %d not defined for this platform\n", power_well_id); + drm_WARN(&dev_priv->drm, 1, + "Power well %d not defined for this platform\n", + power_well_id); return &dev_priv->power_domains.power_wells[0]; } @@ -884,7 +911,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, mutex_lock(&power_domains->lock); power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF); - if (WARN_ON(!power_well)) + if (drm_WARN_ON(&dev_priv->drm, !power_well)) goto unlock; state = sanitize_target_dc_state(dev_priv, state); @@ -912,13 +939,22 @@ unlock: static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) { - bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, - SKL_DISP_PW_2); + enum i915_power_well_id high_pg; - WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); + /* Power wells at this level and above must be disabled for DC5 entry */ + if (INTEL_GEN(dev_priv) >= 12) + high_pg = TGL_DISP_PW_3; + else + high_pg = SKL_DISP_PW_2; - WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), - "DC5 already programmed to be enabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_display_power_well_is_enabled(dev_priv, high_pg), + "Power wells above platform's DC5 limit still enabled.\n"); + + drm_WARN_ONCE(&dev_priv->drm, + (intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC5), + "DC5 already programmed to be enabled.\n"); assert_rpm_wakelock_held(&dev_priv->runtime_pm); assert_csr_loaded(dev_priv); @@ -928,22 +964,25 @@ static void gen9_enable_dc5(struct drm_i915_private *dev_priv) { assert_can_enable_dc5(dev_priv); - DRM_DEBUG_KMS("Enabling DC5\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n"); /* Wa Display #1183: skl,kbl,cfl */ if (IS_GEN9_BC(dev_priv)) - I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | - SKL_SELECT_ALTERNATE_DC_EXIT); + intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1, + intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); } static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) { - WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, - "Backlight is not disabled.\n"); - WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), - "DC6 already programmed to be enabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE, + "Backlight is not disabled.\n"); + drm_WARN_ONCE(&dev_priv->drm, + (intel_de_read(dev_priv, DC_STATE_EN) & + DC_STATE_EN_UPTO_DC6), + "DC6 already programmed to be enabled.\n"); assert_csr_loaded(dev_priv); } @@ -952,12 +991,12 @@ static void skl_enable_dc6(struct drm_i915_private *dev_priv) { assert_can_enable_dc6(dev_priv); - DRM_DEBUG_KMS("Enabling DC6\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n"); /* Wa Display #1183: skl,kbl,cfl */ if (IS_GEN9_BC(dev_priv)) - I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | - SKL_SELECT_ALTERNATE_DC_EXIT); + intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1, + intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); } @@ -968,15 +1007,15 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, const struct i915_power_well_regs *regs = power_well->desc->hsw.regs; int pw_idx = power_well->desc->hsw.idx; u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); - u32 bios_req = I915_READ(regs->bios); + u32 bios_req = intel_de_read(dev_priv, regs->bios); /* Take over the request bit if set by BIOS. */ if (bios_req & mask) { - u32 drv_req = I915_READ(regs->driver); + u32 drv_req = intel_de_read(dev_priv, regs->driver); if (!(drv_req & mask)) - I915_WRITE(regs->driver, drv_req | mask); - I915_WRITE(regs->bios, bios_req & ~mask); + intel_de_write(dev_priv, regs->driver, drv_req | mask); + intel_de_write(dev_priv, regs->bios, bios_req & ~mask); } } @@ -1022,22 +1061,25 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && - (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); + return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 && + (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0); } static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) { - u32 tmp = I915_READ(DBUF_CTL); + u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv); + u8 enabled_dbuf_slices = dev_priv->enabled_dbuf_slices_mask; - WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) != - (DBUF_POWER_STATE | DBUF_POWER_REQUEST), - "Unexpected DBuf power power state (0x%08x)\n", tmp); + drm_WARN(&dev_priv->drm, + hw_enabled_dbuf_slices != enabled_dbuf_slices, + "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n", + hw_enabled_dbuf_slices, + enabled_dbuf_slices); } static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) { - struct intel_cdclk_state cdclk_state = {}; + struct intel_cdclk_config cdclk_config = {}; if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) { tgl_disable_dc3co(dev_priv); @@ -1046,9 +1088,11 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); - dev_priv->display.get_cdclk(dev_priv, &cdclk_state); + dev_priv->display.get_cdclk(dev_priv, &cdclk_config); /* Can't read out voltage_level so can't use intel_cdclk_changed() */ - WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); + drm_WARN_ON(&dev_priv->drm, + intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, + &cdclk_config)); gen9_assert_dbuf_enabled(dev_priv); @@ -1108,9 +1152,9 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) + if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0) i830_enable_pipe(dev_priv, PIPE_A); - if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) + if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) i830_enable_pipe(dev_priv, PIPE_B); } @@ -1124,8 +1168,8 @@ static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE && - I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; + return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE && + intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; } static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, @@ -1163,9 +1207,10 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv, vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); if (wait_for(COND, 100)) - DRM_ERROR("timeout setting power well state %08x (%08x)\n", - state, - vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); + drm_err(&dev_priv->drm, + "timeout setting power well state %08x (%08x)\n", + state, + vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); #undef COND @@ -1204,8 +1249,8 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, * We only ever set the power-on and power-gate states, anything * else is unexpected. */ - WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) && - state != PUNIT_PWRGT_PWR_GATE(pw_idx)); + drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) && + state != PUNIT_PWRGT_PWR_GATE(pw_idx)); if (state == ctrl) enabled = true; @@ -1214,7 +1259,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, * is poking at the power controls too. */ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; - WARN_ON(ctrl != state); + drm_WARN_ON(&dev_priv->drm, ctrl != state); vlv_punit_put(dev_priv); @@ -1231,21 +1276,22 @@ static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) * (and never recovering) in this case. intel_dsi_post_disable() will * clear it when we turn off the display. */ - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); val &= DPOUNIT_CLOCK_GATE_DISABLE; val |= VRHUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); /* * Disable trickle feed and enable pnd deadline calculation */ - I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); - I915_WRITE(CBR1_VLV, 0); - - WARN_ON(dev_priv->rawclk_freq == 0); + intel_de_write(dev_priv, MI_ARB_VLV, + MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); + intel_de_write(dev_priv, CBR1_VLV, 0); - I915_WRITE(RAWCLK_FREQ_VLV, - DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); + drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0); + intel_de_write(dev_priv, RAWCLK_FREQ_VLV, + DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, + 1000)); } static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) @@ -1262,13 +1308,13 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) * CHV DPLL B/C have some issues if VGA mode is enabled. */ for_each_pipe(dev_priv, pipe) { - u32 val = I915_READ(DPLL(pipe)); + u32 val = intel_de_read(dev_priv, DPLL(pipe)); val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - I915_WRITE(DPLL(pipe), val); + intel_de_write(dev_priv, DPLL(pipe), val); } vlv_init_display_clock_gating(dev_priv); @@ -1348,7 +1394,8 @@ static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, * both PLLs disabled, or we risk losing DPIO and PLL * synchronization. */ - I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); + intel_de_write(dev_priv, DPIO_CTL, + intel_de_read(dev_priv, DPIO_CTL) | DPIO_CMNRST); } static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, @@ -1360,7 +1407,8 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, assert_pll_disabled(dev_priv, pipe); /* Assert common reset */ - I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); + intel_de_write(dev_priv, DPIO_CTL, + intel_de_read(dev_priv, DPIO_CTL) & ~DPIO_CMNRST); vlv_set_power_well(dev_priv, power_well, false); } @@ -1422,7 +1470,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) */ if (BITS_SET(phy_control, PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && - (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) + (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); if (BITS_SET(phy_control, @@ -1467,9 +1515,10 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) */ if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS, phy_status_mask, phy_status, 10)) - DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", - I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask, - phy_status, dev_priv->chv_phy_control); + drm_err(&dev_priv->drm, + "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", + intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask, + phy_status, dev_priv->chv_phy_control); } #undef BITS_SET @@ -1481,8 +1530,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, enum pipe pipe; u32 tmp; - WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && - power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); + drm_WARN_ON_ONCE(&dev_priv->drm, + power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && + power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) { pipe = PIPE_A; @@ -1499,7 +1549,8 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, /* Poll for phypwrgood signal */ if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS, PHY_POWERGOOD(phy), 1)) - DRM_ERROR("Display PHY %d is not power up\n", phy); + drm_err(&dev_priv->drm, "Display PHY %d is not power up\n", + phy); vlv_dpio_get(dev_priv); @@ -1527,10 +1578,12 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, vlv_dpio_put(dev_priv); dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); - I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, + dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", - phy, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", + phy, dev_priv->chv_phy_control); assert_chv_phy_status(dev_priv); } @@ -1540,8 +1593,9 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, { enum dpio_phy phy; - WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && - power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); + drm_WARN_ON_ONCE(&dev_priv->drm, + power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC && + power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D); if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) { phy = DPIO_PHY0; @@ -1553,12 +1607,14 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, } dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); - I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, + dev_priv->chv_phy_control); vlv_set_power_well(dev_priv, power_well, false); - DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", - phy, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", + phy, dev_priv->chv_phy_control); /* PHY is fully reset now, so we can enable the PHY state asserts */ dev_priv->chv_phy_assert[phy] = true; @@ -1621,11 +1677,13 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; - WARN(actual != expected, - "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", - !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), - !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), - reg, val); + drm_WARN(&dev_priv->drm, actual != expected, + "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", + !!(actual & DPIO_ALLDL_POWERDOWN), + !!(actual & DPIO_ANYDL_POWERDOWN), + !!(expected & DPIO_ALLDL_POWERDOWN), + !!(expected & DPIO_ANYDL_POWERDOWN), + reg, val); } bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, @@ -1646,10 +1704,12 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, else dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); - I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, + dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", - phy, ch, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", + phy, ch, dev_priv->chv_phy_control); assert_chv_phy_status(dev_priv); @@ -1677,10 +1737,12 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder, else dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); - I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, + dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", - phy, ch, mask, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, + "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", + phy, ch, mask, dev_priv->chv_phy_control); assert_chv_phy_status(dev_priv); @@ -1703,7 +1765,8 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, * We only ever set the power-on and power-gate states, anything * else is unexpected. */ - WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); + drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) && + state != DP_SSS_PWR_GATE(pipe)); enabled = state == DP_SSS_PWR_ON(pipe); /* @@ -1711,7 +1774,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, * is poking at the power controls too. */ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); - WARN_ON(ctrl << 16 != state); + drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state); vlv_punit_put(dev_priv); @@ -1742,9 +1805,10 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); if (wait_for(COND, 100)) - DRM_ERROR("timeout setting power well state %08x (%08x)\n", - state, - vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); + drm_err(&dev_priv->drm, + "timeout setting power well state %08x (%08x)\n", + state, + vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); #undef COND @@ -1752,6 +1816,13 @@ out: vlv_punit_put(dev_priv); } +static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, + struct i915_power_well *power_well) +{ + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL, + dev_priv->chv_phy_control); +} + static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { @@ -1981,12 +2052,13 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv, power_domains = &dev_priv->power_domains; - WARN(!power_domains->domain_use_count[domain], - "Use count on domain %s is already zero\n", - name); - WARN(async_put_domains_mask(power_domains) & BIT_ULL(domain), - "Async disabling of domain %s is pending\n", - name); + drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain], + "Use count on domain %s is already zero\n", + name); + drm_WARN(&dev_priv->drm, + async_put_domains_mask(power_domains) & BIT_ULL(domain), + "Async disabling of domain %s is pending\n", + name); power_domains->domain_use_count[domain]--; @@ -2131,7 +2203,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915, goto out_verify; } - WARN_ON(power_domains->domain_use_count[domain] != 1); + drm_WARN_ON(&i915->drm, power_domains->domain_use_count[domain] != 1); /* Let a pending work requeue itself or queue a new one. */ if (power_domains->async_put_wakeref) { @@ -2206,7 +2278,7 @@ intel_display_power_flush_work_sync(struct drm_i915_private *i915) verify_async_put_domains_state(power_domains); - WARN_ON(power_domains->async_put_wakeref); + drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref); } #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM) @@ -2674,7 +2746,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT_ULL(POWER_DOMAIN_INIT)) #define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ - TGL_PW_2_POWER_DOMAINS | \ + TGL_PW_3_POWER_DOMAINS | \ BIT_ULL(POWER_DOMAIN_MODESET) | \ BIT_ULL(POWER_DOMAIN_AUX_A) | \ BIT_ULL(POWER_DOMAIN_AUX_B) | \ @@ -2734,7 +2806,7 @@ static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { }; static const struct i915_power_well_ops chv_pipe_power_well_ops = { - .sync_hw = i9xx_power_well_sync_hw_noop, + .sync_hw = chv_pipe_power_well_sync_hw, .enable = chv_pipe_power_well_enable, .disable = chv_pipe_power_well_disable, .is_enabled = chv_pipe_power_well_enabled, @@ -3870,7 +3942,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { .name = "power well 3", .domains = TGL_PW_3_POWER_DOMAINS, .ops = &hsw_power_well_ops, - .id = DISP_PW_ID_NONE, + .id = TGL_DISP_PW_3, { .hsw.regs = &hsw_power_well_regs, .hsw.idx = ICL_PW_CTL_IDX_PW_3, @@ -4204,11 +4276,13 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, } else if (enable_dc == -1) { requested_dc = max_dc; } else if (enable_dc > max_dc && enable_dc <= 4) { - DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", - enable_dc, max_dc); + drm_dbg_kms(&dev_priv->drm, + "Adjusting requested max DC state (%d->%d)\n", + enable_dc, max_dc); requested_dc = max_dc; } else { - DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); + drm_err(&dev_priv->drm, + "Unexpected value for enable_dc (%d)\n", enable_dc); requested_dc = max_dc; } @@ -4227,7 +4301,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, break; } - DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); + drm_dbg_kms(&dev_priv->drm, "Allowed DC state mask %02x\n", mask); return mask; } @@ -4371,16 +4445,16 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, { u32 val, status; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); val = enable ? (val | DBUF_POWER_REQUEST) : (val & ~DBUF_POWER_REQUEST); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); udelay(10); - status = I915_READ(reg) & DBUF_POWER_STATE; + status = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; if ((enable && !status) || (!enable && status)) { - DRM_ERROR("DBus power %s timeout!\n", - enable ? "enable" : "disable"); + drm_err(&dev_priv->drm, "DBus power %s timeout!\n", + enable ? "enable" : "disable"); return false; } return true; @@ -4388,80 +4462,60 @@ bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) { - intel_dbuf_slice_set(dev_priv, DBUF_CTL, true); + icl_dbuf_slices_update(dev_priv, BIT(DBUF_S1)); } static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) { - intel_dbuf_slice_set(dev_priv, DBUF_CTL, false); -} - -static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) -{ - if (INTEL_GEN(dev_priv) < 11) - return 1; - return 2; + icl_dbuf_slices_update(dev_priv, 0); } void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, u8 req_slices) { - const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; - bool ret; + int i; + int max_slices = INTEL_INFO(dev_priv)->num_supported_dbuf_slices; + struct i915_power_domains *power_domains = &dev_priv->power_domains; - if (req_slices > intel_dbuf_max_slices(dev_priv)) { - DRM_ERROR("Invalid number of dbuf slices requested\n"); - return; - } + drm_WARN(&dev_priv->drm, hweight8(req_slices) > max_slices, + "Invalid number of dbuf slices requested\n"); - if (req_slices == hw_enabled_slices || req_slices == 0) - return; + DRM_DEBUG_KMS("Updating dbuf slices to 0x%x\n", req_slices); - if (req_slices > hw_enabled_slices) - ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); - else - ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false); + /* + * Might be running this in parallel to gen9_dc_off_power_well_enable + * being called from intel_dp_detect for instance, + * which causes assertion triggered by race condition, + * as gen9_assert_dbuf_enabled might preempt this when registers + * were already updated, while dev_priv was not. + */ + mutex_lock(&power_domains->lock); - if (ret) - dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices; + for (i = 0; i < max_slices; i++) { + intel_dbuf_slice_set(dev_priv, + DBUF_CTL_S(i), + (req_slices & BIT(i)) != 0); + } + + dev_priv->enabled_dbuf_slices_mask = req_slices; + + mutex_unlock(&power_domains->lock); } static void icl_dbuf_enable(struct drm_i915_private *dev_priv) { - I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST); - I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST); - POSTING_READ(DBUF_CTL_S2); - - udelay(10); - - if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || - !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) - DRM_ERROR("DBuf power enable timeout\n"); - else - /* - * FIXME: for now pretend that we only have 1 slice, see - * intel_enabled_dbuf_slices_num(). - */ - dev_priv->wm.skl_hw.ddb.enabled_slices = 1; + skl_ddb_get_hw_state(dev_priv); + /* + * Just power up at least 1 slice, we will + * figure out later which slices we have and what we need. + */ + icl_dbuf_slices_update(dev_priv, dev_priv->enabled_dbuf_slices_mask | + BIT(DBUF_S1)); } static void icl_dbuf_disable(struct drm_i915_private *dev_priv) { - I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST); - I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST); - POSTING_READ(DBUF_CTL_S2); - - udelay(10); - - if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) || - (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)) - DRM_ERROR("DBuf power disable timeout!\n"); - else - /* - * FIXME: for now pretend that the first slice is always - * enabled, see intel_enabled_dbuf_slices_num(). - */ - dev_priv->wm.skl_hw.ddb.enabled_slices = 1; + icl_dbuf_slices_update(dev_priv, 0); } static void icl_mbus_init(struct drm_i915_private *dev_priv) @@ -4472,19 +4526,21 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) MBUS_ABOX_BT_CREDIT_POOL2_MASK | MBUS_ABOX_B_CREDIT_MASK | MBUS_ABOX_BW_CREDIT_MASK; - - val = I915_READ(MBUS_ABOX_CTL); - val &= ~mask; - val |= MBUS_ABOX_BT_CREDIT_POOL1(16) | + val = MBUS_ABOX_BT_CREDIT_POOL1(16) | MBUS_ABOX_BT_CREDIT_POOL2(16) | MBUS_ABOX_B_CREDIT(1) | MBUS_ABOX_BW_CREDIT(1); - I915_WRITE(MBUS_ABOX_CTL, val); + + intel_de_rmw(dev_priv, MBUS_ABOX_CTL, mask, val); + if (INTEL_GEN(dev_priv) >= 12) { + intel_de_rmw(dev_priv, MBUS_ABOX1_CTL, mask, val); + intel_de_rmw(dev_priv, MBUS_ABOX2_CTL, mask, val); + } } static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) { - u32 val = I915_READ(LCPLL_CTL); + u32 val = intel_de_read(dev_priv, LCPLL_CTL); /* * The LCPLL register should be turned on by the BIOS. For now @@ -4493,13 +4549,13 @@ static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) */ if (val & LCPLL_CD_SOURCE_FCLK) - DRM_ERROR("CDCLK source is not LCPLL\n"); + drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); if (val & LCPLL_PLL_DISABLE) - DRM_ERROR("LCPLL is disabled\n"); + drm_err(&dev_priv->drm, "LCPLL is disabled\n"); if ((val & LCPLL_REF_MASK) != LCPLL_REF_NON_SSC) - DRM_ERROR("LCPLL not using non-SSC reference\n"); + drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n"); } static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) @@ -4511,26 +4567,26 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", pipe_name(crtc->pipe)); - I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2), + I915_STATE_WARN(intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), "Display power well on\n"); - I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); - I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); - I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); - I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, + I915_STATE_WARN(intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, "Panel power on\n"); - I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, "CPU PWM1 enabled\n"); if (IS_HASWELL(dev_priv)) - I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, "CPU PWM2 enabled\n"); - I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, "PCH PWM1 enabled\n"); - I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE, "Utility pin enabled\n"); - I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, + I915_STATE_WARN(intel_de_read(dev_priv, PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); /* @@ -4545,9 +4601,9 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv) { if (IS_HASWELL(dev_priv)) - return I915_READ(D_COMP_HSW); + return intel_de_read(dev_priv, D_COMP_HSW); else - return I915_READ(D_COMP_BDW); + return intel_de_read(dev_priv, D_COMP_BDW); } static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) @@ -4555,10 +4611,11 @@ static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val) if (IS_HASWELL(dev_priv)) { if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) - DRM_DEBUG_KMS("Failed to write to D_COMP\n"); + drm_dbg_kms(&dev_priv->drm, + "Failed to write to D_COMP\n"); } else { - I915_WRITE(D_COMP_BDW, val); - POSTING_READ(D_COMP_BDW); + intel_de_write(dev_priv, D_COMP_BDW, val); + intel_de_posting_read(dev_priv, D_COMP_BDW); } } @@ -4577,25 +4634,25 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, assert_can_disable_lcpll(dev_priv); - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); if (switch_to_fclk) { val |= LCPLL_CD_SOURCE_FCLK; - I915_WRITE(LCPLL_CTL, val); + intel_de_write(dev_priv, LCPLL_CTL, val); - if (wait_for_us(I915_READ(LCPLL_CTL) & + if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & LCPLL_CD_SOURCE_FCLK_DONE, 1)) - DRM_ERROR("Switching to FCLK failed\n"); + drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); } val |= LCPLL_PLL_DISABLE; - I915_WRITE(LCPLL_CTL, val); - POSTING_READ(LCPLL_CTL); + intel_de_write(dev_priv, LCPLL_CTL, val); + intel_de_posting_read(dev_priv, LCPLL_CTL); if (intel_de_wait_for_clear(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 1)) - DRM_ERROR("LCPLL still locked\n"); + drm_err(&dev_priv->drm, "LCPLL still locked\n"); val = hsw_read_dcomp(dev_priv); val |= D_COMP_COMP_DISABLE; @@ -4604,13 +4661,13 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) - DRM_ERROR("D_COMP RCOMP still in progress\n"); + drm_err(&dev_priv->drm, "D_COMP RCOMP still in progress\n"); if (allow_power_down) { - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); val |= LCPLL_POWER_DOWN_ALLOW; - I915_WRITE(LCPLL_CTL, val); - POSTING_READ(LCPLL_CTL); + intel_de_write(dev_priv, LCPLL_CTL, val); + intel_de_posting_read(dev_priv, LCPLL_CTL); } } @@ -4622,7 +4679,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) { u32 val; - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) @@ -4636,8 +4693,8 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) if (val & LCPLL_POWER_DOWN_ALLOW) { val &= ~LCPLL_POWER_DOWN_ALLOW; - I915_WRITE(LCPLL_CTL, val); - POSTING_READ(LCPLL_CTL); + intel_de_write(dev_priv, LCPLL_CTL, val); + intel_de_posting_read(dev_priv, LCPLL_CTL); } val = hsw_read_dcomp(dev_priv); @@ -4645,27 +4702,28 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) val &= ~D_COMP_COMP_DISABLE; hsw_write_dcomp(dev_priv, val); - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); val &= ~LCPLL_PLL_DISABLE; - I915_WRITE(LCPLL_CTL, val); + intel_de_write(dev_priv, LCPLL_CTL, val); if (intel_de_wait_for_set(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) - DRM_ERROR("LCPLL not locked yet\n"); + drm_err(&dev_priv->drm, "LCPLL not locked yet\n"); if (val & LCPLL_CD_SOURCE_FCLK) { - val = I915_READ(LCPLL_CTL); + val = intel_de_read(dev_priv, LCPLL_CTL); val &= ~LCPLL_CD_SOURCE_FCLK; - I915_WRITE(LCPLL_CTL, val); + intel_de_write(dev_priv, LCPLL_CTL, val); - if (wait_for_us((I915_READ(LCPLL_CTL) & + if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) - DRM_ERROR("Switching back to LCPLL failed\n"); + drm_err(&dev_priv->drm, + "Switching back to LCPLL failed\n"); } intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL); intel_update_cdclk(dev_priv); - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK"); + intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK"); } /* @@ -4695,12 +4753,12 @@ static void hsw_enable_pc8(struct drm_i915_private *dev_priv) { u32 val; - DRM_DEBUG_KMS("Enabling package C8+\n"); + drm_dbg_kms(&dev_priv->drm, "Enabling package C8+\n"); if (HAS_PCH_LPT_LP(dev_priv)) { - val = I915_READ(SOUTH_DSPCLK_GATE_D); + val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; - I915_WRITE(SOUTH_DSPCLK_GATE_D, val); + intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); } lpt_disable_clkout_dp(dev_priv); @@ -4711,15 +4769,15 @@ static void hsw_disable_pc8(struct drm_i915_private *dev_priv) { u32 val; - DRM_DEBUG_KMS("Disabling package C8+\n"); + drm_dbg_kms(&dev_priv->drm, "Disabling package C8+\n"); hsw_restore_lcpll(dev_priv); intel_init_pch_refclk(dev_priv); if (HAS_PCH_LPT_LP(dev_priv)) { - val = I915_READ(SOUTH_DSPCLK_GATE_D); + val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); val |= PCH_LP_PARTITION_LEVEL_DISABLE; - I915_WRITE(SOUTH_DSPCLK_GATE_D, val); + intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); } } @@ -4737,14 +4795,14 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, reset_bits = RESET_PCH_HANDSHAKE_ENABLE; } - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if (enable) val |= reset_bits; else val &= ~reset_bits; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } static void skl_display_core_init(struct drm_i915_private *dev_priv, @@ -4769,7 +4827,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); gen9_dbuf_enable(dev_priv); @@ -4786,7 +4844,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ /* disable PG1 and Misc I/O */ @@ -4830,7 +4888,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); gen9_dbuf_enable(dev_priv); @@ -4847,7 +4905,7 @@ static void bxt_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* The spec doesn't call for removing the reset handshake flag */ @@ -4889,7 +4947,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume mutex_unlock(&power_domains->lock); /* 5. Enable CD clock */ - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); /* 6. Enable DBUF */ gen9_dbuf_enable(dev_priv); @@ -4911,7 +4969,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) gen9_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* * 4. Disable Power Well 1 (PG1). @@ -4970,25 +5028,23 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv) break; if (table[i].page_mask == 0) { - DRM_DEBUG_DRIVER("Unknown memory configuration; disabling address buddy logic.\n"); - I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE); - I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE); + drm_dbg(&dev_priv->drm, + "Unknown memory configuration; disabling address buddy logic.\n"); + intel_de_write(dev_priv, BW_BUDDY1_CTL, BW_BUDDY_DISABLE); + intel_de_write(dev_priv, BW_BUDDY2_CTL, BW_BUDDY_DISABLE); } else { - u32 val; - - I915_WRITE(BW_BUDDY1_PAGE_MASK, table[i].page_mask); - I915_WRITE(BW_BUDDY2_PAGE_MASK, table[i].page_mask); + intel_de_write(dev_priv, BW_BUDDY1_PAGE_MASK, + table[i].page_mask); + intel_de_write(dev_priv, BW_BUDDY2_PAGE_MASK, + table[i].page_mask); /* Wa_22010178259:tgl */ - val = I915_READ(BW_BUDDY1_CTL); - val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK; - val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8); - I915_WRITE(BW_BUDDY1_CTL, val); - - val = I915_READ(BW_BUDDY2_CTL); - val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK; - val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8); - I915_WRITE(BW_BUDDY2_CTL, val); + intel_de_rmw(dev_priv, BW_BUDDY1_CTL, + BW_BUDDY_TLB_REQ_TIMER_MASK, + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); + intel_de_rmw(dev_priv, BW_BUDDY2_CTL, + BW_BUDDY_TLB_REQ_TIMER_MASK, + REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8)); } } @@ -5016,7 +5072,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, mutex_unlock(&power_domains->lock); /* 4. Enable CDCLK. */ - intel_cdclk_init(dev_priv); + intel_cdclk_init_hw(dev_priv); /* 5. Enable DBUF. */ icl_dbuf_enable(dev_priv); @@ -5045,7 +5101,7 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv) icl_dbuf_disable(dev_priv); /* 3. Disable CD clock */ - intel_cdclk_uninit(dev_priv); + intel_cdclk_uninit_hw(dev_priv); /* * 4. Disable Power Well 1 (PG1). @@ -5090,7 +5146,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) * current lane status. */ if (cmn_bc->desc->ops->is_enabled(dev_priv, cmn_bc)) { - u32 status = I915_READ(DPLL(PIPE_A)); + u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); unsigned int mask; mask = status & DPLL_PORTB_READY_MASK; @@ -5121,7 +5177,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) } if (cmn_d->desc->ops->is_enabled(dev_priv, cmn_d)) { - u32 status = I915_READ(DPIO_PHY_STATUS); + u32 status = intel_de_read(dev_priv, DPIO_PHY_STATUS); unsigned int mask; mask = status & DPLL_PORTD_READY_MASK; @@ -5142,10 +5198,10 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) dev_priv->chv_phy_assert[DPIO_PHY1] = true; } - I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); + drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n", + dev_priv->chv_phy_control); - DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", - dev_priv->chv_phy_control); + /* Defer application of initial phy_control to enabling the powerwell */ } static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) @@ -5158,10 +5214,10 @@ static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) /* If the display might be already active skip this */ if (cmn->desc->ops->is_enabled(dev_priv, cmn) && disp2d->desc->ops->is_enabled(dev_priv, disp2d) && - I915_READ(DPIO_CTL) & DPIO_CMNRST) + intel_de_read(dev_priv, DPIO_CTL) & DPIO_CMNRST) return; - DRM_DEBUG_KMS("toggling display PHY side reset\n"); + drm_dbg_kms(&dev_priv->drm, "toggling display PHY side reset\n"); /* cmnlane needs DPLL registers */ disp2d->desc->ops->enable(dev_priv, disp2d); @@ -5189,8 +5245,9 @@ static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0 static void assert_ved_power_gated(struct drm_i915_private *dev_priv) { - WARN(!vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), - "VED not power gated\n"); + drm_WARN(&dev_priv->drm, + !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_VEDSSPM0), + "VED not power gated\n"); } static void assert_isp_power_gated(struct drm_i915_private *dev_priv) @@ -5201,9 +5258,9 @@ static void assert_isp_power_gated(struct drm_i915_private *dev_priv) {} }; - WARN(!pci_dev_present(isp_ids) && - !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), - "ISP not power gated\n"); + drm_WARN(&dev_priv->drm, !pci_dev_present(isp_ids) && + !vlv_punit_is_power_gated(dev_priv, PUNIT_REG_ISPSSPM0), + "ISP not power gated\n"); } static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv); @@ -5230,9 +5287,6 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) power_domains->initializing = true; - /* Must happen before power domain init on VLV/CHV */ - intel_update_rawclk(i915); - if (INTEL_GEN(i915) >= 11) { icl_display_core_init(i915, resume); } else if (IS_CANNONLAKE(i915)) { @@ -5336,7 +5390,7 @@ void intel_power_domains_disable(struct drm_i915_private *i915) { struct i915_power_domains *power_domains = &i915->power_domains; - WARN_ON(power_domains->wakeref); + drm_WARN_ON(&i915->drm, power_domains->wakeref); power_domains->wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); @@ -5418,7 +5472,7 @@ void intel_power_domains_resume(struct drm_i915_private *i915) intel_power_domains_init_hw(i915, true); power_domains->display_core_suspended = false; } else { - WARN_ON(power_domains->wakeref); + drm_WARN_ON(&i915->drm, power_domains->wakeref); power_domains->wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT); } @@ -5436,13 +5490,13 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915) for_each_power_well(i915, power_well) { enum intel_display_power_domain domain; - DRM_DEBUG_DRIVER("%-25s %d\n", - power_well->desc->name, power_well->count); + drm_dbg(&i915->drm, "%-25s %d\n", + power_well->desc->name, power_well->count); for_each_power_domain(domain, power_well->desc->domains) - DRM_DEBUG_DRIVER(" %-23s %d\n", - intel_display_power_domain_str(domain), - power_domains->domain_use_count[domain]); + drm_dbg(&i915->drm, " %-23s %d\n", + intel_display_power_domain_str(domain), + power_domains->domain_use_count[domain]); } } @@ -5475,19 +5529,21 @@ static void intel_power_domains_verify_state(struct drm_i915_private *i915) enabled = power_well->desc->ops->is_enabled(i915, power_well); if ((power_well->count || power_well->desc->always_on) != enabled) - DRM_ERROR("power well %s state mismatch (refcount %d/enabled %d)", - power_well->desc->name, - power_well->count, enabled); + drm_err(&i915->drm, + "power well %s state mismatch (refcount %d/enabled %d)", + power_well->desc->name, + power_well->count, enabled); domains_count = 0; for_each_power_domain(domain, power_well->desc->domains) domains_count += power_domains->domain_use_count[domain]; if (power_well->count != domains_count) { - DRM_ERROR("power well %s refcount/domain refcount mismatch " - "(refcount %d/domains refcount %d)\n", - power_well->desc->name, power_well->count, - domains_count); + drm_err(&i915->drm, + "power well %s refcount/domain refcount mismatch " + "(refcount %d/domains refcount %d)\n", + power_well->desc->name, power_well->count, + domains_count); dump_domain_info = true; } } diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index 2608a65af7fa..da64a5edae7a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -100,6 +100,7 @@ enum i915_power_well_id { SKL_DISP_PW_MISC_IO, SKL_DISP_PW_1, SKL_DISP_PW_2, + TGL_DISP_PW_3, SKL_DISP_DC_OFF, }; @@ -307,6 +308,11 @@ intel_display_power_put_async(struct drm_i915_private *i915, } #endif +enum dbuf_slice { + DBUF_S1, + DBUF_S2, +}; + #define with_intel_display_power(i915, domain, wf) \ for ((wf) = intel_display_power_get((i915), (domain)); (wf); \ intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 888ea8a170d1..5e00e611f077 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -39,13 +39,14 @@ #include <drm/drm_probe_helper.h> #include <drm/drm_rect.h> #include <drm/drm_vblank.h> -#include <drm/i915_drm.h> #include <drm/i915_mei_hdcp_interface.h> #include <media/cec-notifier.h> #include "i915_drv.h" +#include "intel_de.h" struct drm_printer; +struct __intel_global_objs_state; /* * Display related stuff @@ -139,6 +140,9 @@ struct intel_encoder { int (*compute_config)(struct intel_encoder *, struct intel_crtc_state *, struct drm_connector_state *); + int (*compute_config_late)(struct intel_encoder *, + struct intel_crtc_state *, + struct drm_connector_state *); void (*update_prepare)(struct intel_atomic_state *, struct intel_encoder *, struct intel_crtc *); @@ -214,6 +218,9 @@ struct intel_panel { u8 controller; /* bxt+ only */ struct pwm_device *pwm; + /* DPCD backlight */ + u8 pwmgen_bit_count; + struct backlight_device *device; /* Connector and platform specific backlight functions */ @@ -458,25 +465,8 @@ struct intel_atomic_state { intel_wakeref_t wakeref; - struct { - /* - * Logical state of cdclk (used for all scaling, watermark, - * etc. calculations and checks). This is computed as if all - * enabled crtcs were active. - */ - struct intel_cdclk_state logical; - - /* - * Actual state of cdclk, can be different from the logical - * state only when all crtc's are DPMS off. - */ - struct intel_cdclk_state actual; - - int force_min_cdclk; - bool force_min_cdclk_changed; - /* pipe to which cd2x update is synchronized */ - enum pipe pipe; - } cdclk; + struct __intel_global_objs_state *global_objs; + int num_global_objs; bool dpll_set, modeset; @@ -491,10 +481,6 @@ struct intel_atomic_state { u8 active_pipe_changes; u8 active_pipes; - /* minimum acceptable cdclk for each pipe */ - int min_cdclk[I915_MAX_PIPES]; - /* minimum acceptable voltage level for each pipe */ - u8 min_voltage_level[I915_MAX_PIPES]; struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS]; @@ -508,14 +494,11 @@ struct intel_atomic_state { /* * active_pipes - * min_cdclk[] - * min_voltage_level[] - * cdclk.* */ bool global_state_changed; - /* Gen9+ only */ - struct skl_ddb_values wm_results; + /* Number of enabled DBuf slices */ + u8 enabled_dbuf_slices_mask; struct i915_sw_fence commit_ready; @@ -611,6 +594,7 @@ struct intel_plane_state { struct intel_initial_plane_config { struct intel_framebuffer *fb; + struct i915_vma *vma; unsigned int tiling; int size; u32 base; @@ -657,15 +641,30 @@ struct intel_crtc_scaler_state { /* Flag to use the scanline counter instead of the pixel counter */ #define I915_MODE_FLAG_USE_SCANLINE_COUNTER (1<<2) +struct intel_wm_level { + bool enable; + u32 pri_val; + u32 spr_val; + u32 cur_val; + u32 fbc_val; +}; + struct intel_pipe_wm { struct intel_wm_level wm[5]; - u32 linetime; bool fbc_wm_enabled; bool pipe_enabled; bool sprites_enabled; bool sprites_scaled; }; +struct skl_wm_level { + u16 min_ddb_alloc; + u16 plane_res_b; + u8 plane_res_l; + bool plane_en; + bool ignore_lines; +}; + struct skl_plane_wm { struct skl_wm_level wm[8]; struct skl_wm_level uv_wm[8]; @@ -675,7 +674,6 @@ struct skl_plane_wm { struct skl_pipe_wm { struct skl_plane_wm planes[I915_MAX_PLANES]; - u32 linetime; }; enum vlv_wm_level { @@ -1046,6 +1044,10 @@ struct intel_crtc_state { struct drm_dsc_config config; } dsc; + /* HSW+ linetime watermarks */ + u16 linetime; + u16 ips_linetime; + /* Forward Error correction State */ bool fec_enable; @@ -1059,6 +1061,32 @@ struct intel_crtc_state { enum transcoder mst_master_transcoder; }; +enum intel_pipe_crc_source { + INTEL_PIPE_CRC_SOURCE_NONE, + INTEL_PIPE_CRC_SOURCE_PLANE1, + INTEL_PIPE_CRC_SOURCE_PLANE2, + INTEL_PIPE_CRC_SOURCE_PLANE3, + INTEL_PIPE_CRC_SOURCE_PLANE4, + INTEL_PIPE_CRC_SOURCE_PLANE5, + INTEL_PIPE_CRC_SOURCE_PLANE6, + INTEL_PIPE_CRC_SOURCE_PLANE7, + INTEL_PIPE_CRC_SOURCE_PIPE, + /* TV/DP on pre-gen5/vlv can't use the pipe source. */ + INTEL_PIPE_CRC_SOURCE_TV, + INTEL_PIPE_CRC_SOURCE_DP_B, + INTEL_PIPE_CRC_SOURCE_DP_C, + INTEL_PIPE_CRC_SOURCE_DP_D, + INTEL_PIPE_CRC_SOURCE_AUTO, + INTEL_PIPE_CRC_SOURCE_MAX, +}; + +#define INTEL_PIPE_CRC_ENTRIES_NR 128 +struct intel_pipe_crc { + spinlock_t lock; + int skipped; + enum intel_pipe_crc_source source; +}; + struct intel_crtc { struct drm_crtc base; enum pipe pipe; @@ -1102,6 +1130,10 @@ struct intel_crtc { /* per pipe DSB related info */ struct intel_dsb dsb; + +#ifdef CONFIG_DEBUG_FS + struct intel_pipe_crc pipe_crc; +#endif }; struct intel_plane { @@ -1181,8 +1213,6 @@ struct intel_hdmi { }; struct intel_dp_mst_encoder; -#define DP_MAX_DOWNSTREAM_PORTS 0x10 - /* * enum link_m_n_set: * When platform provides two set of M_N registers for dp, we can @@ -1250,6 +1280,7 @@ struct intel_dp { int max_link_rate; /* sink or branch descriptor */ struct drm_dp_desc desc; + u32 edid_quirks; struct drm_dp_aux aux; u32 aux_busy_last_status; u8 train_set[4]; @@ -1422,8 +1453,17 @@ vlv_pipe_to_channel(enum pipe pipe) } static inline struct intel_crtc * +intel_get_first_crtc(struct drm_i915_private *dev_priv) +{ + return to_intel_crtc(drm_crtc_from_index(&dev_priv->drm, 0)); +} + +static inline struct intel_crtc * intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) { + /* pipe_to_crtc_mapping may have hole on any of 3 display pipe system */ + drm_WARN_ON(&dev_priv->drm, + !(INTEL_INFO(dev_priv)->pipe_mask & BIT(pipe))); return dev_priv->pipe_to_crtc_mapping[pipe]; } @@ -1469,7 +1509,7 @@ enc_to_dig_port(struct intel_encoder *encoder) } static inline struct intel_digital_port * -conn_to_dig_port(struct intel_connector *connector) +intel_attached_dig_port(struct intel_connector *connector) { return enc_to_dig_port(intel_attached_encoder(connector)); } @@ -1486,6 +1526,11 @@ static inline struct intel_dp *enc_to_intel_dp(struct intel_encoder *encoder) return &enc_to_dig_port(encoder)->dp; } +static inline struct intel_dp *intel_attached_dp(struct intel_connector *connector) +{ + return enc_to_intel_dp(intel_attached_encoder(connector)); +} + static inline bool intel_encoder_is_dp(struct intel_encoder *encoder) { switch (encoder->type) { @@ -1608,11 +1653,15 @@ intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state) (1 << INTEL_OUTPUT_DP_MST) | (1 << INTEL_OUTPUT_EDP)); } + static inline void intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) { - drm_wait_one_vblank(&dev_priv->drm, pipe); + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); + + drm_crtc_wait_one_vblank(&crtc->base); } + static inline void intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, enum pipe pipe) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c7424e2a04a3..804b1d966f66 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -40,7 +40,6 @@ #include <drm/drm_edid.h> #include <drm/drm_hdcp.h> #include <drm/drm_probe_helper.h> -#include <drm/i915_drm.h> #include "i915_debugfs.h" #include "i915_drv.h" @@ -49,6 +48,7 @@ #include "intel_audio.h" #include "intel_connector.h" #include "intel_ddi.h" +#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" @@ -146,11 +146,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) return intel_dig_port->base.type == INTEL_OUTPUT_EDP; } -static struct intel_dp *intel_attached_dp(struct intel_connector *connector) -{ - return enc_to_intel_dp(intel_attached_encoder(connector)); -} - static void intel_dp_link_down(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state); static bool edp_panel_vdd_on(struct intel_dp *intel_dp); @@ -272,7 +267,7 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum port port = dig_port->base.port; - u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; + u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; /* Low voltage SKUs are limited to max of 5.4G */ if (voltage == VOLTAGE_INFO_0_85V) @@ -323,14 +318,14 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) 162000, 270000 }; struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); - const struct ddi_vbt_port_info *info = - &dev_priv->vbt.ddi_port_info[dig_port->base.port]; const int *source_rates; - int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate; + int size, max_rate = 0, vbt_max_rate; /* This should only be done once */ - WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); + drm_WARN_ON(&dev_priv->drm, + intel_dp->source_rates || intel_dp->num_source_rates); if (INTEL_GEN(dev_priv) >= 10) { source_rates = cnl_rates; @@ -354,6 +349,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) size = ARRAY_SIZE(g4x_rates); } + vbt_max_rate = intel_bios_dp_max_link_rate(encoder); if (max_rate && vbt_max_rate) max_rate = min(max_rate, vbt_max_rate); else if (vbt_max_rate) @@ -519,12 +515,13 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, */ bits_per_pixel = (link_clock * lane_count * 8) / intel_dp_mode_to_fec_clock(mode_clock); - DRM_DEBUG_KMS("Max link bpp: %u\n", bits_per_pixel); + drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / mode_hdisplay; - DRM_DEBUG_KMS("Max small joiner bpp: %u\n", max_bpp_small_joiner_ram); + drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n", + max_bpp_small_joiner_ram); /* * Greatest allowed DSC BPP = MIN (output BPP from available Link BW @@ -534,8 +531,8 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, /* Error out if the max bpp is less than smallest allowed valid bpp */ if (bits_per_pixel < valid_dsc_bpp[0]) { - DRM_DEBUG_KMS("Unsupported BPP %u, min %u\n", - bits_per_pixel, valid_dsc_bpp[0]); + drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", + bits_per_pixel, valid_dsc_bpp[0]); return 0; } @@ -760,20 +757,22 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) enum dpio_channel ch = vlv_pipe_to_channel(pipe); u32 DP; - if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, - "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name)) + if (drm_WARN(&dev_priv->drm, + intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, + "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n", + pipe_name(pipe), intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name)) return; - DRM_DEBUG_KMS("kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n", + pipe_name(pipe), intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); /* Preserve the BIOS-computed detected bit. This is * supposed to be read-only. */ - DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; + DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; DP |= DP_PORT_WIDTH(1); DP |= DP_LINK_TRAIN_PAT_1; @@ -783,7 +782,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) else DP |= DP_PIPE_SEL(pipe); - pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; + pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; /* * The DPLL for the pipe must be enabled for this to work. @@ -795,8 +794,9 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { - DRM_ERROR("Failed to force on pll for pipe %c!\n", - pipe_name(pipe)); + drm_err(&dev_priv->drm, + "Failed to force on pll for pipe %c!\n", + pipe_name(pipe)); return; } } @@ -807,14 +807,14 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) * to make this power sequencer lock onto the port. * Otherwise even VDD force bit won't work. */ - I915_WRITE(intel_dp->output_reg, DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); - I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); + intel_de_posting_read(dev_priv, intel_dp->output_reg); - I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); + intel_de_posting_read(dev_priv, intel_dp->output_reg); if (!pll_enabled) { vlv_force_pll_off(dev_priv, pipe); @@ -837,13 +837,16 @@ static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (encoder->type == INTEL_OUTPUT_EDP) { - WARN_ON(intel_dp->active_pipe != INVALID_PIPE && - intel_dp->active_pipe != intel_dp->pps_pipe); + drm_WARN_ON(&dev_priv->drm, + intel_dp->active_pipe != INVALID_PIPE && + intel_dp->active_pipe != + intel_dp->pps_pipe); if (intel_dp->pps_pipe != INVALID_PIPE) pipes &= ~(1 << intel_dp->pps_pipe); } else { - WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, + intel_dp->pps_pipe != INVALID_PIPE); if (intel_dp->active_pipe != INVALID_PIPE) pipes &= ~(1 << intel_dp->active_pipe); @@ -866,10 +869,10 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); /* We should never land here with regular DP ports */ - WARN_ON(!intel_dp_is_edp(intel_dp)); + drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE && - intel_dp->active_pipe != intel_dp->pps_pipe); + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE && + intel_dp->active_pipe != intel_dp->pps_pipe); if (intel_dp->pps_pipe != INVALID_PIPE) return intel_dp->pps_pipe; @@ -880,16 +883,17 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp) * Didn't find one. This should not happen since there * are two power sequencers and up to two eDP ports. */ - if (WARN_ON(pipe == INVALID_PIPE)) + if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)) pipe = PIPE_A; vlv_steal_power_sequencer(dev_priv, pipe); intel_dp->pps_pipe = pipe; - DRM_DEBUG_KMS("picked pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(intel_dp->pps_pipe), - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "picked pipe %c power sequencer for [ENCODER:%d:%s]\n", + pipe_name(intel_dp->pps_pipe), + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); /* init power sequencer on this pipe and port */ intel_dp_init_panel_power_sequencer(intel_dp); @@ -913,7 +917,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); /* We should never land here with regular DP ports */ - WARN_ON(!intel_dp_is_edp(intel_dp)); + drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp)); if (!intel_dp->pps_reset) return backlight_controller; @@ -935,13 +939,13 @@ typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, enum pipe pipe) { - return I915_READ(PP_STATUS(pipe)) & PP_ON; + return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON; } static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, enum pipe pipe) { - return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; + return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD; } static bool vlv_pipe_any(struct drm_i915_private *dev_priv, @@ -958,7 +962,7 @@ vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, enum pipe pipe; for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { - u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & + u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & PANEL_PORT_SELECT_MASK; if (port_sel != PANEL_PORT_SELECT_VLV(port)) @@ -997,16 +1001,18 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ if (intel_dp->pps_pipe == INVALID_PIPE) { - DRM_DEBUG_KMS("no initial power sequencer for [ENCODER:%d:%s]\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "no initial power sequencer for [ENCODER:%d:%s]\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); return; } - DRM_DEBUG_KMS("initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name, - pipe_name(intel_dp->pps_pipe)); + drm_dbg_kms(&dev_priv->drm, + "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name, + pipe_name(intel_dp->pps_pipe)); intel_dp_init_panel_power_sequencer(intel_dp); intel_dp_init_panel_power_sequencer_registers(intel_dp, false); @@ -1016,8 +1022,10 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) { struct intel_encoder *encoder; - if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_GEN9_LP(dev_priv))) + if (drm_WARN_ON(&dev_priv->drm, + !(IS_VALLEYVIEW(dev_priv) || + IS_CHERRYVIEW(dev_priv) || + IS_GEN9_LP(dev_priv)))) return; /* @@ -1033,7 +1041,8 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) for_each_intel_dp(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, + intel_dp->active_pipe != INVALID_PIPE); if (encoder->type != INTEL_OUTPUT_EDP) continue; @@ -1119,12 +1128,13 @@ static int edp_notify_handler(struct notifier_block *this, unsigned long code, pp_ctrl_reg = PP_CONTROL(pipe); pp_div_reg = PP_DIVISOR(pipe); - pp_div = I915_READ(pp_div_reg); + pp_div = intel_de_read(dev_priv, pp_div_reg); pp_div &= PP_REFERENCE_DIVIDER_MASK; /* 0x1F write to PP_DIV_REG sets max cycle delay */ - I915_WRITE(pp_div_reg, pp_div | 0x1F); - I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS); + intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F); + intel_de_write(dev_priv, pp_ctrl_reg, + PANEL_UNLOCK_REGS); msleep(intel_dp->panel_power_cycle_delay); } } @@ -1142,7 +1152,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp) intel_dp->pps_pipe == INVALID_PIPE) return false; - return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; + return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; } static bool edp_have_panel_vdd(struct intel_dp *intel_dp) @@ -1155,7 +1165,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp) intel_dp->pps_pipe == INVALID_PIPE) return false; - return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; + return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; } static void @@ -1167,10 +1177,11 @@ intel_dp_check_edp(struct intel_dp *intel_dp) return; if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { - WARN(1, "eDP powered off while attempting aux channel communication.\n"); - DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", - I915_READ(_pp_stat_reg(intel_dp)), - I915_READ(_pp_ctrl_reg(intel_dp))); + drm_WARN(&dev_priv->drm, 1, + "eDP powered off while attempting aux channel communication.\n"); + drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n", + intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), + intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp))); } } @@ -1191,8 +1202,9 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp) trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); if (!done) - DRM_ERROR("%s did not complete or timeout within %ums (status 0x%08x)\n", - intel_dp->aux.name, timeout_ms, status); + drm_err(&i915->drm, + "%s: did not complete or timeout within %ums (status 0x%08x)\n", + intel_dp->aux.name, timeout_ms, status); #undef C return status; @@ -1209,13 +1221,14 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) * The clock divider is based off the hrawclk, and would like to run at * 2MHz. So, take the hrawclk value and divide by 2000 and use that */ - return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); + return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); } static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + u32 freq; if (index) return 0; @@ -1226,9 +1239,10 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) * divide by 2000 and use that */ if (dig_port->aux_ch == AUX_CH_A) - return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); + freq = dev_priv->cdclk.hw.cdclk; else - return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); + freq = RUNTIME_INFO(dev_priv)->rawclk_freq; + return DIV_ROUND_CLOSEST(freq, 2000); } static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) @@ -1360,7 +1374,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, * lowest possible wakeup latency and so prevent the cpu from going into * deep sleep states. */ - pm_qos_update_request(&i915->pm_qos, 0); + cpu_latency_qos_update_request(&i915->pm_qos, 0); intel_dp_check_edp(intel_dp); @@ -1378,8 +1392,9 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, const u32 status = intel_uncore_read(uncore, ch_ctl); if (status != intel_dp->aux_busy_last_status) { - WARN(1, "dp_aux_ch not started status 0x%08x\n", - status); + drm_WARN(&i915->drm, 1, + "%s: not started (status 0x%08x)\n", + intel_dp->aux.name, status); intel_dp->aux_busy_last_status = status; } @@ -1388,7 +1403,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, } /* Only 5 data registers! */ - if (WARN_ON(send_bytes > 20 || recv_size > 20)) { + if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { ret = -E2BIG; goto out; } @@ -1440,7 +1455,8 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, } if ((status & DP_AUX_CH_CTL_DONE) == 0) { - DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); + drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", + intel_dp->aux.name, status); ret = -EBUSY; goto out; } @@ -1450,7 +1466,8 @@ done: * Timeouts occur when the sink is not connected */ if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { - DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); + drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", + intel_dp->aux.name, status); ret = -EIO; goto out; } @@ -1458,7 +1475,8 @@ done: /* Timeouts occur when the device isn't connected, so they're * "normal" -- don't fill the kernel log with these */ if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { - DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); + drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", + intel_dp->aux.name, status); ret = -ETIMEDOUT; goto out; } @@ -1473,8 +1491,9 @@ done: * drm layer takes care for the necessary retries. */ if (recv_bytes == 0 || recv_bytes > 20) { - DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", - recv_bytes); + drm_dbg_kms(&i915->drm, + "%s: Forbidden recv_bytes = %d on aux transaction\n", + intel_dp->aux.name, recv_bytes); ret = -EBUSY; goto out; } @@ -1488,7 +1507,7 @@ done: ret = recv_bytes; out: - pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE); + cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE); if (vdd) edp_panel_vdd_off(intel_dp, false); @@ -1742,7 +1761,8 @@ intel_dp_aux_init(struct intel_dp *intel_dp) drm_dp_aux_init(&intel_dp->aux); /* Failure to allocate our preferred name is not critical */ - intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", + intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/port %c", + aux_ch_name(dig_port->aux_ch), port_name(encoder->port)); intel_dp->aux.transfer = intel_dp_aux_transfer; } @@ -1918,8 +1938,9 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp, /* Get bpp from vbt only for panels that dont have bpp in edid */ if (intel_connector->base.display_info.bpc == 0 && dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { - DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", - dev_priv->vbt.edp.bpp); + drm_dbg_kms(&dev_priv->drm, + "clamping bpp for eDP panel to BIOS-provided %i\n", + dev_priv->vbt.edp.bpp); bpp = dev_priv->vbt.edp.bpp; } } @@ -2115,7 +2136,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, /* Min Input BPC for ICL+ is 8 */ if (pipe_bpp < 8 * 3) { - DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); + drm_dbg_kms(&dev_priv->drm, + "No DSC support for less than 8bpc\n"); return -EINVAL; } @@ -2150,7 +2172,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay); if (!dsc_max_output_bpp || !dsc_dp_slice_count) { - DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); + drm_dbg_kms(&dev_priv->drm, + "Compressed BPP/Slice Count not supported\n"); return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, @@ -2167,26 +2190,28 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (pipe_config->dsc.slice_count > 1) { pipe_config->dsc.dsc_split = true; } else { - DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); + drm_dbg_kms(&dev_priv->drm, + "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); if (ret < 0) { - DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " - "Compressed BPP = %d\n", - pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp); + drm_dbg_kms(&dev_priv->drm, + "Cannot compute valid DSC parameters for Input Bpp = %d " + "Compressed BPP = %d\n", + pipe_config->pipe_bpp, + pipe_config->dsc.compressed_bpp); return ret; } pipe_config->dsc.compression_enable = true; - DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " - "Compressed Bpp = %d Slice Count = %d\n", - pipe_config->pipe_bpp, - pipe_config->dsc.compressed_bpp, - pipe_config->dsc.slice_count); + drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " + "Compressed Bpp = %d Slice Count = %d\n", + pipe_config->pipe_bpp, + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); return 0; } @@ -2214,7 +2239,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, intel_dp->max_link_rate); /* No common link rates between source and sink */ - WARN_ON(common_len <= 0); + drm_WARN_ON(encoder->base.dev, common_len <= 0); limits.min_clock = 0; limits.max_clock = common_len - 1; @@ -2373,7 +2398,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_connector *intel_connector = intel_dp->attached_connector; struct intel_digital_connector_state *intel_conn_state = to_intel_digital_connector_state(conn_state); - bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_CONSTANT_N); int ret = 0, output_bpp; @@ -2515,7 +2540,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder, /* Preserve the BIOS-computed detected bit. This is * supposed to be read-only. */ - intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; + intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; /* Handle DP bits in common between all three register formats */ intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; @@ -2539,12 +2564,12 @@ static void intel_dp_prepare(struct intel_encoder *encoder, intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; - trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); + trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)); if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) trans_dp |= TRANS_DP_ENH_FRAMING; else trans_dp &= ~TRANS_DP_ENH_FRAMING; - I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); + intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp); } else { if (IS_G4X(dev_priv) && pipe_config->limited_color_range) intel_dp->DP |= DP_COLOR_RANGE_16_235; @@ -2590,18 +2615,20 @@ static void wait_panel_status(struct intel_dp *intel_dp, pp_stat_reg = _pp_stat_reg(intel_dp); pp_ctrl_reg = _pp_ctrl_reg(intel_dp); - DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", - mask, value, - I915_READ(pp_stat_reg), - I915_READ(pp_ctrl_reg)); + drm_dbg_kms(&dev_priv->drm, + "mask %08x value %08x status %08x control %08x\n", + mask, value, + intel_de_read(dev_priv, pp_stat_reg), + intel_de_read(dev_priv, pp_ctrl_reg)); if (intel_de_wait_for_register(dev_priv, pp_stat_reg, mask, value, 5000)) - DRM_ERROR("Panel status timeout: status %08x control %08x\n", - I915_READ(pp_stat_reg), - I915_READ(pp_ctrl_reg)); + drm_err(&dev_priv->drm, + "Panel status timeout: status %08x control %08x\n", + intel_de_read(dev_priv, pp_stat_reg), + intel_de_read(dev_priv, pp_ctrl_reg)); - DRM_DEBUG_KMS("Wait complete\n"); + drm_dbg_kms(&dev_priv->drm, "Wait complete\n"); } static void wait_panel_on(struct intel_dp *intel_dp) @@ -2660,9 +2687,9 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); - control = I915_READ(_pp_ctrl_reg(intel_dp)); - if (WARN_ON(!HAS_DDI(dev_priv) && - (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { + control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)); + if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) && + (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { control &= ~PANEL_UNLOCK_MASK; control |= PANEL_UNLOCK_REGS; } @@ -2696,9 +2723,9 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) intel_display_power_get(dev_priv, intel_aux_power_domain(intel_dig_port)); - DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD on\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); if (!edp_have_panel_power(intel_dp)) wait_panel_power_cycle(intel_dp); @@ -2709,17 +2736,19 @@ static bool edp_panel_vdd_on(struct intel_dp *intel_dp) pp_stat_reg = _pp_stat_reg(intel_dp); pp_ctrl_reg = _pp_ctrl_reg(intel_dp); - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); - DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", - I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); + drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", + intel_de_read(dev_priv, pp_stat_reg), + intel_de_read(dev_priv, pp_ctrl_reg)); /* * If the panel wasn't on, delay before accessing aux channel */ if (!edp_have_panel_power(intel_dp)) { - DRM_DEBUG_KMS("[ENCODER:%d:%s] panel power wasn't enabled\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] panel power wasn't enabled\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); msleep(intel_dp->panel_power_up_delay); } @@ -2759,14 +2788,14 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) lockdep_assert_held(&dev_priv->pps_mutex); - WARN_ON(intel_dp->want_panel_vdd); + drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd); if (!edp_have_panel_vdd(intel_dp)) return; - DRM_DEBUG_KMS("Turning [ENCODER:%d:%s] VDD off\n", - intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n", + intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); pp = ilk_get_pp_control(intel_dp); pp &= ~EDP_FORCE_VDD; @@ -2774,12 +2803,13 @@ static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) pp_ctrl_reg = _pp_ctrl_reg(intel_dp); pp_stat_reg = _pp_stat_reg(intel_dp); - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); /* Make sure sequencer is idle before allowing subsequent activity */ - DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", - I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); + drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", + intel_de_read(dev_priv, pp_stat_reg), + intel_de_read(dev_priv, pp_ctrl_reg)); if ((pp & PANEL_POWER_ON) == 0) intel_dp->panel_power_off_time = ktime_get_boottime(); @@ -2851,14 +2881,14 @@ static void edp_panel_on(struct intel_dp *intel_dp) if (!intel_dp_is_edp(intel_dp)) return; - DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power on\n", - dp_to_dig_port(intel_dp)->base.base.base.id, - dp_to_dig_port(intel_dp)->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n", + dp_to_dig_port(intel_dp)->base.base.base.id, + dp_to_dig_port(intel_dp)->base.base.name); - if (WARN(edp_have_panel_power(intel_dp), - "[ENCODER:%d:%s] panel power already on\n", - dp_to_dig_port(intel_dp)->base.base.base.id, - dp_to_dig_port(intel_dp)->base.base.name)) + if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp), + "[ENCODER:%d:%s] panel power already on\n", + dp_to_dig_port(intel_dp)->base.base.base.id, + dp_to_dig_port(intel_dp)->base.base.name)) return; wait_panel_power_cycle(intel_dp); @@ -2868,24 +2898,24 @@ static void edp_panel_on(struct intel_dp *intel_dp) if (IS_GEN(dev_priv, 5)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); } pp |= PANEL_POWER_ON; if (!IS_GEN(dev_priv, 5)) pp |= PANEL_POWER_RESET; - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); wait_panel_on(intel_dp); intel_dp->last_power_on = jiffies; if (IS_GEN(dev_priv, 5)) { pp |= PANEL_POWER_RESET; /* restore panel reset bit */ - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); } } @@ -2913,11 +2943,12 @@ static void edp_panel_off(struct intel_dp *intel_dp) if (!intel_dp_is_edp(intel_dp)) return; - DRM_DEBUG_KMS("Turn [ENCODER:%d:%s] panel power off\n", - dig_port->base.base.base.id, dig_port->base.base.name); + drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n", + dig_port->base.base.base.id, dig_port->base.base.name); - WARN(!intel_dp->want_panel_vdd, "Need [ENCODER:%d:%s] VDD to turn off panel\n", - dig_port->base.base.base.id, dig_port->base.base.name); + drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd, + "Need [ENCODER:%d:%s] VDD to turn off panel\n", + dig_port->base.base.base.id, dig_port->base.base.name); pp = ilk_get_pp_control(intel_dp); /* We need to switch off panel power _and_ force vdd, for otherwise some @@ -2929,8 +2960,8 @@ static void edp_panel_off(struct intel_dp *intel_dp) intel_dp->want_panel_vdd = false; - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); wait_panel_off(intel_dp); intel_dp->panel_power_off_time = ktime_get_boottime(); @@ -2971,8 +3002,8 @@ static void _intel_edp_backlight_on(struct intel_dp *intel_dp) pp = ilk_get_pp_control(intel_dp); pp |= EDP_BLC_ENABLE; - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); } } @@ -3007,8 +3038,8 @@ static void _intel_edp_backlight_off(struct intel_dp *intel_dp) pp = ilk_get_pp_control(intel_dp); pp &= ~EDP_BLC_ENABLE; - I915_WRITE(pp_ctrl_reg, pp); - POSTING_READ(pp_ctrl_reg); + intel_de_write(dev_priv, pp_ctrl_reg, pp); + intel_de_posting_read(dev_priv, pp_ctrl_reg); } intel_dp->last_backlight_off = jiffies; @@ -3059,7 +3090,7 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); - bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; + bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; I915_STATE_WARN(cur_state != state, "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n", @@ -3070,7 +3101,7 @@ static void assert_dp_port(struct intel_dp *intel_dp, bool state) static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) { - bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; + bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; I915_STATE_WARN(cur_state != state, "eDP PLL state assertion failure (expected %s, current %s)\n", @@ -3089,8 +3120,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, assert_dp_port_disabled(intel_dp); assert_edp_pll_disabled(dev_priv); - DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", - pipe_config->port_clock); + drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n", + pipe_config->port_clock); intel_dp->DP &= ~DP_PLL_FREQ_MASK; @@ -3099,8 +3130,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, else intel_dp->DP |= DP_PLL_FREQ_270MHZ; - I915_WRITE(DP_A, intel_dp->DP); - POSTING_READ(DP_A); + intel_de_write(dev_priv, DP_A, intel_dp->DP); + intel_de_posting_read(dev_priv, DP_A); udelay(500); /* @@ -3114,8 +3145,8 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp, intel_dp->DP |= DP_PLL_ENABLE; - I915_WRITE(DP_A, intel_dp->DP); - POSTING_READ(DP_A); + intel_de_write(dev_priv, DP_A, intel_dp->DP); + intel_de_posting_read(dev_priv, DP_A); udelay(200); } @@ -3129,12 +3160,12 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp, assert_dp_port_disabled(intel_dp); assert_edp_pll_enabled(dev_priv); - DRM_DEBUG_KMS("disabling eDP PLL\n"); + drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n"); intel_dp->DP &= ~DP_PLL_ENABLE; - I915_WRITE(DP_A, intel_dp->DP); - POSTING_READ(DP_A); + intel_de_write(dev_priv, DP_A, intel_dp->DP); + intel_de_posting_read(dev_priv, DP_A); udelay(200); } @@ -3149,7 +3180,7 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) * FIXME should really check all downstream ports... */ return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && - intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && + drm_dp_is_branch(intel_dp->dpcd) && intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; } @@ -3214,7 +3245,7 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, enum pipe p; for_each_pipe(dev_priv, p) { - u32 val = I915_READ(TRANS_DP_CTL(p)); + u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { *pipe = p; @@ -3222,7 +3253,8 @@ static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, } } - DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port)); + drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n", + port_name(port)); /* must initialize pipe to something for the asserts */ *pipe = PIPE_A; @@ -3237,7 +3269,7 @@ bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, bool ret; u32 val; - val = I915_READ(dp_reg); + val = intel_de_read(dev_priv, dp_reg); ret = val & DP_PORT_EN; @@ -3289,12 +3321,13 @@ static void intel_dp_get_config(struct intel_encoder *encoder, else pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); - tmp = I915_READ(intel_dp->output_reg); + tmp = intel_de_read(dev_priv, intel_dp->output_reg); pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { - u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); + u32 trans_dp = intel_de_read(dev_priv, + TRANS_DP_CTL(crtc->pipe)); if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; @@ -3328,7 +3361,7 @@ static void intel_dp_get_config(struct intel_encoder *encoder, intel_dp_get_m_n(crtc, pipe_config); if (port == PORT_A) { - if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) + if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) pipe_config->port_clock = 162000; else pipe_config->port_clock = 270000; @@ -3353,8 +3386,9 @@ static void intel_dp_get_config(struct intel_encoder *encoder, * up by the BIOS, and thus we can't get the mode at module * load. */ - DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", - pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); + drm_dbg_kms(&dev_priv->drm, + "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", + pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; } } @@ -3447,11 +3481,12 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); if (dp_train_pat & train_pat_mask) - DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", - dp_train_pat & train_pat_mask); + drm_dbg_kms(&dev_priv->drm, + "Using DP training pattern TPS%d\n", + dp_train_pat & train_pat_mask); if (HAS_DDI(dev_priv)) { - u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl); + u32 temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) temp |= DP_TP_CTL_SCRAMBLE_DISABLE; @@ -3477,7 +3512,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, temp |= DP_TP_CTL_LINK_TRAIN_PAT4; break; } - I915_WRITE(intel_dp->regs.dp_tp_ctl, temp); + intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp); } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { @@ -3494,7 +3529,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, *DP |= DP_LINK_TRAIN_PAT_2_CPT; break; case DP_TRAINING_PATTERN_3: - DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); + drm_dbg_kms(&dev_priv->drm, + "TPS3 not supported, using TPS2 instead\n"); *DP |= DP_LINK_TRAIN_PAT_2_CPT; break; } @@ -3513,7 +3549,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp, *DP |= DP_LINK_TRAIN_PAT_2; break; case DP_TRAINING_PATTERN_3: - DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); + drm_dbg_kms(&dev_priv->drm, + "TPS3 not supported, using TPS2 instead\n"); *DP |= DP_LINK_TRAIN_PAT_2; break; } @@ -3539,8 +3576,8 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp, if (old_crtc_state->has_audio) intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; - I915_WRITE(intel_dp->output_reg, intel_dp->DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); } static void intel_enable_dp(struct intel_encoder *encoder, @@ -3550,11 +3587,11 @@ static void intel_enable_dp(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - u32 dp_reg = I915_READ(intel_dp->output_reg); + u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); enum pipe pipe = crtc->pipe; intel_wakeref_t wakeref; - if (WARN_ON(dp_reg & DP_PORT_EN)) + if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)) return; with_pps_lock(intel_dp, wakeref) { @@ -3583,8 +3620,8 @@ static void intel_enable_dp(struct intel_encoder *encoder, intel_dp_stop_link_train(intel_dp); if (pipe_config->has_audio) { - DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", - pipe_name(pipe)); + drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n", + pipe_name(pipe)); intel_audio_codec_enable(encoder, pipe_config, conn_state); } } @@ -3625,9 +3662,9 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) enum pipe pipe = intel_dp->pps_pipe; i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); - if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) + if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) return; edp_panel_vdd_off_sync(intel_dp); @@ -3641,11 +3678,12 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) * port select always when logically disconnecting a power sequencer * from a port. */ - DRM_DEBUG_KMS("detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", - pipe_name(pipe), intel_dig_port->base.base.base.id, - intel_dig_port->base.base.name); - I915_WRITE(pp_on_reg, 0); - POSTING_READ(pp_on_reg); + drm_dbg_kms(&dev_priv->drm, + "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n", + pipe_name(pipe), intel_dig_port->base.base.base.id, + intel_dig_port->base.base.name); + intel_de_write(dev_priv, pp_on_reg, 0); + intel_de_posting_read(dev_priv, pp_on_reg); intel_dp->pps_pipe = INVALID_PIPE; } @@ -3660,17 +3698,18 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, for_each_intel_dp(&dev_priv->drm, encoder) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - WARN(intel_dp->active_pipe == pipe, - "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", - pipe_name(pipe), encoder->base.base.id, - encoder->base.name); + drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe, + "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n", + pipe_name(pipe), encoder->base.base.id, + encoder->base.name); if (intel_dp->pps_pipe != pipe) continue; - DRM_DEBUG_KMS("stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", - pipe_name(pipe), encoder->base.base.id, - encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n", + pipe_name(pipe), encoder->base.base.id, + encoder->base.name); /* make sure vdd is off before we steal it */ vlv_detach_power_sequencer(intel_dp); @@ -3686,7 +3725,7 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, lockdep_assert_held(&dev_priv->pps_mutex); - WARN_ON(intel_dp->active_pipe != INVALID_PIPE); + drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE); if (intel_dp->pps_pipe != INVALID_PIPE && intel_dp->pps_pipe != crtc->pipe) { @@ -3712,9 +3751,10 @@ static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, /* now it's all ours */ intel_dp->pps_pipe = crtc->pipe; - DRM_DEBUG_KMS("initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", - pipe_name(intel_dp->pps_pipe), encoder->base.base.id, - encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n", + pipe_name(intel_dp->pps_pipe), encoder->base.base.id, + encoder->base.name); /* init power sequencer on this pipe and port */ intel_dp_init_panel_power_sequencer(intel_dp); @@ -4140,18 +4180,22 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) } if (mask) - DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); - - DRM_DEBUG_KMS("Using vswing level %d\n", - train_set & DP_TRAIN_VOLTAGE_SWING_MASK); - DRM_DEBUG_KMS("Using pre-emphasis level %d\n", - (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> - DP_TRAIN_PRE_EMPHASIS_SHIFT); + drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", + signal_levels); + + drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n", + train_set & DP_TRAIN_VOLTAGE_SWING_MASK, + train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : ""); + drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n", + (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> + DP_TRAIN_PRE_EMPHASIS_SHIFT, + train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? + " (max)" : ""); intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; - I915_WRITE(intel_dp->output_reg, intel_dp->DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); } void @@ -4164,8 +4208,8 @@ intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); - I915_WRITE(intel_dp->output_reg, intel_dp->DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); } void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) @@ -4178,10 +4222,10 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) if (!HAS_DDI(dev_priv)) return; - val = I915_READ(intel_dp->regs.dp_tp_ctl); + val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl); val &= ~DP_TP_CTL_LINK_TRAIN_MASK; val |= DP_TP_CTL_LINK_TRAIN_IDLE; - I915_WRITE(intel_dp->regs.dp_tp_ctl, val); + intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val); /* * Until TGL on PORT_A we can have only eDP in SST mode. There the only @@ -4195,7 +4239,8 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_IDLE_DONE, 1)) - DRM_ERROR("Timed out waiting for DP idle patterns\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for DP idle patterns\n"); } static void @@ -4208,10 +4253,12 @@ intel_dp_link_down(struct intel_encoder *encoder, enum port port = encoder->port; u32 DP = intel_dp->DP; - if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) + if (drm_WARN_ON(&dev_priv->drm, + (intel_de_read(dev_priv, intel_dp->output_reg) & + DP_PORT_EN) == 0)) return; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { @@ -4221,12 +4268,12 @@ intel_dp_link_down(struct intel_encoder *encoder, DP &= ~DP_LINK_TRAIN_MASK; DP |= DP_LINK_TRAIN_PAT_IDLE; } - I915_WRITE(intel_dp->output_reg, DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); - I915_WRITE(intel_dp->output_reg, DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); /* * HW workaround for IBX, we need to move the port @@ -4245,12 +4292,12 @@ intel_dp_link_down(struct intel_encoder *encoder, DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | DP_LINK_TRAIN_PAT_1; - I915_WRITE(intel_dp->output_reg, DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); DP &= ~DP_PORT_EN; - I915_WRITE(intel_dp->output_reg, DP); - POSTING_READ(intel_dp->output_reg); + intel_de_write(dev_priv, intel_dp->output_reg, DP); + intel_de_posting_read(dev_priv, intel_dp->output_reg); intel_wait_for_vblank_if_active(dev_priv, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); @@ -4370,7 +4417,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) to_i915(dp_to_dig_port(intel_dp)->base.base.dev); /* this function is meant to be called only once */ - WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); + drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); if (!intel_dp_read_dpcd(intel_dp)) return false; @@ -4390,8 +4437,9 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == sizeof(intel_dp->edp_dpcd)) - DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd), - intel_dp->edp_dpcd); + drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", + (int)sizeof(intel_dp->edp_dpcd), + intel_dp->edp_dpcd); /* * This has to be called after intel_dp->edp_dpcd is filled, PSR checks @@ -4466,7 +4514,8 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) * it don't care about read it here and in intel_edp_init_dpcd(). */ if (!intel_dp_is_edp(intel_dp) && - !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) { + !drm_dp_has_quirk(&intel_dp->desc, 0, + DP_DPCD_QUIRK_NO_SINK_COUNT)) { u8 count; ssize_t r; @@ -5125,7 +5174,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, crtc_state = to_intel_crtc_state(crtc->base.state); - WARN_ON(!intel_crtc_has_dp_encoder(crtc_state)); + drm_WARN_ON(&dev_priv->drm, !intel_crtc_has_dp_encoder(crtc_state)); if (!crtc_state->hw.active) return 0; @@ -5195,7 +5244,8 @@ intel_dp_hotplug(struct intel_encoder *encoder, drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); - WARN(ret, "Acquiring modeset locks failed with %i\n", ret); + drm_WARN(encoder->base.dev, ret, + "Acquiring modeset locks failed with %i\n", ret); /* * Keeping it consistent with intel_ddi_hotplug() and @@ -5281,7 +5331,8 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) intel_psr_short_pulse(intel_dp); if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { - DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); + drm_dbg_kms(&dev_priv->drm, + "Link Training Compliance Test requested\n"); /* Send a Hotplug Uevent to userspace to start modeset */ drm_kms_helper_hotplug_event(&dev_priv->drm); } @@ -5370,7 +5421,7 @@ static bool ibx_digital_port_connected(struct intel_encoder *encoder) return false; } - return I915_READ(SDEISR) & bit; + return intel_de_read(dev_priv, SDEISR) & bit; } static bool cpt_digital_port_connected(struct intel_encoder *encoder) @@ -5393,7 +5444,7 @@ static bool cpt_digital_port_connected(struct intel_encoder *encoder) return false; } - return I915_READ(SDEISR) & bit; + return intel_de_read(dev_priv, SDEISR) & bit; } static bool spt_digital_port_connected(struct intel_encoder *encoder) @@ -5412,7 +5463,7 @@ static bool spt_digital_port_connected(struct intel_encoder *encoder) return cpt_digital_port_connected(encoder); } - return I915_READ(SDEISR) & bit; + return intel_de_read(dev_priv, SDEISR) & bit; } static bool g4x_digital_port_connected(struct intel_encoder *encoder) @@ -5435,7 +5486,7 @@ static bool g4x_digital_port_connected(struct intel_encoder *encoder) return false; } - return I915_READ(PORT_HOTPLUG_STAT) & bit; + return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; } static bool gm45_digital_port_connected(struct intel_encoder *encoder) @@ -5458,7 +5509,7 @@ static bool gm45_digital_port_connected(struct intel_encoder *encoder) return false; } - return I915_READ(PORT_HOTPLUG_STAT) & bit; + return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; } static bool ilk_digital_port_connected(struct intel_encoder *encoder) @@ -5466,7 +5517,7 @@ static bool ilk_digital_port_connected(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (encoder->hpd_pin == HPD_PORT_A) - return I915_READ(DEISR) & DE_DP_A_HOTPLUG; + return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG; else return ibx_digital_port_connected(encoder); } @@ -5476,7 +5527,7 @@ static bool snb_digital_port_connected(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (encoder->hpd_pin == HPD_PORT_A) - return I915_READ(DEISR) & DE_DP_A_HOTPLUG; + return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG; else return cpt_digital_port_connected(encoder); } @@ -5486,7 +5537,7 @@ static bool ivb_digital_port_connected(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (encoder->hpd_pin == HPD_PORT_A) - return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB; + return intel_de_read(dev_priv, DEISR) & DE_DP_A_HOTPLUG_IVB; else return cpt_digital_port_connected(encoder); } @@ -5496,7 +5547,7 @@ static bool bdw_digital_port_connected(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (encoder->hpd_pin == HPD_PORT_A) - return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; + return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; else return cpt_digital_port_connected(encoder); } @@ -5521,16 +5572,16 @@ static bool bxt_digital_port_connected(struct intel_encoder *encoder) return false; } - return I915_READ(GEN8_DE_PORT_ISR) & bit; + return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit; } static bool intel_combo_phy_connected(struct drm_i915_private *dev_priv, enum phy phy) { if (HAS_PCH_MCC(dev_priv) && phy == PHY_C) - return I915_READ(SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); + return intel_de_read(dev_priv, SDEISR) & SDE_TC_HOTPLUG_ICP(PORT_TC1); - return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(phy); + return intel_de_read(dev_priv, SDEISR) & SDE_DDI_HOTPLUG_ICP(phy); } static bool icp_digital_port_connected(struct intel_encoder *encoder) @@ -5631,6 +5682,7 @@ intel_dp_set_edid(struct intel_dp *intel_dp) intel_dp->has_audio = drm_detect_monitor_audio(edid); drm_dp_cec_set_edid(&intel_dp->aux, edid); + intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); } static void @@ -5643,6 +5695,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) intel_connector->detect_edid = NULL; intel_dp->has_audio = false; + intel_dp->edid_quirks = 0; } static int @@ -5656,9 +5709,10 @@ intel_dp_detect(struct drm_connector *connector, struct intel_encoder *encoder = &dig_port->base; enum drm_connector_status status; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); - WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + drm_WARN_ON(&dev_priv->drm, + !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); /* Can't disconnect eDP */ if (intel_dp_is_edp(intel_dp)) @@ -5673,9 +5727,10 @@ intel_dp_detect(struct drm_connector *connector, memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); if (intel_dp->is_mst) { - DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", - intel_dp->is_mst, - intel_dp->mst_mgr.mst_state); + drm_dbg_kms(&dev_priv->drm, + "MST device may have disappeared %d vs %d\n", + intel_dp->is_mst, + intel_dp->mst_mgr.mst_state); intel_dp->is_mst = false; drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); @@ -5763,8 +5818,8 @@ intel_dp_force(struct drm_connector *connector) intel_aux_power_domain(dig_port); intel_wakeref_t wakeref; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); intel_dp_unset_edid(intel_dp); if (connector->status != connector_status_connected) @@ -5815,7 +5870,7 @@ intel_dp_connector_register(struct drm_connector *connector) if (ret) return ret; - i915_debugfs_connector_add(connector); + intel_connector_debugfs_add(connector); DRM_DEBUG_KMS("registering %s bus for %s\n", intel_dp->aux.name, connector->kdev->kobj.name); @@ -6396,6 +6451,7 @@ static int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, bool is_repeater, u8 content_type) { + int ret; struct hdcp2_dp_errata_stream_type stream_type_msg; if (is_repeater) @@ -6411,8 +6467,11 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; stream_type_msg.stream_type = content_type; - return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, + ret = intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, sizeof(stream_type_msg)); + + return ret < 0 ? ret : 0; + } static @@ -6492,7 +6551,8 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) * schedule a vdd off, so we don't hold on to the reference * indefinitely. */ - DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); + drm_dbg_kms(&dev_priv->drm, + "VDD left on by BIOS, adjusting state tracking\n"); intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); edp_panel_vdd_schedule_off(intel_dp); @@ -6519,7 +6579,7 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder) intel_wakeref_t wakeref; if (!HAS_DDI(dev_priv)) - intel_dp->DP = I915_READ(intel_dp->output_reg); + intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); if (lspcon->active) lspcon_resume(lspcon); @@ -6545,6 +6605,140 @@ void intel_dp_encoder_reset(struct drm_encoder *encoder) } } +static int intel_modeset_tile_group(struct intel_atomic_state *state, + int tile_group_id) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct drm_connector_list_iter conn_iter; + struct drm_connector *connector; + int ret = 0; + + drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + struct drm_connector_state *conn_state; + struct intel_crtc_state *crtc_state; + struct intel_crtc *crtc; + + if (!connector->has_tile || + connector->tile_group->id != tile_group_id) + continue; + + conn_state = drm_atomic_get_connector_state(&state->base, + connector); + if (IS_ERR(conn_state)) { + ret = PTR_ERR(conn_state); + break; + } + + crtc = to_intel_crtc(conn_state->crtc); + + if (!crtc) + continue; + + crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + crtc_state->uapi.mode_changed = true; + + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); + if (ret) + break; + } + drm_connector_list_iter_end(&conn_iter); + + return ret; +} + +static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + if (transcoders == 0) + return 0; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + struct intel_crtc_state *crtc_state; + int ret; + + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + if (!crtc_state->hw.enable) + continue; + + if (!(transcoders & BIT(crtc_state->cpu_transcoder))) + continue; + + crtc_state->uapi.mode_changed = true; + + ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); + if (ret) + return ret; + + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); + if (ret) + return ret; + + transcoders &= ~BIT(crtc_state->cpu_transcoder); + } + + drm_WARN_ON(&dev_priv->drm, transcoders != 0); + + return 0; +} + +static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, + struct drm_connector *connector) +{ + const struct drm_connector_state *old_conn_state = + drm_atomic_get_old_connector_state(&state->base, connector); + const struct intel_crtc_state *old_crtc_state; + struct intel_crtc *crtc; + u8 transcoders; + + crtc = to_intel_crtc(old_conn_state->crtc); + if (!crtc) + return 0; + + old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); + + if (!old_crtc_state->hw.active) + return 0; + + transcoders = old_crtc_state->sync_mode_slaves_mask; + if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) + transcoders |= BIT(old_crtc_state->master_transcoder); + + return intel_modeset_affected_transcoders(state, + transcoders); +} + +static int intel_dp_connector_atomic_check(struct drm_connector *conn, + struct drm_atomic_state *_state) +{ + struct drm_i915_private *dev_priv = to_i915(conn->dev); + struct intel_atomic_state *state = to_intel_atomic_state(_state); + int ret; + + ret = intel_digital_connector_atomic_check(conn, &state->base); + if (ret) + return ret; + + if (INTEL_GEN(dev_priv) < 11) + return 0; + + if (!intel_connector_needs_modeset(state, conn)) + return 0; + + if (conn->has_tile) { + ret = intel_modeset_tile_group(state, conn->tile_group->id); + if (ret) + return ret; + } + + return intel_modeset_synced_crtcs(state, conn); +} + static const struct drm_connector_funcs intel_dp_connector_funcs = { .force = intel_dp_force, .fill_modes = drm_helper_probe_single_connector_modes, @@ -6561,7 +6755,7 @@ static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = .detect_ctx = intel_dp_detect, .get_modes = intel_dp_get_modes, .mode_valid = intel_dp_mode_valid, - .atomic_check = intel_digital_connector_atomic_check, + .atomic_check = intel_dp_connector_atomic_check, }; static const struct drm_encoder_funcs intel_dp_enc_funcs = { @@ -6697,10 +6891,10 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) /* Ensure PPS is unlocked */ if (!HAS_DDI(dev_priv)) - I915_WRITE(regs.pp_ctrl, pp_ctl); + intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); - pp_on = I915_READ(regs.pp_on); - pp_off = I915_READ(regs.pp_off); + pp_on = intel_de_read(dev_priv, regs.pp_on); + pp_off = intel_de_read(dev_priv, regs.pp_off); /* Pull timing values out of registers */ seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); @@ -6711,7 +6905,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) if (i915_mmio_reg_valid(regs.pp_div)) { u32 pp_div; - pp_div = I915_READ(regs.pp_div); + pp_div = intel_de_read(dev_priv, regs.pp_div); seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; } else { @@ -6768,8 +6962,9 @@ intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) */ if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); - DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n", - vbt.t11_t12); + drm_dbg_kms(&dev_priv->drm, + "Increasing T12 panel delay as per the quirk to %d\n", + vbt.t11_t12); } /* T11_T12 delay is special and actually in units of 100ms, but zero * based in the hw (so we need to add 100 ms). But the sw vbt @@ -6811,12 +7006,15 @@ intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) intel_dp->panel_power_cycle_delay = get_delay(t11_t12); #undef get_delay - DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", - intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, - intel_dp->panel_power_cycle_delay); + drm_dbg_kms(&dev_priv->drm, + "panel power up delay %d, power down delay %d, power cycle delay %d\n", + intel_dp->panel_power_up_delay, + intel_dp->panel_power_down_delay, + intel_dp->panel_power_cycle_delay); - DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", - intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); + drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n", + intel_dp->backlight_on_delay, + intel_dp->backlight_off_delay); /* * We override the HW backlight delays to 1 because we do manual waits @@ -6841,7 +7039,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u32 pp_on, pp_off, port_sel = 0; - int div = dev_priv->rawclk_freq / 1000; + int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; struct pps_registers regs; enum port port = dp_to_dig_port(intel_dp)->base.port; const struct edp_power_seq *seq = &intel_dp->pps_delays; @@ -6865,14 +7063,16 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, if (force_disable_vdd) { u32 pp = ilk_get_pp_control(intel_dp); - WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); + drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON, + "Panel power already on\n"); if (pp & EDP_FORCE_VDD) - DRM_DEBUG_KMS("VDD already on, disabling first\n"); + drm_dbg_kms(&dev_priv->drm, + "VDD already on, disabling first\n"); pp &= ~EDP_FORCE_VDD; - I915_WRITE(regs.pp_ctrl, pp); + intel_de_write(dev_priv, regs.pp_ctrl, pp); } pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | @@ -6903,31 +7103,31 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, pp_on |= port_sel; - I915_WRITE(regs.pp_on, pp_on); - I915_WRITE(regs.pp_off, pp_off); + intel_de_write(dev_priv, regs.pp_on, pp_on); + intel_de_write(dev_priv, regs.pp_off, pp_off); /* * Compute the divisor for the pp clock, simply match the Bspec formula. */ if (i915_mmio_reg_valid(regs.pp_div)) { - I915_WRITE(regs.pp_div, - REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | - REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); + intel_de_write(dev_priv, regs.pp_div, + REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); } else { u32 pp_ctl; - pp_ctl = I915_READ(regs.pp_ctrl); + pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl); pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); - I915_WRITE(regs.pp_ctrl, pp_ctl); + intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); } - DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", - I915_READ(regs.pp_on), - I915_READ(regs.pp_off), - i915_mmio_reg_valid(regs.pp_div) ? - I915_READ(regs.pp_div) : - (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); + drm_dbg_kms(&dev_priv->drm, + "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", + intel_de_read(dev_priv, regs.pp_on), + intel_de_read(dev_priv, regs.pp_off), + i915_mmio_reg_valid(regs.pp_div) ? + intel_de_read(dev_priv, regs.pp_div) : + (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); } static void intel_dp_pps_init(struct intel_dp *intel_dp) @@ -6964,22 +7164,24 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, enum drrs_refresh_rate_type index = DRRS_HIGH_RR; if (refresh_rate <= 0) { - DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); + drm_dbg_kms(&dev_priv->drm, + "Refresh rate should be positive non-zero.\n"); return; } if (intel_dp == NULL) { - DRM_DEBUG_KMS("DRRS not supported.\n"); + drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); return; } if (!intel_crtc) { - DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS: intel_crtc not initialized\n"); return; } if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { - DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); + drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); return; } @@ -6988,13 +7190,14 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, index = DRRS_LOW_RR; if (index == dev_priv->drrs.refresh_rate_type) { - DRM_DEBUG_KMS( - "DRRS requested for previously set RR...ignoring\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS requested for previously set RR...ignoring\n"); return; } if (!crtc_state->hw.active) { - DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); + drm_dbg_kms(&dev_priv->drm, + "eDP encoder disabled. CRTC not Active\n"); return; } @@ -7008,13 +7211,14 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, break; case DRRS_MAX_RR: default: - DRM_ERROR("Unsupported refreshrate type\n"); + drm_err(&dev_priv->drm, + "Unsupported refreshrate type\n"); } } else if (INTEL_GEN(dev_priv) > 6) { i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); u32 val; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if (index > DRRS_HIGH_RR) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; @@ -7026,12 +7230,13 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, else val &= ~PIPECONF_EDP_RR_MODE_SWITCH; } - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } dev_priv->drrs.refresh_rate_type = index; - DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); + drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", + refresh_rate); } /** @@ -7047,18 +7252,19 @@ void intel_edp_drrs_enable(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); if (!crtc_state->has_drrs) { - DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); + drm_dbg_kms(&dev_priv->drm, "Panel doesn't support DRRS\n"); return; } if (dev_priv->psr.enabled) { - DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR enabled. Not enabling DRRS.\n"); return; } mutex_lock(&dev_priv->drrs.mutex); if (dev_priv->drrs.dp) { - DRM_DEBUG_KMS("DRRS already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "DRRS already enabled\n"); goto unlock; } @@ -7284,25 +7490,28 @@ intel_dp_drrs_init(struct intel_connector *connector, mutex_init(&dev_priv->drrs.mutex); if (INTEL_GEN(dev_priv) <= 6) { - DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); + drm_dbg_kms(&dev_priv->drm, + "DRRS supported for Gen7 and above\n"); return NULL; } if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { - DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); + drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); return NULL; } downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); if (!downclock_mode) { - DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); + drm_dbg_kms(&dev_priv->drm, + "Downclock mode is not found. DRRS not supported\n"); return NULL; } dev_priv->drrs.type = dev_priv->vbt.drrs_type; dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; - DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); + drm_dbg_kms(&dev_priv->drm, + "seamless DRRS supported for eDP panel.\n"); return downclock_mode; } @@ -7331,8 +7540,10 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, * with an already powered-on LVDS power sequencer. */ if (intel_get_lvds_encoder(dev_priv)) { - WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); - DRM_INFO("LVDS was detected, not registering eDP\n"); + drm_WARN_ON(dev, + !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); + drm_info(&dev_priv->drm, + "LVDS was detected, not registering eDP\n"); return false; } @@ -7348,7 +7559,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, if (!has_dpcd) { /* if this fails, presume the device is a ghost */ - DRM_INFO("failed to retrieve link info, disabling eDP\n"); + drm_info(&dev_priv->drm, + "failed to retrieve link info, disabling eDP\n"); goto out_vdd_off; } @@ -7356,8 +7568,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, edid = drm_get_edid(connector, &intel_dp->aux.ddc); if (edid) { if (drm_add_edid_modes(connector, edid)) { - drm_connector_update_edid_property(connector, - edid); + drm_connector_update_edid_property(connector, edid); + intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); } else { kfree(edid); edid = ERR_PTR(-EINVAL); @@ -7393,17 +7605,20 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, if (pipe != PIPE_A && pipe != PIPE_B) pipe = PIPE_A; - DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", - pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, + "using pipe %c for initial backlight setup\n", + pipe_name(pipe)); } intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); intel_connector->panel.backlight.power = intel_edp_backlight_power; intel_panel_setup_backlight(connector, pipe); - if (fixed_mode) - drm_connector_init_panel_orientation_property( - connector, fixed_mode->hdisplay, fixed_mode->vdisplay); + if (fixed_mode) { + drm_connector_set_panel_orientation_with_quirk(connector, + dev_priv->vbt.orientation, + fixed_mode->hdisplay, fixed_mode->vdisplay); + } return true; @@ -7459,10 +7674,10 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, INIT_WORK(&intel_connector->modeset_retry_work, intel_dp_modeset_retry_work_fn); - if (WARN(intel_dig_port->max_lanes < 1, - "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, - intel_encoder->base.name)) + if (drm_WARN(dev, intel_dig_port->max_lanes < 1, + "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", + intel_dig_port->max_lanes, intel_encoder->base.base.id, + intel_encoder->base.name)) return false; intel_dp_set_source_rates(intel_dp); @@ -7472,7 +7687,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_dp->active_pipe = INVALID_PIPE; /* Preserve the current hw state. */ - intel_dp->DP = I915_READ(intel_dp->output_reg); + intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); intel_dp->attached_connector = intel_connector; if (intel_dp_is_port_edp(dev_priv, port)) { @@ -7480,7 +7695,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, * Currently we don't support eDP on TypeC ports, although in * theory it could work on TypeC legacy ports. */ - WARN_ON(intel_phy_is_tc(dev_priv, phy)); + drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); type = DRM_MODE_CONNECTOR_eDP; } else { type = DRM_MODE_CONNECTOR_DisplayPort; @@ -7498,14 +7713,16 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, intel_encoder->type = INTEL_OUTPUT_EDP; /* eDP only on port B and/or C on vlv/chv */ - if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && - intel_dp_is_edp(intel_dp) && - port != PORT_B && port != PORT_C)) + if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || + IS_CHERRYVIEW(dev_priv)) && + intel_dp_is_edp(intel_dp) && + port != PORT_B && port != PORT_C)) return false; - DRM_DEBUG_KMS("Adding %s connector on [ENCODER:%d:%s]\n", - type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", - intel_encoder->base.base.id, intel_encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "Adding %s connector on [ENCODER:%d:%s]\n", + type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", + intel_encoder->base.base.id, intel_encoder->base.name); drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); @@ -7518,6 +7735,7 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, connector->ycbcr_420_allowed = true; intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; intel_dp_aux_init(intel_dp); @@ -7543,7 +7761,8 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); if (ret) - DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); + drm_dbg_kms(&dev_priv->drm, + "HDCP init failed, skipping.\n"); } /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written @@ -7551,8 +7770,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port, * generated on the port when a cable is not attached. */ if (IS_G45(dev_priv)) { - u32 temp = I915_READ(PEG_BAND_GAP_DATA); - I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); + u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); + intel_de_write(dev_priv, PEG_BAND_GAP_DATA, + (temp & ~0xf) | 0xd); } return true; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 3da166054788..0c7be8ed1423 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -8,8 +8,6 @@ #include <linux/types.h> -#include <drm/i915_drm.h> - #include "i915_reg.h" enum pipe; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 7c653f8c307f..3e706bb850a8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -57,10 +57,27 @@ static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable) */ static u32 intel_dp_aux_get_backlight(struct intel_connector *connector) { - struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct intel_dp *intel_dp = intel_attached_dp(connector); u8 read_val[2] = { 0x0 }; + u8 mode_reg; u16 level = 0; + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_EDP_BACKLIGHT_MODE_SET_REGISTER, + &mode_reg) != 1) { + DRM_DEBUG_KMS("Failed to read the DPCD register 0x%x\n", + DP_EDP_BACKLIGHT_MODE_SET_REGISTER); + return 0; + } + + /* + * If we're not in DPCD control mode yet, the programmed brightness + * value is meaningless and we should assume max brightness + */ + if ((mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != + DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) + return connector->panel.backlight.max; + if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val, sizeof(read_val)) < 0) { DRM_DEBUG_KMS("Failed to read DPCD register 0x%x\n", @@ -82,7 +99,7 @@ static void intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct intel_dp *intel_dp = intel_attached_dp(connector); u8 vals[2] = { 0x0 }; vals[0] = level; @@ -110,62 +127,29 @@ intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32 lev static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); - int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1; - u8 pn, pn_min, pn_max; + struct intel_dp *intel_dp = intel_attached_dp(connector); + const u8 pn = connector->panel.backlight.pwmgen_bit_count; + int freq, fxp, f, fxp_actual, fxp_min, fxp_max; - /* Find desired value of (F x P) - * Note that, if F x P is out of supported range, the maximum value or - * minimum value will applied automatically. So no need to check that. - */ freq = dev_priv->vbt.backlight.pwm_freq_hz; - DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq); if (!freq) { DRM_DEBUG_KMS("Use panel default backlight frequency\n"); return false; } fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq); + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); + fxp_actual = f << pn; - /* Use highest possible value of Pn for more granularity of brightness - * adjustment while satifying the conditions below. - * - Pn is in the range of Pn_min and Pn_max - * - F is in the range of 1 and 255 - * - FxP is within 25% of desired value. - * Note: 25% is arbitrary value and may need some tweak. - */ - if (drm_dp_dpcd_readb(&intel_dp->aux, - DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) { - DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n"); - return false; - } - if (drm_dp_dpcd_readb(&intel_dp->aux, - DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) { - DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n"); - return false; - } - pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; - pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; - + /* Ensure frequency is within 25% of desired value */ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); - if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { - DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n"); - return false; - } - - for (pn = pn_max; pn >= pn_min; pn--) { - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); - fxp_actual = f << pn; - if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) - break; - } - if (drm_dp_dpcd_writeb(&intel_dp->aux, - DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) { - DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n"); + if (fxp_min > fxp_actual || fxp_actual > fxp_max) { + DRM_DEBUG_KMS("Actual frequency out of range\n"); return false; } + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) { DRM_DEBUG_KMS("Failed to write aux backlight freq\n"); @@ -178,7 +162,8 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st const struct drm_connector_state *conn_state) { struct intel_connector *connector = to_intel_connector(conn_state->connector); - struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct intel_dp *intel_dp = intel_attached_dp(connector); + struct intel_panel *panel = &connector->panel; u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode; if (drm_dp_dpcd_readb(&intel_dp->aux, @@ -197,6 +182,12 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT: new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK; new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; + + if (drm_dp_dpcd_writeb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT, + panel->backlight.pwmgen_bit_count) < 0) + DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n"); + break; /* Do nothing when it is already DPCD mode */ @@ -216,8 +207,9 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st } } + intel_dp_aux_set_backlight(conn_state, + connector->panel.backlight.level); set_aux_backlight_enable(intel_dp, true); - intel_dp_aux_set_backlight(conn_state, connector->panel.backlight.level); } static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -226,20 +218,91 @@ static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old false); } +static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_attached_dp(connector); + struct intel_panel *panel = &connector->panel; + u32 max_backlight = 0; + int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1; + u8 pn, pn_min, pn_max; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) == 1) { + pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + max_backlight = (1 << pn) - 1; + } + + /* Find desired value of (F x P) + * Note that, if F x P is out of supported range, the maximum value or + * minimum value will applied automatically. So no need to check that. + */ + freq = i915->vbt.backlight.pwm_freq_hz; + DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", freq); + if (!freq) { + DRM_DEBUG_KMS("Use panel default backlight frequency\n"); + return max_backlight; + } + + fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq); + + /* Use highest possible value of Pn for more granularity of brightness + * adjustment while satifying the conditions below. + * - Pn is in the range of Pn_min and Pn_max + * - F is in the range of 1 and 255 + * - FxP is within 25% of desired value. + * Note: 25% is arbitrary value and may need some tweak. + */ + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) { + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap min\n"); + return max_backlight; + } + if (drm_dp_dpcd_readb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) { + DRM_DEBUG_KMS("Failed to read pwmgen bit count cap max\n"); + return max_backlight; + } + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; + + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { + DRM_DEBUG_KMS("VBT defined backlight frequency out of range\n"); + return max_backlight; + } + + for (pn = pn_max; pn >= pn_min; pn--) { + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); + fxp_actual = f << pn; + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) + break; + } + + DRM_DEBUG_KMS("Using eDP pwmgen bit count of %d\n", pn); + if (drm_dp_dpcd_writeb(&intel_dp->aux, + DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) { + DRM_DEBUG_KMS("Failed to write aux pwmgen bit count\n"); + return max_backlight; + } + panel->backlight.pwmgen_bit_count = pn; + + max_backlight = (1 << pn) - 1; + + return max_backlight; +} + static int intel_dp_aux_setup_backlight(struct intel_connector *connector, enum pipe pipe) { - struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); struct intel_panel *panel = &connector->panel; - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) - panel->backlight.max = 0xFFFF; - else - panel->backlight.max = 0xFF; + panel->backlight.max = intel_dp_aux_calc_max_backlight(connector); + if (!panel->backlight.max) + return -ENODEV; panel->backlight.min = 0; panel->backlight.level = intel_dp_aux_get_backlight(connector); - panel->backlight.enabled = panel->backlight.level != 0; return 0; @@ -248,7 +311,7 @@ static int intel_dp_aux_setup_backlight(struct intel_connector *connector, static bool intel_dp_aux_display_control_capable(struct intel_connector *connector) { - struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct intel_dp *intel_dp = intel_attached_dp(connector); /* Check the eDP Display control capabilities registers to determine if * the panel can support backlight control over the aux channel @@ -265,15 +328,31 @@ intel_dp_aux_display_control_capable(struct intel_connector *connector) int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) { struct intel_panel *panel = &intel_connector->panel; - struct drm_i915_private *dev_priv = to_i915(intel_connector->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder); + struct drm_device *dev = intel_connector->base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); if (i915_modparams.enable_dpcd_backlight == 0 || - (i915_modparams.enable_dpcd_backlight == -1 && - dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE)) + !intel_dp_aux_display_control_capable(intel_connector)) return -ENODEV; - if (!intel_dp_aux_display_control_capable(intel_connector)) + /* + * There are a lot of machines that don't advertise the backlight + * control interface to use properly in their VBIOS, :\ + */ + if (dev_priv->vbt.backlight.type != + INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE && + !drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks, + DP_QUIRK_FORCE_DPCD_BACKLIGHT)) { + DRM_DEV_INFO(dev->dev, + "Panel advertises DPCD backlight support, but " + "VBT disagrees. If your backlight controls " + "don't work try booting with " + "i915.enable_dpcd_backlight=1. If your machine " + "needs this, please file a _new_ bug report on " + "drm/i915, see " FDO_BUG_URL " for details.\n"); return -ENODEV; + } panel->backlight.setup = intel_dp_aux_setup_backlight; panel->backlight.enable = intel_dp_aux_enable_backlight; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 2a1130dd1ad0..a7defb37ab00 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -130,6 +130,7 @@ static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp) static bool intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 voltage; int voltage_tries, cr_tries, max_cr_tries; bool max_vswing_reached = false; @@ -143,9 +144,11 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) &link_bw, &rate_select); if (link_bw) - DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw); + drm_dbg_kms(&i915->drm, + "Using LINK_BW_SET value %02x\n", link_bw); else - DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select); + drm_dbg_kms(&i915->drm, + "Using LINK_RATE_SET value %02x\n", rate_select); /* Write the link configuration data */ link_config[0] = link_bw; @@ -169,7 +172,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) if (!intel_dp_reset_link_train(intel_dp, DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) { - DRM_ERROR("failed to enable link training\n"); + drm_err(&i915->drm, "failed to enable link training\n"); return false; } @@ -193,22 +196,23 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); if (!intel_dp_get_link_status(intel_dp, link_status)) { - DRM_ERROR("failed to get link status\n"); + drm_err(&i915->drm, "failed to get link status\n"); return false; } if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { - DRM_DEBUG_KMS("clock recovery OK\n"); + drm_dbg_kms(&i915->drm, "clock recovery OK\n"); return true; } if (voltage_tries == 5) { - DRM_DEBUG_KMS("Same voltage tried 5 times\n"); + drm_dbg_kms(&i915->drm, + "Same voltage tried 5 times\n"); return false; } if (max_vswing_reached) { - DRM_DEBUG_KMS("Max Voltage Swing reached\n"); + drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); return false; } @@ -217,7 +221,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) /* Update training set as requested by target */ intel_get_adjust_train(intel_dp, link_status); if (!intel_dp_update_link_train(intel_dp)) { - DRM_ERROR("failed to update link training\n"); + drm_err(&i915->drm, + "failed to update link training\n"); return false; } @@ -231,7 +236,8 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp) max_vswing_reached = true; } - DRM_ERROR("Failed clock recovery %d times, giving up!\n", max_cr_tries); + drm_err(&i915->drm, + "Failed clock recovery %d times, giving up!\n", max_cr_tries); return false; } @@ -256,9 +262,11 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) return DP_TRAINING_PATTERN_4; } else if (intel_dp->link_rate == 810000) { if (!source_tps4) - DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "8.1 Gbps link rate without source HBR3/TPS4 support\n"); if (!sink_tps4) - DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "8.1 Gbps link rate without sink TPS4 support\n"); } /* * Intel platforms that support HBR2 also support TPS3. TPS3 support is @@ -271,9 +279,11 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) return DP_TRAINING_PATTERN_3; } else if (intel_dp->link_rate >= 540000) { if (!source_tps3) - DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); if (!sink_tps3) - DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); } return DP_TRAINING_PATTERN_2; @@ -282,6 +292,7 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp) static bool intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); int tries; u32 training_pattern; u8 link_status[DP_LINK_STATUS_SIZE]; @@ -295,7 +306,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) /* channel equalization */ if (!intel_dp_set_link_train(intel_dp, training_pattern)) { - DRM_ERROR("failed to start channel equalization\n"); + drm_err(&i915->drm, "failed to start channel equalization\n"); return false; } @@ -303,7 +314,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); if (!intel_dp_get_link_status(intel_dp, link_status)) { - DRM_ERROR("failed to get link status\n"); + drm_err(&i915->drm, + "failed to get link status\n"); break; } @@ -311,23 +323,25 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { intel_dp_dump_link_status(link_status); - DRM_DEBUG_KMS("Clock recovery check failed, cannot " - "continue channel equalization\n"); + drm_dbg_kms(&i915->drm, + "Clock recovery check failed, cannot " + "continue channel equalization\n"); break; } if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { channel_eq = true; - DRM_DEBUG_KMS("Channel EQ done. DP Training " - "successful\n"); + drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training " + "successful\n"); break; } /* Update training set as requested by target */ intel_get_adjust_train(intel_dp, link_status); if (!intel_dp_update_link_train(intel_dp)) { - DRM_ERROR("failed to update link training\n"); + drm_err(&i915->drm, + "failed to update link training\n"); break; } } @@ -335,7 +349,8 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp) /* Try 5 times, else fail and try at lower BW */ if (tries == 5) { intel_dp_dump_link_status(link_status); - DRM_DEBUG_KMS("Channel equalization failed 5 times\n"); + drm_dbg_kms(&i915->drm, + "Channel equalization failed 5 times\n"); } intel_dp_set_idle_link_train(intel_dp); @@ -362,17 +377,19 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) if (!intel_dp_link_training_channel_equalization(intel_dp)) goto failure_handling; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", - intel_connector->base.base.id, - intel_connector->base.name, - intel_dp->link_rate, intel_dp->lane_count); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, + intel_dp->link_rate, intel_dp->lane_count); return; failure_handling: - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", - intel_connector->base.base.id, - intel_connector->base.name, - intel_dp->link_rate, intel_dp->lane_count); + drm_dbg_kms(&dp_to_i915(intel_dp)->drm, + "[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d", + intel_connector->base.base.id, + intel_connector->base.name, + intel_dp->link_rate, intel_dp->lane_count); if (!intel_dp_get_link_train_fallback_values(intel_dp, intel_dp->link_rate, intel_dp->lane_count)) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index cba68c5a80fa..44f3fd251ca1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -50,7 +50,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; void *port = connector->port; - bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_CONSTANT_N); int bpp, slots = -EINVAL; @@ -352,8 +352,9 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, intel_dp->active_mst_links--; last_mst_stream = intel_dp->active_mst_links == 0; - WARN_ON(INTEL_GEN(dev_priv) >= 12 && last_mst_stream && - !intel_dp_mst_is_master_trans(old_crtc_state)); + drm_WARN_ON(&dev_priv->drm, + INTEL_GEN(dev_priv) >= 12 && last_mst_stream && + !intel_dp_mst_is_master_trans(old_crtc_state)); intel_crtc_vblank_off(old_crtc_state); @@ -361,9 +362,12 @@ static void intel_mst_post_disable_dp(struct intel_encoder *encoder, drm_dp_update_payload_part2(&intel_dp->mst_mgr); - val = I915_READ(TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder)); + val = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder)); val &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; - I915_WRITE(TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), val); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), + val); if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, DP_TP_STATUS_ACT_SENT, 1)) @@ -437,8 +441,9 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, connector->encoder = encoder; intel_mst->connector = connector; first_mst_stream = intel_dp->active_mst_links == 0; - WARN_ON(INTEL_GEN(dev_priv) >= 12 && first_mst_stream && - !intel_dp_mst_is_master_trans(pipe_config)); + drm_WARN_ON(&dev_priv->drm, + INTEL_GEN(dev_priv) >= 12 && first_mst_stream && + !intel_dp_mst_is_master_trans(pipe_config)); DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); @@ -459,8 +464,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, DRM_ERROR("failed to allocate vcpi\n"); intel_dp->active_mst_links++; - temp = I915_READ(intel_dp->regs.dp_tp_status); - I915_WRITE(intel_dp->regs.dp_tp_status, temp); + temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_status); + intel_de_write(dev_priv, intel_dp->regs.dp_tp_status, temp); ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); @@ -475,6 +480,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder, intel_ddi_enable_pipe_clock(pipe_config); intel_ddi_set_dp_msa(pipe_config, conn_state); + + intel_dp_set_m_n(pipe_config, M1_N1); } static void intel_mst_enable_dp(struct intel_encoder *encoder, @@ -486,6 +493,12 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = &intel_dig_port->dp; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); + + intel_enable_pipe(pipe_config); + + intel_crtc_vblank_on(pipe_config); + DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links); if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status, @@ -535,12 +548,41 @@ static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) return ret; } +static int +intel_dp_mst_connector_late_register(struct drm_connector *connector) +{ + struct intel_connector *intel_connector = to_intel_connector(connector); + int ret; + + ret = drm_dp_mst_connector_late_register(connector, + intel_connector->port); + if (ret < 0) + return ret; + + ret = intel_connector_register(connector); + if (ret < 0) + drm_dp_mst_connector_early_unregister(connector, + intel_connector->port); + + return ret; +} + +static void +intel_dp_mst_connector_early_unregister(struct drm_connector *connector) +{ + struct intel_connector *intel_connector = to_intel_connector(connector); + + intel_connector_unregister(connector); + drm_dp_mst_connector_early_unregister(connector, + intel_connector->port); +} + static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .atomic_get_property = intel_digital_connector_atomic_get_property, .atomic_set_property = intel_digital_connector_atomic_set_property, - .late_register = intel_connector_register, - .early_unregister = intel_connector_unregister, + .late_register = intel_dp_mst_connector_late_register, + .early_unregister = intel_dp_mst_connector_early_unregister, .destroy = intel_connector_destroy, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_duplicate_state = intel_digital_connector_duplicate_state, @@ -632,9 +674,9 @@ static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) { - if (connector->encoder && connector->base.state->crtc) { + if (intel_attached_encoder(connector) && connector->base.state->crtc) { enum pipe pipe; - if (!connector->encoder->get_hw_state(connector->encoder, &pipe)) + if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe)) return false; return true; } @@ -706,36 +748,8 @@ err: return NULL; } -static void intel_dp_register_mst_connector(struct drm_connector *connector) -{ - struct drm_i915_private *dev_priv = to_i915(connector->dev); - - if (dev_priv->fbdev) - drm_fb_helper_add_one_connector(&dev_priv->fbdev->helper, - connector); - - drm_connector_register(connector); -} - -static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, - struct drm_connector *connector) -{ - struct drm_i915_private *dev_priv = to_i915(connector->dev); - - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, connector->name); - drm_connector_unregister(connector); - - if (dev_priv->fbdev) - drm_fb_helper_remove_one_connector(&dev_priv->fbdev->helper, - connector); - - drm_connector_put(connector); -} - static const struct drm_dp_mst_topology_cbs mst_cbs = { .add_connector = intel_dp_add_mst_connector, - .register_connector = intel_dp_register_mst_connector, - .destroy_connector = intel_dp_destroy_mst_connector, }; static struct intel_dp_mst_encoder * diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index 6fb1f7a7364e..399a7edb4568 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -259,7 +259,8 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, } } - WARN(1, "PHY not found for PORT %c", port_name(port)); + drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", + port_name(port)); *phy = DPIO_PHY0; *ch = DPIO_CH0; } @@ -278,33 +279,34 @@ void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, * While we write to the group register to program all lanes at once we * can read only lane registers and we pick lanes 0/1 for that. */ - val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); + val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); - I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); + intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); - val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); + val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; - I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); + intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); - val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); + val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); val &= ~SCALE_DCOMP_METHOD; if (enable) val |= SCALE_DCOMP_METHOD; if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) - DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set"); + drm_err(&dev_priv->drm, + "Disabled scaling while ouniqetrangenmethod was set"); - I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); + intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val); - val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); + val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); val &= ~DE_EMPHASIS; val |= deemphasis << DEEMPH_SHIFT; - I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); + intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); - val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); + val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; - I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); + intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); } bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, @@ -314,20 +316,20 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, phy_info = bxt_get_phy_info(dev_priv, phy); - if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) + if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) return false; - if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & + if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { - DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n", - phy); + drm_dbg(&dev_priv->drm, + "DDI PHY %d powered, but power hasn't settled\n", phy); return false; } - if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { - DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n", - phy); + if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { + drm_dbg(&dev_priv->drm, + "DDI PHY %d powered, but still in reset\n", phy); return false; } @@ -337,7 +339,7 @@ bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) { - u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); + u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; } @@ -347,7 +349,8 @@ static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, { if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy), GRC_DONE, 10)) - DRM_ERROR("timeout waiting for PHY%d GRC\n", phy); + drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", + phy); } static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, @@ -364,18 +367,19 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); if (bxt_ddi_phy_verify_state(dev_priv, phy)) { - DRM_DEBUG_DRIVER("DDI PHY %d already enabled, " - "won't reprogram it\n", phy); + drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " + "won't reprogram it\n", phy); return; } - DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, " - "force reprogramming it\n", phy); + drm_dbg(&dev_priv->drm, + "DDI PHY %d enabled with invalid state, " + "force reprogramming it\n", phy); } - val = I915_READ(BXT_P_CR_GT_DISP_PWRON); + val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); val |= phy_info->pwron_mask; - I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); + intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); /* * The PHY registers start out inaccessible and respond to reads with @@ -390,29 +394,30 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1)) - DRM_ERROR("timeout during PHY%d power on\n", phy); + drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", + phy); /* Program PLL Rcomp code offset */ - val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); + val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy)); val &= ~IREF0RC_OFFSET_MASK; val |= 0xE4 << IREF0RC_OFFSET_SHIFT; - I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); + intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val); - val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); + val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy)); val &= ~IREF1RC_OFFSET_MASK; val |= 0xE4 << IREF1RC_OFFSET_SHIFT; - I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); + intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val); /* Program power gating */ - val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); + val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy)); val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; - I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); + intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val); if (phy_info->dual_channel) { - val = I915_READ(BXT_PORT_CL2CM_DW6(phy)); + val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy)); val |= DW6_OLDO_DYN_PWR_DOWN_EN; - I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); + intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val); } if (phy_info->rcomp_phy != -1) { @@ -430,19 +435,19 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, grc_code = val << GRC_CODE_FAST_SHIFT | val << GRC_CODE_SLOW_SHIFT | val; - I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code); + intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code); - val = I915_READ(BXT_PORT_REF_DW8(phy)); + val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy)); val |= GRC_DIS | GRC_RDY_OVRD; - I915_WRITE(BXT_PORT_REF_DW8(phy), val); + intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val); } if (phy_info->reset_delay) udelay(phy_info->reset_delay); - val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); + val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); val |= COMMON_RESET_DIS; - I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); + intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); } void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) @@ -452,13 +457,13 @@ void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) phy_info = bxt_get_phy_info(dev_priv, phy); - val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); + val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); val &= ~COMMON_RESET_DIS; - I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); + intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); - val = I915_READ(BXT_P_CR_GT_DISP_PWRON); + val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); val &= ~phy_info->pwron_mask; - I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); + intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); } void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) @@ -496,7 +501,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, va_list args; u32 val; - val = I915_READ(reg); + val = intel_de_read(dev_priv, reg); if ((val & mask) == expected) return true; @@ -504,7 +509,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, vaf.fmt = reg_fmt; vaf.va = &args; - DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: " + drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " "current %08x, expected %08x (mask %08x)\n", phy, &vaf, reg.reg, val, (val & ~mask) | expected, mask); @@ -599,7 +604,8 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); for (lane = 0; lane < 4; lane++) { - u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); + u32 val = intel_de_read(dev_priv, + BXT_PORT_TX_DW14_LN(phy, ch, lane)); /* * Note that on CHV this flag is called UPAR, but has @@ -609,7 +615,8 @@ void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, if (lane_lat_optim_mask & BIT(lane)) val |= LATENCY_OPTIM; - I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); + intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), + val); } } @@ -627,7 +634,8 @@ bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) mask = 0; for (lane = 0; lane < 4; lane++) { - u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); + u32 val = intel_de_read(dev_priv, + BXT_PORT_TX_DW14_LN(phy, ch, lane)); if (val & LATENCY_OPTIM) mask |= BIT(lane); diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index c75e34d87111..2d47f1f756a2 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -45,6 +45,22 @@ * commit phase. */ +struct intel_dpll_mgr { + const struct dpll_info *dpll_info; + + bool (*get_dplls)(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder); + void (*put_dplls)(struct intel_atomic_state *state, + struct intel_crtc *crtc); + void (*update_active_dpll)(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_encoder *encoder); + void (*update_ref_clks)(struct drm_i915_private *i915); + void (*dump_hw_state)(struct drm_i915_private *dev_priv, + const struct intel_dpll_hw_state *hw_state); +}; + static void intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, struct intel_shared_dpll_state *shared_dpll) @@ -52,8 +68,8 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv, enum intel_dpll_id i; /* Copy shared dpll state */ - for (i = 0; i < dev_priv->num_shared_dpll; i++) { - struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; + for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { + struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i]; shared_dpll[i] = pll->state; } @@ -88,7 +104,7 @@ struct intel_shared_dpll * intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, enum intel_dpll_id id) { - return &dev_priv->shared_dplls[id]; + return &dev_priv->dpll.shared_dplls[id]; } /** @@ -103,11 +119,14 @@ enum intel_dpll_id intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - if (WARN_ON(pll < dev_priv->shared_dplls|| - pll > &dev_priv->shared_dplls[dev_priv->num_shared_dpll])) + long pll_idx = pll - dev_priv->dpll.shared_dplls; + + if (drm_WARN_ON(&dev_priv->drm, + pll_idx < 0 || + pll_idx >= dev_priv->dpll.num_shared_dpll)) return -1; - return (enum intel_dpll_id) (pll - dev_priv->shared_dplls); + return pll_idx; } /* For ILK+ */ @@ -118,7 +137,8 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv, bool cur_state; struct intel_dpll_hw_state hw_state; - if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) + if (drm_WARN(&dev_priv->drm, !pll, + "asserting DPLL %s with no DPLL\n", onoff(state))) return; cur_state = pll->info->funcs->get_hw_state(dev_priv, pll, &hw_state); @@ -140,19 +160,19 @@ void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_shared_dpll *pll = crtc_state->shared_dpll; - if (WARN_ON(pll == NULL)) + if (drm_WARN_ON(&dev_priv->drm, pll == NULL)) return; - mutex_lock(&dev_priv->dpll_lock); - WARN_ON(!pll->state.crtc_mask); + mutex_lock(&dev_priv->dpll.lock); + drm_WARN_ON(&dev_priv->drm, !pll->state.crtc_mask); if (!pll->active_mask) { - DRM_DEBUG_DRIVER("setting up %s\n", pll->info->name); - WARN_ON(pll->on); + drm_dbg(&dev_priv->drm, "setting up %s\n", pll->info->name); + drm_WARN_ON(&dev_priv->drm, pll->on); assert_shared_dpll_disabled(dev_priv, pll); pll->info->funcs->prepare(dev_priv, pll); } - mutex_unlock(&dev_priv->dpll_lock); + mutex_unlock(&dev_priv->dpll.lock); } /** @@ -169,35 +189,36 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state) unsigned int crtc_mask = drm_crtc_mask(&crtc->base); unsigned int old_mask; - if (WARN_ON(pll == NULL)) + if (drm_WARN_ON(&dev_priv->drm, pll == NULL)) return; - mutex_lock(&dev_priv->dpll_lock); + mutex_lock(&dev_priv->dpll.lock); old_mask = pll->active_mask; - if (WARN_ON(!(pll->state.crtc_mask & crtc_mask)) || - WARN_ON(pll->active_mask & crtc_mask)) + if (drm_WARN_ON(&dev_priv->drm, !(pll->state.crtc_mask & crtc_mask)) || + drm_WARN_ON(&dev_priv->drm, pll->active_mask & crtc_mask)) goto out; pll->active_mask |= crtc_mask; - DRM_DEBUG_KMS("enable %s (active %x, on? %d) for crtc %d\n", - pll->info->name, pll->active_mask, pll->on, - crtc->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "enable %s (active %x, on? %d) for crtc %d\n", + pll->info->name, pll->active_mask, pll->on, + crtc->base.base.id); if (old_mask) { - WARN_ON(!pll->on); + drm_WARN_ON(&dev_priv->drm, !pll->on); assert_shared_dpll_enabled(dev_priv, pll); goto out; } - WARN_ON(pll->on); + drm_WARN_ON(&dev_priv->drm, pll->on); - DRM_DEBUG_KMS("enabling %s\n", pll->info->name); + drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name); pll->info->funcs->enable(dev_priv, pll); pll->on = true; out: - mutex_unlock(&dev_priv->dpll_lock); + mutex_unlock(&dev_priv->dpll.lock); } /** @@ -220,27 +241,28 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) if (pll == NULL) return; - mutex_lock(&dev_priv->dpll_lock); - if (WARN_ON(!(pll->active_mask & crtc_mask))) + mutex_lock(&dev_priv->dpll.lock); + if (drm_WARN_ON(&dev_priv->drm, !(pll->active_mask & crtc_mask))) goto out; - DRM_DEBUG_KMS("disable %s (active %x, on? %d) for crtc %d\n", - pll->info->name, pll->active_mask, pll->on, - crtc->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "disable %s (active %x, on? %d) for crtc %d\n", + pll->info->name, pll->active_mask, pll->on, + crtc->base.base.id); assert_shared_dpll_enabled(dev_priv, pll); - WARN_ON(!pll->on); + drm_WARN_ON(&dev_priv->drm, !pll->on); pll->active_mask &= ~crtc_mask; if (pll->active_mask) goto out; - DRM_DEBUG_KMS("disabling %s\n", pll->info->name); + drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name); pll->info->funcs->disable(dev_priv, pll); pll->on = false; out: - mutex_unlock(&dev_priv->dpll_lock); + mutex_unlock(&dev_priv->dpll.lock); } static struct intel_shared_dpll * @@ -256,10 +278,10 @@ intel_find_shared_dpll(struct intel_atomic_state *state, shared_dpll = intel_atomic_get_shared_dpll_state(&state->base); - WARN_ON(dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); + drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1)); for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) { - pll = &dev_priv->shared_dplls[i]; + pll = &dev_priv->dpll.shared_dplls[i]; /* Only want to check enabled timings first */ if (shared_dpll[i].crtc_mask == 0) { @@ -271,20 +293,21 @@ intel_find_shared_dpll(struct intel_atomic_state *state, if (memcmp(pll_state, &shared_dpll[i].hw_state, sizeof(*pll_state)) == 0) { - DRM_DEBUG_KMS("[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", - crtc->base.base.id, crtc->base.name, - pll->info->name, - shared_dpll[i].crtc_mask, - pll->active_mask); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] sharing existing %s (crtc mask 0x%08x, active %x)\n", + crtc->base.base.id, crtc->base.name, + pll->info->name, + shared_dpll[i].crtc_mask, + pll->active_mask); return pll; } } /* Ok no matching timings, maybe there's a free one? */ if (unused_pll) { - DRM_DEBUG_KMS("[CRTC:%d:%s] allocated %s\n", - crtc->base.base.id, crtc->base.name, - unused_pll->info->name); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n", + crtc->base.base.id, crtc->base.name, + unused_pll->info->name); return unused_pll; } @@ -297,6 +320,7 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *pll_state) { + struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_shared_dpll_state *shared_dpll; const enum intel_dpll_id id = pll->info->id; @@ -305,8 +329,8 @@ intel_reference_shared_dpll(struct intel_atomic_state *state, if (shared_dpll[id].crtc_mask == 0) shared_dpll[id].hw_state = *pll_state; - DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->info->name, - pipe_name(crtc->pipe)); + drm_dbg(&i915->drm, "using %s for pipe %c\n", pll->info->name, + pipe_name(crtc->pipe)); shared_dpll[id].crtc_mask |= 1 << crtc->pipe; } @@ -357,9 +381,9 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state) if (!state->dpll_set) return; - for (i = 0; i < dev_priv->num_shared_dpll; i++) { + for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { struct intel_shared_dpll *pll = - &dev_priv->shared_dplls[i]; + &dev_priv->dpll.shared_dplls[i]; swap(pll->state, shared_dpll[i]); } @@ -378,10 +402,10 @@ static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(PCH_DPLL(id)); + val = intel_de_read(dev_priv, PCH_DPLL(id)); hw_state->dpll = val; - hw_state->fp0 = I915_READ(PCH_FP0(id)); - hw_state->fp1 = I915_READ(PCH_FP1(id)); + hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); + hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); @@ -393,8 +417,8 @@ static void ibx_pch_dpll_prepare(struct drm_i915_private *dev_priv, { const enum intel_dpll_id id = pll->info->id; - I915_WRITE(PCH_FP0(id), pll->state.hw_state.fp0); - I915_WRITE(PCH_FP1(id), pll->state.hw_state.fp1); + intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0); + intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1); } static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) @@ -404,7 +428,7 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); - val = I915_READ(PCH_DREF_CONTROL); + val = intel_de_read(dev_priv, PCH_DREF_CONTROL); enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | DREF_SUPERSPREAD_SOURCE_MASK)); I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); @@ -418,10 +442,10 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, /* PCH refclock must be enabled first */ ibx_assert_pch_refclk_enabled(dev_priv); - I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); /* Wait for the clocks to stabilize. */ - POSTING_READ(PCH_DPLL(id)); + intel_de_posting_read(dev_priv, PCH_DPLL(id)); udelay(150); /* The pixel multiplier can only be updated once the @@ -429,8 +453,8 @@ static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, * * So write it again. */ - I915_WRITE(PCH_DPLL(id), pll->state.hw_state.dpll); - POSTING_READ(PCH_DPLL(id)); + intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll); + intel_de_posting_read(dev_priv, PCH_DPLL(id)); udelay(200); } @@ -439,8 +463,8 @@ static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, { const enum intel_dpll_id id = pll->info->id; - I915_WRITE(PCH_DPLL(id), 0); - POSTING_READ(PCH_DPLL(id)); + intel_de_write(dev_priv, PCH_DPLL(id), 0); + intel_de_posting_read(dev_priv, PCH_DPLL(id)); udelay(200); } @@ -457,11 +481,12 @@ static bool ibx_get_dpll(struct intel_atomic_state *state, if (HAS_PCH_IBX(dev_priv)) { /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ i = (enum intel_dpll_id) crtc->pipe; - pll = &dev_priv->shared_dplls[i]; + pll = &dev_priv->dpll.shared_dplls[i]; - DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", - crtc->base.base.id, crtc->base.name, - pll->info->name); + drm_dbg_kms(&dev_priv->drm, + "[CRTC:%d:%s] using pre-allocated %s\n", + crtc->base.base.id, crtc->base.name, + pll->info->name); } else { pll = intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, @@ -484,12 +509,13 @@ static bool ibx_get_dpll(struct intel_atomic_state *state, static void ibx_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " - "fp0: 0x%x, fp1: 0x%x\n", - hw_state->dpll, - hw_state->dpll_md, - hw_state->fp0, - hw_state->fp1); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + hw_state->dpll, + hw_state->dpll_md, + hw_state->fp0, + hw_state->fp1); } static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { @@ -499,21 +525,34 @@ static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = { .get_hw_state = ibx_pch_dpll_get_hw_state, }; +static const struct dpll_info pch_plls[] = { + { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 }, + { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 }, + { }, +}; + +static const struct intel_dpll_mgr pch_pll_mgr = { + .dpll_info = pch_plls, + .get_dplls = ibx_get_dpll, + .put_dplls = intel_put_dpll, + .dump_hw_state = ibx_dump_hw_state, +}; + static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { const enum intel_dpll_id id = pll->info->id; - I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll); - POSTING_READ(WRPLL_CTL(id)); + intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll); + intel_de_posting_read(dev_priv, WRPLL_CTL(id)); udelay(20); } static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { - I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); - POSTING_READ(SPLL_CTL); + intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll); + intel_de_posting_read(dev_priv, SPLL_CTL); udelay(20); } @@ -523,9 +562,9 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; u32 val; - val = I915_READ(WRPLL_CTL(id)); - I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); - POSTING_READ(WRPLL_CTL(id)); + val = intel_de_read(dev_priv, WRPLL_CTL(id)); + intel_de_write(dev_priv, WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); + intel_de_posting_read(dev_priv, WRPLL_CTL(id)); /* * Try to set up the PCH reference clock once all DPLLs @@ -541,9 +580,9 @@ static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, enum intel_dpll_id id = pll->info->id; u32 val; - val = I915_READ(SPLL_CTL); - I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); - POSTING_READ(SPLL_CTL); + val = intel_de_read(dev_priv, SPLL_CTL); + intel_de_write(dev_priv, SPLL_CTL, val & ~SPLL_PLL_ENABLE); + intel_de_posting_read(dev_priv, SPLL_CTL); /* * Try to set up the PCH reference clock once all DPLLs @@ -566,7 +605,7 @@ static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(WRPLL_CTL(id)); + val = intel_de_read(dev_priv, WRPLL_CTL(id)); hw_state->wrpll = val; intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); @@ -586,7 +625,7 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(SPLL_CTL); + val = intel_de_read(dev_priv, SPLL_CTL); hw_state->spll = val; intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); @@ -811,8 +850,8 @@ hsw_ddi_calculate_wrpll(int clock /* in Hz */, } static struct intel_shared_dpll * -hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state, - struct intel_crtc *crtc) +hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); @@ -839,8 +878,47 @@ hsw_ddi_hdmi_get_dpll(struct intel_atomic_state *state, return pll; } +static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, + const struct intel_shared_dpll *pll) +{ + int refclk; + int n, p, r; + u32 wrpll = pll->state.hw_state.wrpll; + + switch (wrpll & WRPLL_REF_MASK) { + case WRPLL_REF_SPECIAL_HSW: + /* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */ + if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) { + refclk = dev_priv->dpll.ref_clks.nssc; + break; + } + /* fall through */ + case WRPLL_REF_PCH_SSC: + /* + * We could calculate spread here, but our checking + * code only cares about 5% accuracy, and spread is a max of + * 0.5% downspread. + */ + refclk = dev_priv->dpll.ref_clks.ssc; + break; + case WRPLL_REF_LCPLL: + refclk = 2700000; + break; + default: + MISSING_CASE(wrpll); + return 0; + } + + r = wrpll & WRPLL_DIVIDER_REF_MASK; + p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; + n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; + + /* Convert to KHz, p & r have a fixed point portion */ + return (refclk * n / 10) / (p * r) * 2; +} + static struct intel_shared_dpll * -hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state) +hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); struct intel_shared_dpll *pll; @@ -858,7 +936,8 @@ hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state) pll_id = DPLL_ID_LCPLL_2700; break; default: - DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); + drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n", + clock); return NULL; } @@ -870,6 +949,69 @@ hsw_ddi_dp_get_dpll(struct intel_crtc_state *crtc_state) return pll; } +static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + int link_clock = 0; + + switch (pll->info->id) { + case DPLL_ID_LCPLL_810: + link_clock = 81000; + break; + case DPLL_ID_LCPLL_1350: + link_clock = 135000; + break; + case DPLL_ID_LCPLL_2700: + link_clock = 270000; + break; + default: + drm_WARN(&i915->drm, 1, "bad port clock sel\n"); + break; + } + + return link_clock * 2; +} + +static struct intel_shared_dpll * +hsw_ddi_spll_get_dpll(struct intel_atomic_state *state, + struct intel_crtc *crtc) +{ + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + if (WARN_ON(crtc_state->port_clock / 2 != 135000)) + return NULL; + + crtc_state->dpll_hw_state.spll = SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | + SPLL_REF_MUXED_SSC; + + return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, + BIT(DPLL_ID_SPLL)); +} + +static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + int link_clock = 0; + + switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) { + case SPLL_FREQ_810MHz: + link_clock = 81000; + break; + case SPLL_FREQ_1350MHz: + link_clock = 135000; + break; + case SPLL_FREQ_2700MHz: + link_clock = 270000; + break; + default: + drm_WARN(&i915->drm, 1, "bad spll freq\n"); + break; + } + + return link_clock * 2; +} + static bool hsw_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) @@ -881,23 +1023,14 @@ static bool hsw_get_dpll(struct intel_atomic_state *state, memset(&crtc_state->dpll_hw_state, 0, sizeof(crtc_state->dpll_hw_state)); - if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { - pll = hsw_ddi_hdmi_get_dpll(state, crtc); - } else if (intel_crtc_has_dp_encoder(crtc_state)) { - pll = hsw_ddi_dp_get_dpll(crtc_state); - } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { - if (WARN_ON(crtc_state->port_clock / 2 != 135000)) - return false; - - crtc_state->dpll_hw_state.spll = - SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC; - - pll = intel_find_shared_dpll(state, crtc, - &crtc_state->dpll_hw_state, - BIT(DPLL_ID_SPLL)); - } else { + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + pll = hsw_ddi_wrpll_get_dpll(state, crtc); + else if (intel_crtc_has_dp_encoder(crtc_state)) + pll = hsw_ddi_lcpll_get_dpll(crtc_state); + else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) + pll = hsw_ddi_spll_get_dpll(state, crtc); + else return false; - } if (!pll) return false; @@ -910,23 +1043,35 @@ static bool hsw_get_dpll(struct intel_atomic_state *state, return true; } +static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915) +{ + i915->dpll.ref_clks.ssc = 135000; + /* Non-SSC is only used on non-ULT HSW. */ + if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) + i915->dpll.ref_clks.nssc = 24000; + else + i915->dpll.ref_clks.nssc = 135000; +} + static void hsw_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", - hw_state->wrpll, hw_state->spll); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", + hw_state->wrpll, hw_state->spll); } static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = { .enable = hsw_ddi_wrpll_enable, .disable = hsw_ddi_wrpll_disable, .get_hw_state = hsw_ddi_wrpll_get_hw_state, + .get_freq = hsw_ddi_wrpll_get_freq, }; static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = { .enable = hsw_ddi_spll_enable, .disable = hsw_ddi_spll_disable, .get_hw_state = hsw_ddi_spll_get_hw_state, + .get_freq = hsw_ddi_spll_get_freq, }; static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv, @@ -950,6 +1095,25 @@ static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = { .enable = hsw_ddi_lcpll_enable, .disable = hsw_ddi_lcpll_disable, .get_hw_state = hsw_ddi_lcpll_get_hw_state, + .get_freq = hsw_ddi_lcpll_get_freq, +}; + +static const struct dpll_info hsw_plls[] = { + { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 }, + { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 }, + { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 }, + { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON }, + { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON }, + { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON }, + { }, +}; + +static const struct intel_dpll_mgr hsw_pll_mgr = { + .dpll_info = hsw_plls, + .get_dplls = hsw_get_dpll, + .put_dplls = intel_put_dpll, + .update_ref_clks = hsw_update_dpll_ref_clks, + .dump_hw_state = hsw_dump_hw_state, }; struct skl_dpll_regs { @@ -989,15 +1153,15 @@ static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; u32 val; - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); val &= ~(DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id)); val |= pll->state.hw_state.ctrl1 << (id * 6); - I915_WRITE(DPLL_CTRL1, val); - POSTING_READ(DPLL_CTRL1); + intel_de_write(dev_priv, DPLL_CTRL1, val); + intel_de_posting_read(dev_priv, DPLL_CTRL1); } static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, @@ -1008,17 +1172,17 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, skl_ddi_pll_write_ctrl1(dev_priv, pll); - I915_WRITE(regs[id].cfgcr1, pll->state.hw_state.cfgcr1); - I915_WRITE(regs[id].cfgcr2, pll->state.hw_state.cfgcr2); - POSTING_READ(regs[id].cfgcr1); - POSTING_READ(regs[id].cfgcr2); + intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1); + intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2); + intel_de_posting_read(dev_priv, regs[id].cfgcr1); + intel_de_posting_read(dev_priv, regs[id].cfgcr2); /* the enable bit is always bit 31 */ - I915_WRITE(regs[id].ctl, - I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE); + intel_de_write(dev_priv, regs[id].ctl, + intel_de_read(dev_priv, regs[id].ctl) | LCPLL_PLL_ENABLE); if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5)) - DRM_ERROR("DPLL %d not locked\n", id); + drm_err(&dev_priv->drm, "DPLL %d not locked\n", id); } static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv, @@ -1034,9 +1198,9 @@ static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, const enum intel_dpll_id id = pll->info->id; /* the enable bit is always bit 31 */ - I915_WRITE(regs[id].ctl, - I915_READ(regs[id].ctl) & ~LCPLL_PLL_ENABLE); - POSTING_READ(regs[id].ctl); + intel_de_write(dev_priv, regs[id].ctl, + intel_de_read(dev_priv, regs[id].ctl) & ~LCPLL_PLL_ENABLE); + intel_de_posting_read(dev_priv, regs[id].ctl); } static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv, @@ -1061,17 +1225,17 @@ static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = false; - val = I915_READ(regs[id].ctl); + val = intel_de_read(dev_priv, regs[id].ctl); if (!(val & LCPLL_PLL_ENABLE)) goto out; - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; /* avoid reading back stale values if HDMI mode is not enabled */ if (val & DPLL_CTRL1_HDMI_MODE(id)) { - hw_state->cfgcr1 = I915_READ(regs[id].cfgcr1); - hw_state->cfgcr2 = I915_READ(regs[id].cfgcr2); + hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); + hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2); } ret = true; @@ -1099,11 +1263,11 @@ static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv, ret = false; /* DPLL0 is always enabled since it drives CDCLK */ - val = I915_READ(regs[id].ctl); - if (WARN_ON(!(val & LCPLL_PLL_ENABLE))) + val = intel_de_read(dev_priv, regs[id].ctl); + if (drm_WARN_ON(&dev_priv->drm, !(val & LCPLL_PLL_ENABLE))) goto out; - val = I915_READ(DPLL_CTRL1); + val = intel_de_read(dev_priv, DPLL_CTRL1); hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; ret = true; @@ -1222,6 +1386,7 @@ struct skl_wrpll_params { static void skl_wrpll_params_populate(struct skl_wrpll_params *params, u64 afe_clock, + int ref_clock, u64 central_freq, u32 p0, u32 p1, u32 p2) { @@ -1281,14 +1446,15 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params, * Intermediate values are in Hz. * Divide by MHz to match bsepc */ - params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); + params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1)); params->dco_fraction = - div_u64((div_u64(dco_freq, 24) - + div_u64((div_u64(dco_freq, ref_clock / KHz(1)) - params->dco_integer * MHz(1)) * 0x8000, MHz(1)); } static bool skl_ddi_calculate_wrpll(int clock /* in Hz */, + int ref_clock, struct skl_wrpll_params *wrpll_params) { u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ @@ -1354,14 +1520,15 @@ skip_remaining_dividers: */ p0 = p1 = p2 = 0; skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); - skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, - p0, p1, p2); + skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock, + ctx.central_freq, p0, p1, p2); return true; } static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); u32 ctrl1, cfgcr1, cfgcr2; struct skl_wrpll_params wrpll_params = { 0, }; @@ -1374,6 +1541,7 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); if (!skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000, + i915->dpll.ref_clks.nssc, &wrpll_params)) return false; @@ -1396,6 +1564,64 @@ static bool skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) return true; } +static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; + int ref_clock = i915->dpll.ref_clks.nssc; + u32 p0, p1, p2, dco_freq; + + p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK; + p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK; + + if (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_MODE(1)) + p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; + else + p1 = 1; + + + switch (p0) { + case DPLL_CFGCR2_PDIV_1: + p0 = 1; + break; + case DPLL_CFGCR2_PDIV_2: + p0 = 2; + break; + case DPLL_CFGCR2_PDIV_3: + p0 = 3; + break; + case DPLL_CFGCR2_PDIV_7: + p0 = 7; + break; + } + + switch (p2) { + case DPLL_CFGCR2_KDIV_5: + p2 = 5; + break; + case DPLL_CFGCR2_KDIV_2: + p2 = 2; + break; + case DPLL_CFGCR2_KDIV_3: + p2 = 3; + break; + case DPLL_CFGCR2_KDIV_1: + p2 = 1; + break; + } + + dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) * + ref_clock; + + dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * + ref_clock / 0x8000; + + if (WARN_ON(p0 == 0 || p1 == 0 || p2 == 0)) + return 0; + + return dco_freq / (p0 * p1 * p2 * 5); +} + static bool skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) { @@ -1436,25 +1662,62 @@ skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) return true; } +static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + int link_clock = 0; + + switch ((pll->state.hw_state.ctrl1 & + DPLL_CTRL1_LINK_RATE_MASK(0)) >> + DPLL_CTRL1_LINK_RATE_SHIFT(0)) { + case DPLL_CTRL1_LINK_RATE_810: + link_clock = 81000; + break; + case DPLL_CTRL1_LINK_RATE_1080: + link_clock = 108000; + break; + case DPLL_CTRL1_LINK_RATE_1350: + link_clock = 135000; + break; + case DPLL_CTRL1_LINK_RATE_1620: + link_clock = 162000; + break; + case DPLL_CTRL1_LINK_RATE_2160: + link_clock = 216000; + break; + case DPLL_CTRL1_LINK_RATE_2700: + link_clock = 270000; + break; + default: + drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); + break; + } + + return link_clock * 2; +} + static bool skl_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_shared_dpll *pll; bool bret; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { bret = skl_ddi_hdmi_pll_dividers(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n"); + drm_dbg_kms(&i915->drm, + "Could not get HDMI pll dividers.\n"); return false; } } else if (intel_crtc_has_dp_encoder(crtc_state)) { bret = skl_ddi_dp_set_dpll_hw_state(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not set DP dpll HW state.\n"); + drm_dbg_kms(&i915->drm, + "Could not set DP dpll HW state.\n"); return false; } } else { @@ -1482,10 +1745,29 @@ static bool skl_get_dpll(struct intel_atomic_state *state, return true; } +static int skl_ddi_pll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + /* + * ctrl1 register is already shifted for each pll, just use 0 to get + * the internal shift for each field + */ + if (pll->state.hw_state.ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) + return skl_ddi_wrpll_get_freq(i915, pll); + else + return skl_ddi_lcpll_get_freq(i915, pll); +} + +static void skl_update_dpll_ref_clks(struct drm_i915_private *i915) +{ + /* No SSC ref */ + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; +} + static void skl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: " + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", hw_state->ctrl1, hw_state->cfgcr1, @@ -1496,12 +1778,30 @@ static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = { .enable = skl_ddi_pll_enable, .disable = skl_ddi_pll_disable, .get_hw_state = skl_ddi_pll_get_hw_state, + .get_freq = skl_ddi_pll_get_freq, }; static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = { .enable = skl_ddi_dpll0_enable, .disable = skl_ddi_dpll0_disable, .get_hw_state = skl_ddi_dpll0_get_hw_state, + .get_freq = skl_ddi_pll_get_freq, +}; + +static const struct dpll_info skl_plls[] = { + { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON }, + { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 }, + { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 }, + { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 }, + { }, +}; + +static const struct intel_dpll_mgr skl_pll_mgr = { + .dpll_info = skl_plls, + .get_dplls = skl_get_dpll, + .put_dplls = intel_put_dpll, + .update_ref_clks = skl_update_dpll_ref_clks, + .dump_hw_state = skl_dump_hw_state, }; static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, @@ -1515,113 +1815,114 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); /* Non-SSC reference */ - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp |= PORT_PLL_REF_SEL; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); if (IS_GEMINILAKE(dev_priv)) { - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp |= PORT_PLL_POWER_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); - if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & + if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_POWER_STATE), 200)) - DRM_ERROR("Power state not set for PLL:%d\n", port); + drm_err(&dev_priv->drm, + "Power state not set for PLL:%d\n", port); } /* Disable 10 bit clock */ - temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); temp &= ~PORT_PLL_10BIT_CLK_ENABLE; - I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); /* Write P1 & P2 */ - temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)); temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); temp |= pll->state.hw_state.ebb0; - I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch), temp); /* Write M2 integer */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 0)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); temp &= ~PORT_PLL_M2_MASK; temp |= pll->state.hw_state.pll0; - I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 0), temp); /* Write N */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 1)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); temp &= ~PORT_PLL_N_MASK; temp |= pll->state.hw_state.pll1; - I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 1), temp); /* Write M2 fraction */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 2)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); temp &= ~PORT_PLL_M2_FRAC_MASK; temp |= pll->state.hw_state.pll2; - I915_WRITE(BXT_PORT_PLL(phy, ch, 2), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 2), temp); /* Write M2 fraction enable */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 3)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); temp &= ~PORT_PLL_M2_FRAC_ENABLE; temp |= pll->state.hw_state.pll3; - I915_WRITE(BXT_PORT_PLL(phy, ch, 3), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 3), temp); /* Write coeff */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 6)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); temp &= ~PORT_PLL_PROP_COEFF_MASK; temp &= ~PORT_PLL_INT_COEFF_MASK; temp &= ~PORT_PLL_GAIN_CTL_MASK; temp |= pll->state.hw_state.pll6; - I915_WRITE(BXT_PORT_PLL(phy, ch, 6), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6), temp); /* Write calibration val */ - temp = I915_READ(BXT_PORT_PLL(phy, ch, 8)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); temp &= ~PORT_PLL_TARGET_CNT_MASK; temp |= pll->state.hw_state.pll8; - I915_WRITE(BXT_PORT_PLL(phy, ch, 8), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 8), temp); - temp = I915_READ(BXT_PORT_PLL(phy, ch, 9)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; temp |= pll->state.hw_state.pll9; - I915_WRITE(BXT_PORT_PLL(phy, ch, 9), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 9), temp); - temp = I915_READ(BXT_PORT_PLL(phy, ch, 10)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; temp &= ~PORT_PLL_DCO_AMP_MASK; temp |= pll->state.hw_state.pll10; - I915_WRITE(BXT_PORT_PLL(phy, ch, 10), temp); + intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10), temp); /* Recalibrate with new settings */ - temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); temp |= PORT_PLL_RECALIBRATE; - I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); temp &= ~PORT_PLL_10BIT_CLK_ENABLE; temp |= pll->state.hw_state.ebb4; - I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp); /* Enable PLL */ - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp |= PORT_PLL_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); - POSTING_READ(BXT_PORT_PLL_ENABLE(port)); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); + intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); - if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), + if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK), 200)) - DRM_ERROR("PLL %d not locked\n", port); + drm_err(&dev_priv->drm, "PLL %d not locked\n", port); if (IS_GEMINILAKE(dev_priv)) { - temp = I915_READ(BXT_PORT_TX_DW5_LN0(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch)); temp |= DCC_DELAY_RANGE_2; - I915_WRITE(BXT_PORT_TX_DW5_GRP(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch), temp); } /* * While we write to the group register to program all lanes at once we * can read only lane registers and we pick lanes 0/1 for that. */ - temp = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); + temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch)); temp &= ~LANE_STAGGER_MASK; temp &= ~LANESTAGGER_STRAP_OVRD; temp |= pll->state.hw_state.pcsdw12; - I915_WRITE(BXT_PORT_PCS_DW12_GRP(phy, ch), temp); + intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch), temp); } static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, @@ -1630,19 +1931,20 @@ static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */ u32 temp; - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp &= ~PORT_PLL_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); - POSTING_READ(BXT_PORT_PLL_ENABLE(port)); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); + intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); if (IS_GEMINILAKE(dev_priv)) { - temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); + temp = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); temp &= ~PORT_PLL_POWER_ENABLE; - I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); + intel_de_write(dev_priv, BXT_PORT_PLL_ENABLE(port), temp); - if (wait_for_us(!(I915_READ(BXT_PORT_PLL_ENABLE(port)) & - PORT_PLL_POWER_STATE), 200)) - DRM_ERROR("Power state not reset for PLL:%d\n", port); + if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & + PORT_PLL_POWER_STATE), 200)) + drm_err(&dev_priv->drm, + "Power state not reset for PLL:%d\n", port); } } @@ -1666,40 +1968,40 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = false; - val = I915_READ(BXT_PORT_PLL_ENABLE(port)); + val = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)); if (!(val & PORT_PLL_ENABLE)) goto out; - hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); + hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch)); hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; - hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); + hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch)); hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; - hw_state->pll0 = I915_READ(BXT_PORT_PLL(phy, ch, 0)); + hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0)); hw_state->pll0 &= PORT_PLL_M2_MASK; - hw_state->pll1 = I915_READ(BXT_PORT_PLL(phy, ch, 1)); + hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1)); hw_state->pll1 &= PORT_PLL_N_MASK; - hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2)); + hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2)); hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; - hw_state->pll3 = I915_READ(BXT_PORT_PLL(phy, ch, 3)); + hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3)); hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; - hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6)); + hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6)); hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | PORT_PLL_INT_COEFF_MASK | PORT_PLL_GAIN_CTL_MASK; - hw_state->pll8 = I915_READ(BXT_PORT_PLL(phy, ch, 8)); + hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8)); hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; - hw_state->pll9 = I915_READ(BXT_PORT_PLL(phy, ch, 9)); + hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; - hw_state->pll10 = I915_READ(BXT_PORT_PLL(phy, ch, 10)); + hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10)); hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | PORT_PLL_DCO_AMP_MASK; @@ -1708,11 +2010,14 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, * can read only lane registers. We configure all lanes the same way, so * here just read out lanes 0/1 and output a note if lanes 2/3 differ. */ - hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(phy, ch)); - if (I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) - DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", - hw_state->pcsdw12, - I915_READ(BXT_PORT_PCS_DW12_LN23(phy, ch))); + hw_state->pcsdw12 = intel_de_read(dev_priv, + BXT_PORT_PCS_DW12_LN01(phy, ch)); + if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12) + drm_dbg(&dev_priv->drm, + "lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", + hw_state->pcsdw12, + intel_de_read(dev_priv, + BXT_PORT_PCS_DW12_LN23(phy, ch))); hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; ret = true; @@ -1751,6 +2056,7 @@ static bool bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, struct bxt_clk_div *clk_div) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct dpll best_clock; @@ -1760,9 +2066,9 @@ bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state, * i9xx_crtc_compute_clock */ if (!bxt_find_best_dpll(crtc_state, &best_clock)) { - DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", - crtc_state->port_clock, - pipe_name(crtc->pipe)); + drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n", + crtc_state->port_clock, + pipe_name(crtc->pipe)); return false; } @@ -1799,6 +2105,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state, static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, const struct bxt_clk_div *clk_div) { + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; int clock = crtc_state->port_clock; int vco = clk_div->vco; @@ -1824,7 +2131,7 @@ static bool bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state, gain_ctl = 1; targ_cnt = 9; } else { - DRM_ERROR("Invalid VCO\n"); + drm_err(&i915->drm, "Invalid VCO\n"); return false; } @@ -1885,6 +2192,23 @@ bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state) return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div); } +static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; + struct dpll clock; + + clock.m1 = 2; + clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22; + if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE) + clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; + clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; + clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; + clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; + + return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock); +} + static bool bxt_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) @@ -1907,8 +2231,8 @@ static bool bxt_get_dpll(struct intel_atomic_state *state, id = (enum intel_dpll_id) encoder->port; pll = intel_get_shared_dpll_by_id(dev_priv, id); - DRM_DEBUG_KMS("[CRTC:%d:%s] using pre-allocated %s\n", - crtc->base.base.id, crtc->base.name, pll->info->name); + drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n", + crtc->base.base.id, crtc->base.name, pll->info->name); intel_reference_shared_dpll(state, crtc, pll, &crtc_state->dpll_hw_state); @@ -1918,89 +2242,37 @@ static bool bxt_get_dpll(struct intel_atomic_state *state, return true; } +static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915) +{ + i915->dpll.ref_clks.ssc = 100000; + i915->dpll.ref_clks.nssc = 100000; + /* DSI non-SSC ref 19.2MHz */ +} + static void bxt_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," - "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " - "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", - hw_state->ebb0, - hw_state->ebb4, - hw_state->pll0, - hw_state->pll1, - hw_state->pll2, - hw_state->pll3, - hw_state->pll6, - hw_state->pll8, - hw_state->pll9, - hw_state->pll10, - hw_state->pcsdw12); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," + "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " + "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", + hw_state->ebb0, + hw_state->ebb4, + hw_state->pll0, + hw_state->pll1, + hw_state->pll2, + hw_state->pll3, + hw_state->pll6, + hw_state->pll8, + hw_state->pll9, + hw_state->pll10, + hw_state->pcsdw12); } static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = { .enable = bxt_ddi_pll_enable, .disable = bxt_ddi_pll_disable, .get_hw_state = bxt_ddi_pll_get_hw_state, -}; - -struct intel_dpll_mgr { - const struct dpll_info *dpll_info; - - bool (*get_dplls)(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder); - void (*put_dplls)(struct intel_atomic_state *state, - struct intel_crtc *crtc); - void (*update_active_dpll)(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_encoder *encoder); - void (*dump_hw_state)(struct drm_i915_private *dev_priv, - const struct intel_dpll_hw_state *hw_state); -}; - -static const struct dpll_info pch_plls[] = { - { "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 }, - { "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 }, - { }, -}; - -static const struct intel_dpll_mgr pch_pll_mgr = { - .dpll_info = pch_plls, - .get_dplls = ibx_get_dpll, - .put_dplls = intel_put_dpll, - .dump_hw_state = ibx_dump_hw_state, -}; - -static const struct dpll_info hsw_plls[] = { - { "WRPLL 1", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1, 0 }, - { "WRPLL 2", &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2, 0 }, - { "SPLL", &hsw_ddi_spll_funcs, DPLL_ID_SPLL, 0 }, - { "LCPLL 810", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810, INTEL_DPLL_ALWAYS_ON }, - { "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON }, - { "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON }, - { }, -}; - -static const struct intel_dpll_mgr hsw_pll_mgr = { - .dpll_info = hsw_plls, - .get_dplls = hsw_get_dpll, - .put_dplls = intel_put_dpll, - .dump_hw_state = hsw_dump_hw_state, -}; - -static const struct dpll_info skl_plls[] = { - { "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON }, - { "DPLL 1", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 }, - { "DPLL 2", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 }, - { "DPLL 3", &skl_ddi_pll_funcs, DPLL_ID_SKL_DPLL3, 0 }, - { }, -}; - -static const struct intel_dpll_mgr skl_pll_mgr = { - .dpll_info = skl_plls, - .get_dplls = skl_get_dpll, - .put_dplls = intel_put_dpll, - .dump_hw_state = skl_dump_hw_state, + .get_freq = bxt_ddi_pll_get_freq, }; static const struct dpll_info bxt_plls[] = { @@ -2014,6 +2286,7 @@ static const struct intel_dpll_mgr bxt_pll_mgr = { .dpll_info = bxt_plls, .get_dplls = bxt_get_dpll, .put_dplls = intel_put_dpll, + .update_ref_clks = bxt_update_dpll_ref_clks, .dump_hw_state = bxt_dump_hw_state, }; @@ -2024,32 +2297,32 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, u32 val; /* 1. Enable DPLL power in DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val |= PLL_POWER_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 2. Wait for DPLL power state enabled in DPLL_ENABLE. */ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_POWER_STATE, 5)) - DRM_ERROR("PLL %d Power not enabled\n", id); + drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", id); /* * 3. Configure DPLL_CFGCR0 to set SSC enable/disable, * select DP mode, and set DP link rate. */ val = pll->state.hw_state.cfgcr0; - I915_WRITE(CNL_DPLL_CFGCR0(id), val); + intel_de_write(dev_priv, CNL_DPLL_CFGCR0(id), val); /* 4. Reab back to ensure writes completed */ - POSTING_READ(CNL_DPLL_CFGCR0(id)); + intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR0(id)); /* 3. Configure DPLL_CFGCR0 */ /* Avoid touch CFGCR1 if HDMI mode is not enabled */ if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { val = pll->state.hw_state.cfgcr1; - I915_WRITE(CNL_DPLL_CFGCR1(id), val); + intel_de_write(dev_priv, CNL_DPLL_CFGCR1(id), val); /* 4. Reab back to ensure writes completed */ - POSTING_READ(CNL_DPLL_CFGCR1(id)); + intel_de_posting_read(dev_priv, CNL_DPLL_CFGCR1(id)); } /* @@ -2062,13 +2335,13 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, */ /* 6. Enable DPLL in DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val |= PLL_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 7. Wait for PLL lock status in DPLL_ENABLE. */ if (intel_de_wait_for_set(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) - DRM_ERROR("PLL %d not locked\n", id); + drm_err(&dev_priv->drm, "PLL %d not locked\n", id); /* * 8. If the frequency will result in a change to the voltage @@ -2106,13 +2379,13 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, */ /* 3. Disable DPLL through DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val &= ~PLL_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 4. Wait for PLL not locked status in DPLL_ENABLE. */ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_LOCK, 5)) - DRM_ERROR("PLL %d locked\n", id); + drm_err(&dev_priv->drm, "PLL %d locked\n", id); /* * 5. If the frequency will result in a change to the voltage @@ -2124,14 +2397,14 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv, */ /* 6. Disable DPLL power in DPLL_ENABLE. */ - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); val &= ~PLL_POWER_ENABLE; - I915_WRITE(CNL_DPLL_ENABLE(id), val); + intel_de_write(dev_priv, CNL_DPLL_ENABLE(id), val); /* 7. Wait for DPLL power state disabled in DPLL_ENABLE. */ if (intel_de_wait_for_clear(dev_priv, CNL_DPLL_ENABLE(id), PLL_POWER_STATE, 5)) - DRM_ERROR("PLL %d Power not disabled\n", id); + drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", id); } static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, @@ -2150,16 +2423,17 @@ static bool cnl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, ret = false; - val = I915_READ(CNL_DPLL_ENABLE(id)); + val = intel_de_read(dev_priv, CNL_DPLL_ENABLE(id)); if (!(val & PLL_ENABLE)) goto out; - val = I915_READ(CNL_DPLL_CFGCR0(id)); + val = intel_de_read(dev_priv, CNL_DPLL_CFGCR0(id)); hw_state->cfgcr0 = val; /* avoid reading back stale values if HDMI mode is not enabled */ if (val & DPLL_CFGCR0_HDMI_MODE) { - hw_state->cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + CNL_DPLL_CFGCR1(id)); } ret = true; @@ -2256,27 +2530,12 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params, params->dco_fraction = dco & 0x7fff; } -int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv) -{ - int ref_clock = dev_priv->cdclk.hw.ref; - - /* - * For ICL+, the spec states: if reference frequency is 38.4, - * use 19.2 because the DPLL automatically divides that by 2. - */ - if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400) - ref_clock = 19200; - - return ref_clock; -} - static bool -cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state, - struct skl_wrpll_params *wrpll_params) +__cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state, + struct skl_wrpll_params *wrpll_params, + int ref_clock) { - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); u32 afe_clock = crtc_state->port_clock * 5; - u32 ref_clock; u32 dco_min = 7998000; u32 dco_max = 10000000; u32 dco_mid = (dco_min + dco_max) / 2; @@ -2308,15 +2567,22 @@ cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state, return false; cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv); - - ref_clock = cnl_hdmi_pll_ref_clock(dev_priv); - cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv, kdiv); return true; } +static bool +cnl_ddi_calculate_wrpll(struct intel_crtc_state *crtc_state, + struct skl_wrpll_params *wrpll_params) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params, + i915->dpll.ref_clks.nssc); +} + static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) { u32 cfgcr0, cfgcr1; @@ -2344,6 +2610,68 @@ static bool cnl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state) return true; } +static int __cnl_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, + const struct intel_shared_dpll *pll, + int ref_clock) +{ + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; + u32 p0, p1, p2, dco_freq; + + p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK; + p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK; + + if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) + p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> + DPLL_CFGCR1_QDIV_RATIO_SHIFT; + else + p1 = 1; + + + switch (p0) { + case DPLL_CFGCR1_PDIV_2: + p0 = 2; + break; + case DPLL_CFGCR1_PDIV_3: + p0 = 3; + break; + case DPLL_CFGCR1_PDIV_5: + p0 = 5; + break; + case DPLL_CFGCR1_PDIV_7: + p0 = 7; + break; + } + + switch (p2) { + case DPLL_CFGCR1_KDIV_1: + p2 = 1; + break; + case DPLL_CFGCR1_KDIV_2: + p2 = 2; + break; + case DPLL_CFGCR1_KDIV_3: + p2 = 3; + break; + } + + dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * + ref_clock; + + dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> + DPLL_CFGCR0_DCO_FRACTION_SHIFT) * ref_clock) / 0x8000; + + if (drm_WARN_ON(&dev_priv->drm, p0 == 0 || p1 == 0 || p2 == 0)) + return 0; + + return dco_freq / (p0 * p1 * p2 * 5); +} + +static int cnl_ddi_wrpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + return __cnl_ddi_wrpll_get_freq(i915, pll, i915->dpll.ref_clks.nssc); +} + static bool cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) { @@ -2389,30 +2717,72 @@ cnl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state) return true; } +static int cnl_ddi_lcpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + int link_clock = 0; + + switch (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK) { + case DPLL_CFGCR0_LINK_RATE_810: + link_clock = 81000; + break; + case DPLL_CFGCR0_LINK_RATE_1080: + link_clock = 108000; + break; + case DPLL_CFGCR0_LINK_RATE_1350: + link_clock = 135000; + break; + case DPLL_CFGCR0_LINK_RATE_1620: + link_clock = 162000; + break; + case DPLL_CFGCR0_LINK_RATE_2160: + link_clock = 216000; + break; + case DPLL_CFGCR0_LINK_RATE_2700: + link_clock = 270000; + break; + case DPLL_CFGCR0_LINK_RATE_3240: + link_clock = 324000; + break; + case DPLL_CFGCR0_LINK_RATE_4050: + link_clock = 405000; + break; + default: + drm_WARN(&i915->drm, 1, "Unsupported link rate\n"); + break; + } + + return link_clock * 2; +} + static bool cnl_get_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); struct intel_shared_dpll *pll; bool bret; if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { bret = cnl_ddi_hdmi_pll_dividers(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not get HDMI pll dividers.\n"); + drm_dbg_kms(&i915->drm, + "Could not get HDMI pll dividers.\n"); return false; } } else if (intel_crtc_has_dp_encoder(crtc_state)) { bret = cnl_ddi_dp_set_dpll_hw_state(crtc_state); if (!bret) { - DRM_DEBUG_KMS("Could not set DP dpll HW state.\n"); + drm_dbg_kms(&i915->drm, + "Could not set DP dpll HW state.\n"); return false; } } else { - DRM_DEBUG_KMS("Skip DPLL setup for output_types 0x%x\n", - crtc_state->output_types); + drm_dbg_kms(&i915->drm, + "Skip DPLL setup for output_types 0x%x\n", + crtc_state->output_types); return false; } @@ -2422,7 +2792,7 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, BIT(DPLL_ID_SKL_DPLL1) | BIT(DPLL_ID_SKL_DPLL0)); if (!pll) { - DRM_DEBUG_KMS("No PLL selected\n"); + drm_dbg_kms(&i915->drm, "No PLL selected\n"); return false; } @@ -2434,19 +2804,35 @@ static bool cnl_get_dpll(struct intel_atomic_state *state, return true; } +static int cnl_ddi_pll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) + return cnl_ddi_wrpll_get_freq(i915, pll); + else + return cnl_ddi_lcpll_get_freq(i915, pll); +} + +static void cnl_update_dpll_ref_clks(struct drm_i915_private *i915) +{ + /* No SSC reference */ + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; +} + static void cnl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: " - "cfgcr0: 0x%x, cfgcr1: 0x%x\n", - hw_state->cfgcr0, - hw_state->cfgcr1); + drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: " + "cfgcr0: 0x%x, cfgcr1: 0x%x\n", + hw_state->cfgcr0, + hw_state->cfgcr1); } static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = { .enable = cnl_ddi_pll_enable, .disable = cnl_ddi_pll_disable, .get_hw_state = cnl_ddi_pll_get_hw_state, + .get_freq = cnl_ddi_pll_get_freq, }; static const struct dpll_info cnl_plls[] = { @@ -2460,6 +2846,7 @@ static const struct intel_dpll_mgr cnl_pll_mgr = { .dpll_info = cnl_plls, .get_dplls = cnl_get_dpll, .put_dplls = intel_put_dpll, + .update_ref_clks = cnl_update_dpll_ref_clks, .dump_hw_state = cnl_dump_hw_state, }; @@ -2555,7 +2942,7 @@ static bool icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state, { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); const struct icl_combo_pll_params *params = - dev_priv->cdclk.hw.ref == 24000 ? + dev_priv->dpll.ref_clks.nssc == 24000 ? icl_dp_combo_pll_24MHz_values : icl_dp_combo_pll_19_2MHz_values; int clock = crtc_state->port_clock; @@ -2578,9 +2965,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); if (INTEL_GEN(dev_priv) >= 12) { - switch (dev_priv->cdclk.hw.ref) { + switch (dev_priv->dpll.ref_clks.nssc) { default: - MISSING_CASE(dev_priv->cdclk.hw.ref); + MISSING_CASE(dev_priv->dpll.ref_clks.nssc); /* fall-through */ case 19200: case 38400: @@ -2591,9 +2978,9 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, break; } } else { - switch (dev_priv->cdclk.hw.ref) { + switch (dev_priv->dpll.ref_clks.nssc) { default: - MISSING_CASE(dev_priv->cdclk.hw.ref); + MISSING_CASE(dev_priv->dpll.ref_clks.nssc); /* fall-through */ case 19200: case 38400: @@ -2608,6 +2995,49 @@ static bool icl_calc_tbt_pll(struct intel_crtc_state *crtc_state, return true; } +static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + /* + * The PLL outputs multiple frequencies at the same time, selection is + * made at DDI clock mux level. + */ + drm_WARN_ON(&i915->drm, 1); + + return 0; +} + +static int icl_wrpll_ref_clock(struct drm_i915_private *i915) +{ + int ref_clock = i915->dpll.ref_clks.nssc; + + /* + * For ICL+, the spec states: if reference frequency is 38.4, + * use 19.2 because the DPLL automatically divides that by 2. + */ + if (ref_clock == 38400) + ref_clock = 19200; + + return ref_clock; +} + +static bool +icl_calc_wrpll(struct intel_crtc_state *crtc_state, + struct skl_wrpll_params *wrpll_params) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + return __cnl_ddi_calculate_wrpll(crtc_state, wrpll_params, + icl_wrpll_ref_clock(i915)); +} + +static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + return __cnl_ddi_wrpll_get_freq(i915, pll, + icl_wrpll_ref_clock(i915)); +} + static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder, struct intel_dpll_hw_state *pll_state) @@ -2622,7 +3052,7 @@ static bool icl_calc_dpll_state(struct intel_crtc_state *crtc_state, ret = icl_calc_tbt_pll(crtc_state, &pll_params); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) - ret = cnl_ddi_calculate_wrpll(crtc_state, &pll_params); + ret = icl_calc_wrpll(crtc_state, &pll_params); else ret = icl_calc_dp_combo_pll(crtc_state, &pll_params); @@ -2745,7 +3175,7 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, struct intel_dpll_hw_state *pll_state) { struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); - int refclk_khz = dev_priv->cdclk.hw.ref; + int refclk_khz = dev_priv->dpll.ref_clks.nssc; int clock = crtc_state->port_clock; u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac; u32 iref_ndiv, iref_trim, iref_pulse_w; @@ -2761,7 +3191,8 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, if (!icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz, pll_state, is_dkl)) { - DRM_DEBUG_KMS("Failed to find divisors for clock %d\n", clock); + drm_dbg_kms(&dev_priv->drm, + "Failed to find divisors for clock %d\n", clock); return false; } @@ -2774,8 +3205,9 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, } if (m2div_int > 255) { - DRM_DEBUG_KMS("Failed to find mdiv for clock %d\n", - clock); + drm_dbg_kms(&dev_priv->drm, + "Failed to find mdiv for clock %d\n", + clock); return false; } } @@ -2944,6 +3376,78 @@ static bool icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state, return true; } +static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv, + const struct intel_shared_dpll *pll) +{ + const struct intel_dpll_hw_state *pll_state = &pll->state.hw_state; + u32 m1, m2_int, m2_frac, div1, div2, ref_clock; + u64 tmp; + + ref_clock = dev_priv->dpll.ref_clks.nssc; + + if (INTEL_GEN(dev_priv) >= 12) { + m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK; + m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT; + m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK; + + if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) { + m2_frac = pll_state->mg_pll_bias & + DKL_PLL_BIAS_FBDIV_FRAC_MASK; + m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT; + } else { + m2_frac = 0; + } + } else { + m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK; + m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; + + if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) { + m2_frac = pll_state->mg_pll_div0 & + MG_PLL_DIV0_FBDIV_FRAC_MASK; + m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT; + } else { + m2_frac = 0; + } + } + + switch (pll_state->mg_clktop2_hsclkctl & + MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: + div1 = 2; + break; + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: + div1 = 3; + break; + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: + div1 = 5; + break; + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: + div1 = 7; + break; + default: + MISSING_CASE(pll_state->mg_clktop2_hsclkctl); + return 0; + } + + div2 = (pll_state->mg_clktop2_hsclkctl & + MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> + MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; + + /* div2 value of 0 is same as 1 means no div */ + if (div2 == 0) + div2 = 1; + + /* + * Adjust the original formula to delay the division by 2^22 in order to + * minimize possible rounding errors. + */ + tmp = (u64)m1 * m2_int * ref_clock + + (((u64)m1 * m2_frac * ref_clock) >> 22); + tmp = div_u64(tmp, 5 * div1 * div2); + + return tmp; +} + /** * icl_set_active_port_dpll - select the active port DPLL for a given CRTC * @crtc_state: state for the CRTC to select the DPLL for @@ -2996,7 +3500,8 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, unsigned long dpll_mask; if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate combo PHY PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate combo PHY PLL state.\n"); return false; } @@ -3013,8 +3518,9 @@ static bool icl_get_combo_phy_dpll(struct intel_atomic_state *state, &port_dpll->hw_state, dpll_mask); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No combo PHY PLL found for [ENCODER:%d:%s]\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&dev_priv->drm, + "No combo PHY PLL found for [ENCODER:%d:%s]\n", + encoder->base.base.id, encoder->base.name); return false; } @@ -3038,7 +3544,8 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT]; if (!icl_calc_dpll_state(crtc_state, encoder, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate TBT PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate TBT PLL state.\n"); return false; } @@ -3046,7 +3553,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, &port_dpll->hw_state, BIT(DPLL_ID_ICL_TBTPLL)); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No TBT-ALT PLL found\n"); + drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n"); return false; } intel_reference_shared_dpll(state, crtc, @@ -3055,7 +3562,8 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY]; if (!icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state)) { - DRM_DEBUG_KMS("Could not calculate MG PHY PLL state.\n"); + drm_dbg_kms(&dev_priv->drm, + "Could not calculate MG PHY PLL state.\n"); goto err_unreference_tbt_pll; } @@ -3065,7 +3573,7 @@ static bool icl_get_tc_phy_dplls(struct intel_atomic_state *state, &port_dpll->hw_state, BIT(dpll_id)); if (!port_dpll->pll) { - DRM_DEBUG_KMS("No MG PHY PLL found\n"); + drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n"); goto err_unreference_tbt_pll; } intel_reference_shared_dpll(state, crtc, @@ -3140,37 +3648,39 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(MG_PLL_ENABLE(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port)); if (!(val & PLL_ENABLE)) goto out; - hw_state->mg_refclkin_ctl = I915_READ(MG_REFCLKIN_CTL(tc_port)); + hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, + MG_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_coreclkctl1 = - I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); + intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; hw_state->mg_clktop2_hsclkctl = - I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); + intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; - hw_state->mg_pll_div0 = I915_READ(MG_PLL_DIV0(tc_port)); - hw_state->mg_pll_div1 = I915_READ(MG_PLL_DIV1(tc_port)); - hw_state->mg_pll_lf = I915_READ(MG_PLL_LF(tc_port)); - hw_state->mg_pll_frac_lock = I915_READ(MG_PLL_FRAC_LOCK(tc_port)); - hw_state->mg_pll_ssc = I915_READ(MG_PLL_SSC(tc_port)); + hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port)); + hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port)); + hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port)); + hw_state->mg_pll_frac_lock = intel_de_read(dev_priv, + MG_PLL_FRAC_LOCK(tc_port)); + hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port)); - hw_state->mg_pll_bias = I915_READ(MG_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias = - I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); - if (dev_priv->cdclk.hw.ref == 38400) { + if (dev_priv->dpll.ref_clks.nssc == 38400) { hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART; hw_state->mg_pll_bias_mask = 0; } else { @@ -3202,7 +3712,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(MG_PLL_ENABLE(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port)); if (!(val & PLL_ENABLE)) goto out; @@ -3210,13 +3720,15 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, * All registers read here have the same HIP_INDEX_REG even though * they are on different building blocks */ - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x2)); - hw_state->mg_refclkin_ctl = I915_READ(DKL_REFCLKIN_CTL(tc_port)); + hw_state->mg_refclkin_ctl = intel_de_read(dev_priv, + DKL_REFCLKIN_CTL(tc_port)); hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK; hw_state->mg_clktop2_hsclkctl = - I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port)); + intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); hw_state->mg_clktop2_hsclkctl &= MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | @@ -3224,32 +3736,32 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv, MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK; hw_state->mg_clktop2_coreclkctl1 = - I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port)); + intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); hw_state->mg_clktop2_coreclkctl1 &= MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; - hw_state->mg_pll_div0 = I915_READ(DKL_PLL_DIV0(tc_port)); + hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); hw_state->mg_pll_div0 &= (DKL_PLL_DIV0_INTEG_COEFF_MASK | DKL_PLL_DIV0_PROP_COEFF_MASK | DKL_PLL_DIV0_FBPREDIV_MASK | DKL_PLL_DIV0_FBDIV_INT_MASK); - hw_state->mg_pll_div1 = I915_READ(DKL_PLL_DIV1(tc_port)); + hw_state->mg_pll_div1 = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); - hw_state->mg_pll_ssc = I915_READ(DKL_PLL_SSC(tc_port)); + hw_state->mg_pll_ssc = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); - hw_state->mg_pll_bias = I915_READ(DKL_PLL_BIAS(tc_port)); + hw_state->mg_pll_bias = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); hw_state->mg_pll_tdc_coldst_bias = - I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); @@ -3274,20 +3786,26 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv, if (!wakeref) return false; - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); if (!(val & PLL_ENABLE)) goto out; if (INTEL_GEN(dev_priv) >= 12) { - hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id)); + hw_state->cfgcr0 = intel_de_read(dev_priv, + TGL_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + TGL_DPLL_CFGCR1(id)); } else { if (IS_ELKHARTLAKE(dev_priv) && id == DPLL_ID_EHL_DPLL4) { - hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(4)); - hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(4)); + hw_state->cfgcr0 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR0(4)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR1(4)); } else { - hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id)); - hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id)); + hw_state->cfgcr0 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR0(id)); + hw_state->cfgcr1 = intel_de_read(dev_priv, + ICL_DPLL_CFGCR1(id)); } } @@ -3338,9 +3856,9 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv, } } - I915_WRITE(cfgcr0_reg, hw_state->cfgcr0); - I915_WRITE(cfgcr1_reg, hw_state->cfgcr1); - POSTING_READ(cfgcr1_reg); + intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); + intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1); + intel_de_posting_read(dev_priv, cfgcr1_reg); } static void icl_mg_pll_write(struct drm_i915_private *dev_priv, @@ -3356,41 +3874,42 @@ static void icl_mg_pll_write(struct drm_i915_private *dev_priv, * during the calc/readout phase if the mask depends on some other HW * state like refclk, see icl_calc_mg_pll_state(). */ - val = I915_READ(MG_REFCLKIN_CTL(tc_port)); + val = intel_de_read(dev_priv, MG_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - I915_WRITE(MG_REFCLKIN_CTL(tc_port), val); + intel_de_write(dev_priv, MG_REFCLKIN_CTL(tc_port), val); - val = I915_READ(MG_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - I915_WRITE(MG_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_de_write(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port), val); - val = I915_READ(MG_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - I915_WRITE(MG_CLKTOP2_HSCLKCTL(tc_port), val); + intel_de_write(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port), val); - I915_WRITE(MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); - I915_WRITE(MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); - I915_WRITE(MG_PLL_LF(tc_port), hw_state->mg_pll_lf); - I915_WRITE(MG_PLL_FRAC_LOCK(tc_port), hw_state->mg_pll_frac_lock); - I915_WRITE(MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); + intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0); + intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1); + intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf); + intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port), + hw_state->mg_pll_frac_lock); + intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc); - val = I915_READ(MG_PLL_BIAS(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port)); val &= ~hw_state->mg_pll_bias_mask; val |= hw_state->mg_pll_bias; - I915_WRITE(MG_PLL_BIAS(tc_port), val); + intel_de_write(dev_priv, MG_PLL_BIAS(tc_port), val); - val = I915_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~hw_state->mg_pll_tdc_coldst_bias_mask; val |= hw_state->mg_pll_tdc_coldst_bias; - I915_WRITE(MG_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_de_write(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port), val); - POSTING_READ(MG_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port)); } static void dkl_pll_write(struct drm_i915_private *dev_priv, @@ -3404,62 +3923,63 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv, * All registers programmed here have the same HIP_INDEX_REG even * though on different building block */ - I915_WRITE(HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, 0x2)); + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port), + HIP_INDEX_VAL(tc_port, 0x2)); /* All the registers are RMW */ - val = I915_READ(DKL_REFCLKIN_CTL(tc_port)); + val = intel_de_read(dev_priv, DKL_REFCLKIN_CTL(tc_port)); val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK; val |= hw_state->mg_refclkin_ctl; - I915_WRITE(DKL_REFCLKIN_CTL(tc_port), val); + intel_de_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val); - val = I915_READ(DKL_CLKTOP2_CORECLKCTL1(tc_port)); + val = intel_de_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port)); val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK; val |= hw_state->mg_clktop2_coreclkctl1; - I915_WRITE(DKL_CLKTOP2_CORECLKCTL1(tc_port), val); + intel_de_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); - val = I915_READ(DKL_CLKTOP2_HSCLKCTL(tc_port)); + val = intel_de_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port)); val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK | MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK); val |= hw_state->mg_clktop2_hsclkctl; - I915_WRITE(DKL_CLKTOP2_HSCLKCTL(tc_port), val); + intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val); - val = I915_READ(DKL_PLL_DIV0(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port)); val &= ~(DKL_PLL_DIV0_INTEG_COEFF_MASK | DKL_PLL_DIV0_PROP_COEFF_MASK | DKL_PLL_DIV0_FBPREDIV_MASK | DKL_PLL_DIV0_FBDIV_INT_MASK); val |= hw_state->mg_pll_div0; - I915_WRITE(DKL_PLL_DIV0(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_DIV0(tc_port), val); - val = I915_READ(DKL_PLL_DIV1(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_DIV1(tc_port)); val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK | DKL_PLL_DIV1_TDC_TARGET_CNT_MASK); val |= hw_state->mg_pll_div1; - I915_WRITE(DKL_PLL_DIV1(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_DIV1(tc_port), val); - val = I915_READ(DKL_PLL_SSC(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_SSC(tc_port)); val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK | DKL_PLL_SSC_STEP_LEN_MASK | DKL_PLL_SSC_STEP_NUM_MASK | DKL_PLL_SSC_EN); val |= hw_state->mg_pll_ssc; - I915_WRITE(DKL_PLL_SSC(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_SSC(tc_port), val); - val = I915_READ(DKL_PLL_BIAS(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port)); val &= ~(DKL_PLL_BIAS_FRAC_EN_H | DKL_PLL_BIAS_FBDIV_FRAC_MASK); val |= hw_state->mg_pll_bias; - I915_WRITE(DKL_PLL_BIAS(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_BIAS(tc_port), val); - val = I915_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port)); + val = intel_de_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK | DKL_PLL_TDC_FEED_FWD_GAIN_MASK); val |= hw_state->mg_pll_tdc_coldst_bias; - I915_WRITE(DKL_PLL_TDC_COLDST_BIAS(tc_port), val); + intel_de_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); - POSTING_READ(DKL_PLL_TDC_COLDST_BIAS(tc_port)); + intel_de_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port)); } static void icl_pll_power_enable(struct drm_i915_private *dev_priv, @@ -3468,16 +3988,17 @@ static void icl_pll_power_enable(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val |= PLL_POWER_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* * The spec says we need to "wait" but it also says it should be * immediate. */ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - DRM_ERROR("PLL %d Power not enabled\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d Power not enabled\n", + pll->info->id); } static void icl_pll_enable(struct drm_i915_private *dev_priv, @@ -3486,13 +4007,13 @@ static void icl_pll_enable(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val |= PLL_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* Timeout is actually 600us. */ if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1)) - DRM_ERROR("PLL %d not locked\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id); } static void combo_pll_enable(struct drm_i915_private *dev_priv, @@ -3584,26 +4105,27 @@ static void icl_pll_disable(struct drm_i915_private *dev_priv, * nothign here. */ - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val &= ~PLL_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* Timeout is actually 1us. */ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1)) - DRM_ERROR("PLL %d locked\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id); /* DVFS post sequence would be here. See the comment above. */ - val = I915_READ(enable_reg); + val = intel_de_read(dev_priv, enable_reg); val &= ~PLL_POWER_ENABLE; - I915_WRITE(enable_reg, val); + intel_de_write(dev_priv, enable_reg, val); /* * The spec says we need to "wait" but it also says it should be * immediate. */ if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1)) - DRM_ERROR("PLL %d Power not disabled\n", pll->info->id); + drm_err(&dev_priv->drm, "PLL %d Power not disabled\n", + pll->info->id); } static void combo_pll_disable(struct drm_i915_private *dev_priv, @@ -3639,44 +4161,54 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv, icl_pll_disable(dev_priv, pll, enable_reg); } +static void icl_update_dpll_ref_clks(struct drm_i915_private *i915) +{ + /* No SSC ref */ + i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref; +} + static void icl_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - DRM_DEBUG_KMS("dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, " - "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " - "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " - "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " - "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, " - "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", - hw_state->cfgcr0, hw_state->cfgcr1, - hw_state->mg_refclkin_ctl, - hw_state->mg_clktop2_coreclkctl1, - hw_state->mg_clktop2_hsclkctl, - hw_state->mg_pll_div0, - hw_state->mg_pll_div1, - hw_state->mg_pll_lf, - hw_state->mg_pll_frac_lock, - hw_state->mg_pll_ssc, - hw_state->mg_pll_bias, - hw_state->mg_pll_tdc_coldst_bias); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, " + "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, " + "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, " + "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, " + "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, " + "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n", + hw_state->cfgcr0, hw_state->cfgcr1, + hw_state->mg_refclkin_ctl, + hw_state->mg_clktop2_coreclkctl1, + hw_state->mg_clktop2_hsclkctl, + hw_state->mg_pll_div0, + hw_state->mg_pll_div1, + hw_state->mg_pll_lf, + hw_state->mg_pll_frac_lock, + hw_state->mg_pll_ssc, + hw_state->mg_pll_bias, + hw_state->mg_pll_tdc_coldst_bias); } static const struct intel_shared_dpll_funcs combo_pll_funcs = { .enable = combo_pll_enable, .disable = combo_pll_disable, .get_hw_state = combo_pll_get_hw_state, + .get_freq = icl_ddi_combo_pll_get_freq, }; static const struct intel_shared_dpll_funcs tbt_pll_funcs = { .enable = tbt_pll_enable, .disable = tbt_pll_disable, .get_hw_state = tbt_pll_get_hw_state, + .get_freq = icl_ddi_tbt_pll_get_freq, }; static const struct intel_shared_dpll_funcs mg_pll_funcs = { .enable = mg_pll_enable, .disable = mg_pll_disable, .get_hw_state = mg_pll_get_hw_state, + .get_freq = icl_ddi_mg_pll_get_freq, }; static const struct dpll_info icl_plls[] = { @@ -3695,6 +4227,7 @@ static const struct intel_dpll_mgr icl_pll_mgr = { .get_dplls = icl_get_dplls, .put_dplls = icl_put_dplls, .update_active_dpll = icl_update_active_dpll, + .update_ref_clks = icl_update_dpll_ref_clks, .dump_hw_state = icl_dump_hw_state, }; @@ -3709,6 +4242,7 @@ static const struct intel_dpll_mgr ehl_pll_mgr = { .dpll_info = ehl_plls, .get_dplls = icl_get_dplls, .put_dplls = icl_put_dplls, + .update_ref_clks = icl_update_dpll_ref_clks, .dump_hw_state = icl_dump_hw_state, }; @@ -3716,6 +4250,7 @@ static const struct intel_shared_dpll_funcs dkl_pll_funcs = { .enable = mg_pll_enable, .disable = mg_pll_disable, .get_hw_state = dkl_pll_get_hw_state, + .get_freq = icl_ddi_mg_pll_get_freq, }; static const struct dpll_info tgl_plls[] = { @@ -3736,6 +4271,7 @@ static const struct intel_dpll_mgr tgl_pll_mgr = { .get_dplls = icl_get_dplls, .put_dplls = icl_put_dplls, .update_active_dpll = icl_update_active_dpll, + .update_ref_clks = icl_update_dpll_ref_clks, .dump_hw_state = icl_dump_hw_state, }; @@ -3770,22 +4306,22 @@ void intel_shared_dpll_init(struct drm_device *dev) dpll_mgr = &pch_pll_mgr; if (!dpll_mgr) { - dev_priv->num_shared_dpll = 0; + dev_priv->dpll.num_shared_dpll = 0; return; } dpll_info = dpll_mgr->dpll_info; for (i = 0; dpll_info[i].name; i++) { - WARN_ON(i != dpll_info[i].id); - dev_priv->shared_dplls[i].info = &dpll_info[i]; + drm_WARN_ON(dev, i != dpll_info[i].id); + dev_priv->dpll.shared_dplls[i].info = &dpll_info[i]; } - dev_priv->dpll_mgr = dpll_mgr; - dev_priv->num_shared_dpll = i; - mutex_init(&dev_priv->dpll_lock); + dev_priv->dpll.mgr = dpll_mgr; + dev_priv->dpll.num_shared_dpll = i; + mutex_init(&dev_priv->dpll.lock); - BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); + BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS); } /** @@ -3812,9 +4348,9 @@ bool intel_reserve_shared_dplls(struct intel_atomic_state *state, struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; + const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; - if (WARN_ON(!dpll_mgr)) + if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) return false; return dpll_mgr->get_dplls(state, crtc, encoder); @@ -3835,7 +4371,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; + const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; /* * FIXME: this function is called for every platform having a @@ -3864,35 +4400,114 @@ void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll_mgr; + const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr; - if (WARN_ON(!dpll_mgr)) + if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr)) return; dpll_mgr->update_active_dpll(state, crtc, encoder); } /** + * intel_dpll_get_freq - calculate the DPLL's output frequency + * @i915: i915 device + * @pll: DPLL for which to calculate the output frequency + * + * Return the output frequency corresponding to @pll's current state. + */ +int intel_dpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll) +{ + if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq)) + return 0; + + return pll->info->funcs->get_freq(i915, pll); +} + +static void readout_dpll_hw_state(struct drm_i915_private *i915, + struct intel_shared_dpll *pll) +{ + struct intel_crtc *crtc; + + pll->on = pll->info->funcs->get_hw_state(i915, pll, + &pll->state.hw_state); + + if (IS_ELKHARTLAKE(i915) && pll->on && + pll->info->id == DPLL_ID_EHL_DPLL4) { + pll->wakeref = intel_display_power_get(i915, + POWER_DOMAIN_DPLL_DC_OFF); + } + + pll->state.crtc_mask = 0; + for_each_intel_crtc(&i915->drm, crtc) { + struct intel_crtc_state *crtc_state = + to_intel_crtc_state(crtc->base.state); + + if (crtc_state->hw.active && crtc_state->shared_dpll == pll) + pll->state.crtc_mask |= 1 << crtc->pipe; + } + pll->active_mask = pll->state.crtc_mask; + + drm_dbg_kms(&i915->drm, + "%s hw state readout: crtc_mask 0x%08x, on %i\n", + pll->info->name, pll->state.crtc_mask, pll->on); +} + +void intel_dpll_readout_hw_state(struct drm_i915_private *i915) +{ + int i; + + if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks) + i915->dpll.mgr->update_ref_clks(i915); + + for (i = 0; i < i915->dpll.num_shared_dpll; i++) + readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]); +} + +static void sanitize_dpll_state(struct drm_i915_private *i915, + struct intel_shared_dpll *pll) +{ + if (!pll->on || pll->active_mask) + return; + + drm_dbg_kms(&i915->drm, + "%s enabled but not in use, disabling\n", + pll->info->name); + + pll->info->funcs->disable(i915, pll); + pll->on = false; +} + +void intel_dpll_sanitize_state(struct drm_i915_private *i915) +{ + int i; + + for (i = 0; i < i915->dpll.num_shared_dpll; i++) + sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]); +} + +/** * intel_shared_dpll_dump_hw_state - write hw_state to dmesg * @dev_priv: i915 drm device * @hw_state: hw state to be written to the log * - * Write the relevant values in @hw_state to dmesg using DRM_DEBUG_KMS. + * Write the relevant values in @hw_state to dmesg using drm_dbg_kms. */ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state) { - if (dev_priv->dpll_mgr) { - dev_priv->dpll_mgr->dump_hw_state(dev_priv, hw_state); + if (dev_priv->dpll.mgr) { + dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state); } else { /* fallback for platforms that don't use the shared dpll * infrastructure */ - DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " - "fp0: 0x%x, fp1: 0x%x\n", - hw_state->dpll, - hw_state->dpll_md, - hw_state->fp0, - hw_state->fp1); + drm_dbg_kms(&dev_priv->drm, + "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " + "fp0: 0x%x, fp1: 0x%x\n", + hw_state->dpll, + hw_state->dpll_md, + hw_state->fp0, + hw_state->fp1); } } diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index 2a104c64291d..5d9a2bc371e7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -278,6 +278,15 @@ struct intel_shared_dpll_funcs { bool (*get_hw_state)(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *hw_state); + + /** + * @get_freq: + * + * Hook for calculating the pll's output frequency based on its + * current state. + */ + int (*get_freq)(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll); }; /** @@ -372,15 +381,18 @@ void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, void intel_update_active_dpll(struct intel_atomic_state *state, struct intel_crtc *crtc, struct intel_encoder *encoder); +int intel_dpll_get_freq(struct drm_i915_private *i915, + const struct intel_shared_dpll *pll); void intel_prepare_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); void intel_shared_dpll_swap_state(struct intel_atomic_state *state); void intel_shared_dpll_init(struct drm_device *dev); +void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); +void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_dpll_hw_state *hw_state); -int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv); enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); bool intel_dpll_is_combophy(enum intel_dpll_id id); diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index ada006a690df..d7a6bf2277df 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -40,7 +40,7 @@ static inline bool is_dsb_busy(struct intel_dsb *dsb) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id)); + return DSB_STATUS & intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); } static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb) @@ -50,16 +50,16 @@ static inline bool intel_dsb_enable_engine(struct intel_dsb *dsb) enum pipe pipe = crtc->pipe; u32 dsb_ctrl; - dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id)); + dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); if (DSB_STATUS & dsb_ctrl) { - DRM_DEBUG_KMS("DSB engine is busy.\n"); + drm_dbg_kms(&dev_priv->drm, "DSB engine is busy.\n"); return false; } dsb_ctrl |= DSB_ENABLE; - I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl); + intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl); - POSTING_READ(DSB_CTRL(pipe, dsb->id)); + intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id)); return true; } @@ -70,16 +70,16 @@ static inline bool intel_dsb_disable_engine(struct intel_dsb *dsb) enum pipe pipe = crtc->pipe; u32 dsb_ctrl; - dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id)); + dsb_ctrl = intel_de_read(dev_priv, DSB_CTRL(pipe, dsb->id)); if (DSB_STATUS & dsb_ctrl) { - DRM_DEBUG_KMS("DSB engine is busy.\n"); + drm_dbg_kms(&dev_priv->drm, "DSB engine is busy.\n"); return false; } dsb_ctrl &= ~DSB_ENABLE; - I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl); + intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), dsb_ctrl); - POSTING_READ(DSB_CTRL(pipe, dsb->id)); + intel_de_posting_read(dev_priv, DSB_CTRL(pipe, dsb->id)); return true; } @@ -115,20 +115,20 @@ intel_dsb_get(struct intel_crtc *crtc) obj = i915_gem_object_create_internal(i915, DSB_BUF_SIZE); if (IS_ERR(obj)) { - DRM_ERROR("Gem object creation failed\n"); + drm_err(&i915->drm, "Gem object creation failed\n"); goto out; } vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { - DRM_ERROR("Vma creation failed\n"); + drm_err(&i915->drm, "Vma creation failed\n"); i915_gem_object_put(obj); goto out; } buf = i915_gem_object_pin_map(vma->obj, I915_MAP_WC); if (IS_ERR(buf)) { - DRM_ERROR("Command buffer creation failed\n"); + drm_err(&i915->drm, "Command buffer creation failed\n"); goto out; } @@ -165,7 +165,7 @@ void intel_dsb_put(struct intel_dsb *dsb) if (!HAS_DSB(i915)) return; - if (WARN_ON(dsb->refcount == 0)) + if (drm_WARN_ON(&i915->drm, dsb->refcount == 0)) return; if (--dsb->refcount == 0) { @@ -198,12 +198,12 @@ void intel_dsb_indexed_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 reg_val; if (!buf) { - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); return; } - if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) { - DRM_DEBUG_KMS("DSB buffer overflow\n"); + if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { + drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); return; } @@ -272,12 +272,12 @@ void intel_dsb_reg_write(struct intel_dsb *dsb, i915_reg_t reg, u32 val) u32 *buf = dsb->cmd_buf; if (!buf) { - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); return; } - if (WARN_ON(dsb->free_pos >= DSB_BUF_SIZE)) { - DRM_DEBUG_KMS("DSB buffer overflow\n"); + if (drm_WARN_ON(&dev_priv->drm, dsb->free_pos >= DSB_BUF_SIZE)) { + drm_dbg_kms(&dev_priv->drm, "DSB buffer overflow\n"); return; } @@ -310,10 +310,12 @@ void intel_dsb_commit(struct intel_dsb *dsb) goto reset; if (is_dsb_busy(dsb)) { - DRM_ERROR("HEAD_PTR write failed - dsb engine is busy.\n"); + drm_err(&dev_priv->drm, + "HEAD_PTR write failed - dsb engine is busy.\n"); goto reset; } - I915_WRITE(DSB_HEAD(pipe, dsb->id), i915_ggtt_offset(dsb->vma)); + intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id), + i915_ggtt_offset(dsb->vma)); tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES); if (tail > dsb->free_pos * 4) @@ -321,14 +323,18 @@ void intel_dsb_commit(struct intel_dsb *dsb) (tail - dsb->free_pos * 4)); if (is_dsb_busy(dsb)) { - DRM_ERROR("TAIL_PTR write failed - dsb engine is busy.\n"); + drm_err(&dev_priv->drm, + "TAIL_PTR write failed - dsb engine is busy.\n"); goto reset; } - DRM_DEBUG_KMS("DSB execution started - head 0x%x, tail 0x%x\n", - i915_ggtt_offset(dsb->vma), tail); - I915_WRITE(DSB_TAIL(pipe, dsb->id), i915_ggtt_offset(dsb->vma) + tail); + drm_dbg_kms(&dev_priv->drm, + "DSB execution started - head 0x%x, tail 0x%x\n", + i915_ggtt_offset(dsb->vma), tail); + intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id), + i915_ggtt_offset(dsb->vma) + tail); if (wait_for(!is_dsb_busy(dsb), 1)) { - DRM_ERROR("Timed out waiting for DSB workload completion.\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for DSB workload completion.\n"); goto reset; } diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c index c87838843d0b..b53c50372918 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c @@ -45,7 +45,7 @@ static u32 dcs_get_backlight(struct intel_connector *connector) { - struct intel_encoder *encoder = connector->encoder; + struct intel_encoder *encoder = intel_attached_encoder(connector); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); struct mipi_dsi_device *dsi_device; u8 data = 0; @@ -160,13 +160,13 @@ int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector) { struct drm_device *dev = intel_connector->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_encoder *encoder = intel_connector->encoder; + struct intel_encoder *encoder = intel_attached_encoder(intel_connector); struct intel_panel *panel = &intel_connector->panel; if (dev_priv->vbt.backlight.type != INTEL_BACKLIGHT_DSI_DCS) return -ENODEV; - if (WARN_ON(encoder->type != INTEL_OUTPUT_DSI)) + if (drm_WARN_ON(dev, encoder->type != INTEL_OUTPUT_DSI)) return -EINVAL; panel->backlight.setup = dcs_setup_backlight; diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index 04f953ba8f00..574dcfec9577 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -36,7 +36,6 @@ #include <drm/drm_crtc.h> #include <drm/drm_edid.h> -#include <drm/i915_drm.h> #include <video/mipi_display.h> @@ -136,7 +135,7 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u16 len; enum port port; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); flags = *data++; type = *data++; @@ -158,7 +157,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, dsi_device = intel_dsi->dsi_hosts[port]->device; if (!dsi_device) { - DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); + drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", + port_name(port)); goto out; } @@ -182,7 +182,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: - DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); + drm_dbg(&dev_priv->drm, + "Generic Read not yet implemented or used\n"); break; case MIPI_DSI_GENERIC_LONG_WRITE: mipi_dsi_generic_write(dsi_device, data, len); @@ -194,7 +195,8 @@ static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, mipi_dsi_dcs_write_buffer(dsi_device, data, 2); break; case MIPI_DSI_DCS_READ: - DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); + drm_dbg(&dev_priv->drm, + "DCS Read not yet implemented or used\n"); break; case MIPI_DSI_DCS_LONG_WRITE: mipi_dsi_dcs_write_buffer(dsi_device, data, len); @@ -212,9 +214,10 @@ out: static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) { + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); u32 delay = *((const u32 *) data); - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&i915->drm, "\n"); usleep_range(delay, delay + 10); data += 4; @@ -231,7 +234,8 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, u8 port; if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { - DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); + drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", + gpio_index); return; } @@ -244,10 +248,11 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv, if (gpio_source == 0) { port = IOSF_PORT_GPIO_NC; } else if (gpio_source == 1) { - DRM_DEBUG_KMS("SC gpio not supported\n"); + drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); return; } else { - DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); + drm_dbg_kms(&dev_priv->drm, + "unknown gpio source %u\n", gpio_source); return; } } @@ -291,13 +296,15 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv, } else { /* XXX: The spec is unclear about CHV GPIO on seq v2 */ if (gpio_source != 0) { - DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); + drm_dbg_kms(&dev_priv->drm, + "unknown gpio source %u\n", gpio_source); return; } if (gpio_index >= CHV_GPIO_IDX_START_E) { - DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n", - gpio_index); + drm_dbg_kms(&dev_priv->drm, + "invalid gpio index %u for GPIO N\n", + gpio_index); return; } @@ -332,8 +339,9 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, GPIOD_OUT_HIGH); if (IS_ERR_OR_NULL(gpio_desc)) { - DRM_ERROR("GPIO index %u request failed (%ld)\n", - gpio_index, PTR_ERR(gpio_desc)); + drm_err(&dev_priv->drm, + "GPIO index %u request failed (%ld)\n", + gpio_index, PTR_ERR(gpio_desc)); return; } @@ -346,7 +354,7 @@ static void bxt_exec_gpio(struct drm_i915_private *dev_priv, static void icl_exec_gpio(struct drm_i915_private *dev_priv, u8 gpio_source, u8 gpio_index, bool value) { - DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n"); + drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); } static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) @@ -356,7 +364,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) u8 gpio_source, gpio_index = 0, gpio_number; bool value; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); if (dev_priv->vbt.dsi.seq_version >= 3) gpio_index = *data++; @@ -494,13 +502,16 @@ err_bus: static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) { - DRM_DEBUG_KMS("Skipping SPI element execution\n"); + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); + + drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); return data + *(data + 5) + 6; } static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) { + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); #ifdef CONFIG_PMIC_OPREGION u32 value, mask, reg_address; u16 i2c_address; @@ -516,9 +527,10 @@ static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) reg_address, value, mask); if (ret) - DRM_ERROR("%s failed, error: %d\n", __func__, ret); + drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); #else - DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); + drm_err(&i915->drm, + "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); #endif return data + 15; @@ -570,17 +582,18 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, const u8 *data; fn_mipi_elem_exec mipi_elem_exec; - if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) + if (drm_WARN_ON(&dev_priv->drm, + seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) return; data = dev_priv->vbt.dsi.sequence[seq_id]; if (!data) return; - WARN_ON(*data != seq_id); + drm_WARN_ON(&dev_priv->drm, *data != seq_id); - DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n", - seq_id, sequence_name(seq_id)); + drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", + seq_id, sequence_name(seq_id)); /* Skip Sequence Byte. */ data++; @@ -612,18 +625,21 @@ static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, /* Consistency check if we have size. */ if (operation_size && data != next) { - DRM_ERROR("Inconsistent operation size\n"); + drm_err(&dev_priv->drm, + "Inconsistent operation size\n"); return; } } else if (operation_size) { /* We have size, skip. */ - DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n", - operation_byte); + drm_dbg_kms(&dev_priv->drm, + "Unsupported MIPI operation byte %u\n", + operation_byte); data += operation_size; } else { /* No size, can't skip without parsing. */ - DRM_ERROR("Unsupported MIPI operation byte %u\n", - operation_byte); + drm_err(&dev_priv->drm, + "Unsupported MIPI operation byte %u\n", + operation_byte); return; } } @@ -658,40 +674,54 @@ void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) void intel_dsi_log_params(struct intel_dsi *intel_dsi) { - DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk); - DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap); - DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count); - DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg); - DRM_DEBUG_KMS("Video mode format %s\n", - intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? - "non-burst with sync pulse" : - intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? - "non-burst with sync events" : - intel_dsi->video_mode_format == VIDEO_MODE_BURST ? - "burst" : "<unknown>"); - DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio); - DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val); - DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt)); - DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop)); - DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); + struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); + + drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); + drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", + intel_dsi->pixel_overlap); + drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); + drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); + drm_dbg_kms(&i915->drm, "Video mode format %s\n", + intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? + "non-burst with sync pulse" : + intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? + "non-burst with sync events" : + intel_dsi->video_mode_format == VIDEO_MODE_BURST ? + "burst" : "<unknown>"); + drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", + intel_dsi->burst_mode_ratio); + drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); + drm_dbg_kms(&i915->drm, "Eot %s\n", + enableddisabled(intel_dsi->eotp_pkt)); + drm_dbg_kms(&i915->drm, "Clockstop %s\n", + enableddisabled(!intel_dsi->clock_stop)); + drm_dbg_kms(&i915->drm, "Mode %s\n", + intel_dsi->operation_mode ? "command" : "video"); if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) - DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); + drm_dbg_kms(&i915->drm, + "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) - DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); + drm_dbg_kms(&i915->drm, + "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); else - DRM_DEBUG_KMS("Dual link: NONE\n"); - DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); - DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); - DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); - DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); - DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); - DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); - DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); - DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); - DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); - DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); - DRM_DEBUG_KMS("BTA %s\n", - enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); + drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); + drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); + drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); + drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", + intel_dsi->lp_rx_timeout); + drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", + intel_dsi->turn_arnd_val); + drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); + drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", + intel_dsi->hs_to_lp_count); + drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); + drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); + drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", + intel_dsi->clk_lp_to_hs_count); + drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", + intel_dsi->clk_hs_to_lp_count); + drm_dbg_kms(&i915->drm, "BTA %s\n", + enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); } bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) @@ -704,7 +734,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) u16 burst_mode_ratio; enum port port; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; @@ -763,7 +793,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) mipi_config->target_burst_mode_freq = bitrate; if (mipi_config->target_burst_mode_freq < bitrate) { - DRM_ERROR("Burst mode freq is less than computed\n"); + drm_err(&dev_priv->drm, + "Burst mode freq is less than computed\n"); return false; } @@ -773,7 +804,8 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); } else { - DRM_ERROR("Burst mode target is not set\n"); + drm_err(&dev_priv->drm, + "Burst mode target is not set\n"); return false; } } else @@ -856,17 +888,20 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, ARRAY_SIZE(soc_pwm_pinctrl_map)); if (ret) - DRM_ERROR("Failed to register pwm0 pinmux mapping\n"); + drm_err(&dev_priv->drm, + "Failed to register pwm0 pinmux mapping\n"); pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); if (IS_ERR(pinctrl)) - DRM_ERROR("Failed to set pinmux to PWM\n"); + drm_err(&dev_priv->drm, + "Failed to set pinmux to PWM\n"); } if (want_panel_gpio) { intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); if (IS_ERR(intel_dsi->gpio_panel)) { - DRM_ERROR("Failed to own gpio for panel control\n"); + drm_err(&dev_priv->drm, + "Failed to own gpio for panel control\n"); intel_dsi->gpio_panel = NULL; } } @@ -875,7 +910,8 @@ void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) intel_dsi->gpio_backlight = gpiod_get(dev->dev, "backlight", flags); if (IS_ERR(intel_dsi->gpio_backlight)) { - DRM_ERROR("Failed to own gpio for backlight control\n"); + drm_err(&dev_priv->drm, + "Failed to own gpio for backlight control\n"); intel_dsi->gpio_backlight = NULL; } } diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 86a337c9d85d..341d5ce8b062 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -30,7 +30,6 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "intel_connector.h" @@ -44,6 +43,7 @@ #define INTEL_DVO_CHIP_LVDS 1 #define INTEL_DVO_CHIP_TMDS 2 #define INTEL_DVO_CHIP_TVOUT 4 +#define INTEL_DVO_CHIP_LVDS_NO_FIXED 5 #define SIL164_ADDR 0x38 #define CH7xxx_ADDR 0x76 @@ -101,13 +101,13 @@ static const struct intel_dvo_device intel_dvo_devices[] = { .dev_ops = &ch7017_ops, }, { - .type = INTEL_DVO_CHIP_TMDS, + .type = INTEL_DVO_CHIP_LVDS_NO_FIXED, .name = "ns2501", .dvo_reg = DVOB, .dvo_srcdim_reg = DVOB_SRCDIM, .slave_addr = NS2501_ADDR, .dev_ops = &ns2501_ops, - } + }, }; struct intel_dvo { @@ -137,7 +137,7 @@ static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) struct intel_dvo *intel_dvo = intel_attached_dvo(connector); u32 tmp; - tmp = I915_READ(intel_dvo->dev.dvo_reg); + tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); if (!(tmp & DVO_ENABLE)) return false; @@ -152,7 +152,7 @@ static bool intel_dvo_get_hw_state(struct intel_encoder *encoder, struct intel_dvo *intel_dvo = enc_to_dvo(encoder); u32 tmp; - tmp = I915_READ(intel_dvo->dev.dvo_reg); + tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); *pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT; @@ -168,7 +168,7 @@ static void intel_dvo_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO); - tmp = I915_READ(intel_dvo->dev.dvo_reg); + tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); if (tmp & DVO_HSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; else @@ -190,11 +190,11 @@ static void intel_disable_dvo(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dvo *intel_dvo = enc_to_dvo(encoder); i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; - u32 temp = I915_READ(dvo_reg); + u32 temp = intel_de_read(dev_priv, dvo_reg); intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false); - I915_WRITE(dvo_reg, temp & ~DVO_ENABLE); - I915_READ(dvo_reg); + intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE); + intel_de_read(dev_priv, dvo_reg); } static void intel_enable_dvo(struct intel_encoder *encoder, @@ -204,14 +204,14 @@ static void intel_enable_dvo(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dvo *intel_dvo = enc_to_dvo(encoder); i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; - u32 temp = I915_READ(dvo_reg); + u32 temp = intel_de_read(dev_priv, dvo_reg); intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, &pipe_config->hw.mode, &pipe_config->hw.adjusted_mode); - I915_WRITE(dvo_reg, temp | DVO_ENABLE); - I915_READ(dvo_reg); + intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE); + intel_de_read(dev_priv, dvo_reg); intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true); } @@ -286,7 +286,7 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder, i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; /* Save the data order, since I don't know what it should be set to. */ - dvo_val = I915_READ(dvo_reg) & + dvo_val = intel_de_read(dev_priv, dvo_reg) & (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG); dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | DVO_BLANK_ACTIVE_HIGH; @@ -301,11 +301,10 @@ static void intel_dvo_pre_enable(struct intel_encoder *encoder, /*I915_WRITE(DVOB_SRCDIM, (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ - I915_WRITE(dvo_srcdim_reg, - (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | - (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); + intel_de_write(dev_priv, dvo_srcdim_reg, + (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT)); /*I915_WRITE(DVOB, dvo_val);*/ - I915_WRITE(dvo_reg, dvo_val); + intel_de_write(dev_priv, dvo_reg, dvo_val); } static enum drm_connector_status @@ -481,15 +480,16 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) * initialize the device. */ for_each_pipe(dev_priv, pipe) { - dpll[pipe] = I915_READ(DPLL(pipe)); - I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); + dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(pipe), + dpll[pipe] | DPLL_DVO_2X_MODE); } dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); /* restore the DVO 2x clock state to original */ for_each_pipe(dev_priv, pipe) { - I915_WRITE(DPLL(pipe), dpll[pipe]); + intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); } intel_gmbus_force_bit(i2c, false); @@ -507,17 +507,21 @@ void intel_dvo_init(struct drm_i915_private *dev_priv) intel_encoder->port = port; intel_encoder->pipe_mask = ~0; - switch (dvo->type) { - case INTEL_DVO_CHIP_TMDS: + if (dvo->type != INTEL_DVO_CHIP_LVDS) intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | (1 << INTEL_OUTPUT_DVO); + + switch (dvo->type) { + case INTEL_DVO_CHIP_TMDS: + intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; drm_connector_init(&dev_priv->drm, connector, &intel_dvo_connector_funcs, DRM_MODE_CONNECTOR_DVII); encoder_type = DRM_MODE_ENCODER_TMDS; break; + case INTEL_DVO_CHIP_LVDS_NO_FIXED: case INTEL_DVO_CHIP_LVDS: - intel_encoder->cloneable = 0; drm_connector_init(&dev_priv->drm, connector, &intel_dvo_connector_funcs, DRM_MODE_CONNECTOR_LVDS); diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index a1048ece541e..2e5d835a9eaa 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -41,15 +41,12 @@ #include <drm/drm_fourcc.h> #include "i915_drv.h" +#include "i915_trace.h" +#include "i915_vgpu.h" #include "intel_display_types.h" #include "intel_fbc.h" #include "intel_frontbuffer.h" -static inline bool fbc_supported(struct drm_i915_private *dev_priv) -{ - return HAS_FBC(dev_priv); -} - /* * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's @@ -97,12 +94,12 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv) u32 fbc_ctl; /* Disable compression */ - fbc_ctl = I915_READ(FBC_CONTROL); + fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); if ((fbc_ctl & FBC_CTL_EN) == 0) return; fbc_ctl &= ~FBC_CTL_EN; - I915_WRITE(FBC_CONTROL, fbc_ctl); + intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); /* Wait for compressing bit to clear */ if (intel_de_wait_for_clear(dev_priv, FBC_STATUS, @@ -132,7 +129,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) /* Clear old tags */ for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) - I915_WRITE(FBC_TAG(i), 0); + intel_de_write(dev_priv, FBC_TAG(i), 0); if (IS_GEN(dev_priv, 4)) { u32 fbc_ctl2; @@ -142,12 +139,13 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane); if (params->fence_id >= 0) fbc_ctl2 |= FBC_CTL_CPU_FENCE; - I915_WRITE(FBC_CONTROL2, fbc_ctl2); - I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset); + intel_de_write(dev_priv, FBC_CONTROL2, fbc_ctl2); + intel_de_write(dev_priv, FBC_FENCE_OFF, + params->crtc.fence_y_offset); } /* enable it... */ - fbc_ctl = I915_READ(FBC_CONTROL); + fbc_ctl = intel_de_read(dev_priv, FBC_CONTROL); fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; if (IS_I945GM(dev_priv)) @@ -155,12 +153,12 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; if (params->fence_id >= 0) fbc_ctl |= params->fence_id; - I915_WRITE(FBC_CONTROL, fbc_ctl); + intel_de_write(dev_priv, FBC_CONTROL, fbc_ctl); } static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv) { - return I915_READ(FBC_CONTROL) & FBC_CTL_EN; + return intel_de_read(dev_priv, FBC_CONTROL) & FBC_CTL_EN; } static void g4x_fbc_activate(struct drm_i915_private *dev_priv) @@ -176,13 +174,14 @@ static void g4x_fbc_activate(struct drm_i915_private *dev_priv) if (params->fence_id >= 0) { dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id; - I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset); + intel_de_write(dev_priv, DPFC_FENCE_YOFF, + params->crtc.fence_y_offset); } else { - I915_WRITE(DPFC_FENCE_YOFF, 0); + intel_de_write(dev_priv, DPFC_FENCE_YOFF, 0); } /* enable it... */ - I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); + intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); } static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) @@ -190,23 +189,27 @@ static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv) u32 dpfc_ctl; /* Disable compression */ - dpfc_ctl = I915_READ(DPFC_CONTROL); + dpfc_ctl = intel_de_read(dev_priv, DPFC_CONTROL); if (dpfc_ctl & DPFC_CTL_EN) { dpfc_ctl &= ~DPFC_CTL_EN; - I915_WRITE(DPFC_CONTROL, dpfc_ctl); + intel_de_write(dev_priv, DPFC_CONTROL, dpfc_ctl); } } static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv) { - return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; + return intel_de_read(dev_priv, DPFC_CONTROL) & DPFC_CTL_EN; } /* This function forces a CFB recompression through the nuke operation. */ static void intel_fbc_recompress(struct drm_i915_private *dev_priv) { - I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE); - POSTING_READ(MSG_FBC_REND_STATE); + struct intel_fbc *fbc = &dev_priv->fbc; + + trace_intel_fbc_nuke(fbc->crtc); + + intel_de_write(dev_priv, MSG_FBC_REND_STATE, FBC_REND_NUKE); + intel_de_posting_read(dev_priv, MSG_FBC_REND_STATE); } static void ilk_fbc_activate(struct drm_i915_private *dev_priv) @@ -237,22 +240,22 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) if (IS_GEN(dev_priv, 5)) dpfc_ctl |= params->fence_id; if (IS_GEN(dev_priv, 6)) { - I915_WRITE(SNB_DPFC_CTL_SA, - SNB_CPU_FENCE_ENABLE | - params->fence_id); - I915_WRITE(DPFC_CPU_FENCE_OFFSET, - params->crtc.fence_y_offset); + intel_de_write(dev_priv, SNB_DPFC_CTL_SA, + SNB_CPU_FENCE_ENABLE | params->fence_id); + intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, + params->crtc.fence_y_offset); } } else { if (IS_GEN(dev_priv, 6)) { - I915_WRITE(SNB_DPFC_CTL_SA, 0); - I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); + intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0); + intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0); } } - I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset); + intel_de_write(dev_priv, ILK_DPFC_FENCE_YOFF, + params->crtc.fence_y_offset); /* enable it... */ - I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); + intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); intel_fbc_recompress(dev_priv); } @@ -262,16 +265,16 @@ static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv) u32 dpfc_ctl; /* Disable compression */ - dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); + dpfc_ctl = intel_de_read(dev_priv, ILK_DPFC_CONTROL); if (dpfc_ctl & DPFC_CTL_EN) { dpfc_ctl &= ~DPFC_CTL_EN; - I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); + intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl); } } static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv) { - return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; + return intel_de_read(dev_priv, ILK_DPFC_CONTROL) & DPFC_CTL_EN; } static void gen7_fbc_activate(struct drm_i915_private *dev_priv) @@ -282,14 +285,14 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) /* Display WA #0529: skl, kbl, bxt. */ if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) { - u32 val = I915_READ(CHICKEN_MISC_4); + u32 val = intel_de_read(dev_priv, CHICKEN_MISC_4); val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); if (params->gen9_wa_cfb_stride) val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride; - I915_WRITE(CHICKEN_MISC_4, val); + intel_de_write(dev_priv, CHICKEN_MISC_4, val); } dpfc_ctl = 0; @@ -314,13 +317,13 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) if (params->fence_id >= 0) { dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; - I915_WRITE(SNB_DPFC_CTL_SA, - SNB_CPU_FENCE_ENABLE | - params->fence_id); - I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset); - } else { - I915_WRITE(SNB_DPFC_CTL_SA,0); - I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); + intel_de_write(dev_priv, SNB_DPFC_CTL_SA, + SNB_CPU_FENCE_ENABLE | params->fence_id); + intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, + params->crtc.fence_y_offset); + } else if (dev_priv->ggtt.num_fences) { + intel_de_write(dev_priv, SNB_DPFC_CTL_SA, 0); + intel_de_write(dev_priv, DPFC_CPU_FENCE_OFFSET, 0); } if (dev_priv->fbc.false_color) @@ -328,21 +331,20 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) if (IS_IVYBRIDGE(dev_priv)) { /* WaFbcAsynchFlipDisableFbcQueue:ivb */ - I915_WRITE(ILK_DISPLAY_CHICKEN1, - I915_READ(ILK_DISPLAY_CHICKEN1) | - ILK_FBCQ_DIS); + intel_de_write(dev_priv, ILK_DISPLAY_CHICKEN1, + intel_de_read(dev_priv, ILK_DISPLAY_CHICKEN1) | ILK_FBCQ_DIS); } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ - I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe), - I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) | - HSW_FBCQ_DIS); + intel_de_write(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe), + intel_de_read(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe)) | HSW_FBCQ_DIS); } if (INTEL_GEN(dev_priv) >= 11) /* Wa_1409120013:icl,ehl,tgl */ - I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); + intel_de_write(dev_priv, ILK_DPFC_CHICKEN, + ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL); - I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); + intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); intel_fbc_recompress(dev_priv); } @@ -361,6 +363,8 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; + trace_intel_fbc_activate(fbc->crtc); + fbc->active = true; fbc->activated = true; @@ -378,6 +382,8 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; + trace_intel_fbc_deactivate(fbc->crtc); + fbc->active = false; if (INTEL_GEN(dev_priv) >= 5) @@ -407,7 +413,7 @@ static void intel_fbc_deactivate(struct drm_i915_private *dev_priv, { struct intel_fbc *fbc = &dev_priv->fbc; - WARN_ON(!mutex_is_locked(&fbc->lock)); + drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); if (fbc->active) intel_fbc_hw_deactivate(dev_priv); @@ -471,7 +477,8 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, struct drm_mm_node *uninitialized_var(compressed_llb); int ret; - WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb)); + drm_WARN_ON(&dev_priv->drm, + drm_mm_node_allocated(&fbc->compressed_fb)); ret = find_compression_threshold(dev_priv, &fbc->compressed_fb, size, fb_cpp); @@ -485,9 +492,11 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, fbc->threshold = ret; if (INTEL_GEN(dev_priv) >= 5) - I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start); + intel_de_write(dev_priv, ILK_DPFC_CB_BASE, + fbc->compressed_fb.start); else if (IS_GM45(dev_priv)) { - I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start); + intel_de_write(dev_priv, DPFC_CB_BASE, + fbc->compressed_fb.start); } else { compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL); if (!compressed_llb) @@ -500,16 +509,16 @@ static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv, fbc->compressed_llb = compressed_llb; - GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start, - fbc->compressed_fb.start, - U32_MAX)); - GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start, - fbc->compressed_llb->start, - U32_MAX)); - I915_WRITE(FBC_CFB_BASE, - dev_priv->dsm.start + fbc->compressed_fb.start); - I915_WRITE(FBC_LL_BASE, - dev_priv->dsm.start + compressed_llb->start); + GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start, + fbc->compressed_fb.start, + U32_MAX)); + GEM_BUG_ON(range_overflows_end_t(u64, dev_priv->dsm.start, + fbc->compressed_llb->start, + U32_MAX)); + intel_de_write(dev_priv, FBC_CFB_BASE, + dev_priv->dsm.start + fbc->compressed_fb.start); + intel_de_write(dev_priv, FBC_LL_BASE, + dev_priv->dsm.start + compressed_llb->start); } DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n", @@ -530,20 +539,22 @@ static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; - if (drm_mm_node_allocated(&fbc->compressed_fb)) - i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); + if (!drm_mm_node_allocated(&fbc->compressed_fb)) + return; if (fbc->compressed_llb) { i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb); kfree(fbc->compressed_llb); } + + i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb); } void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; - if (!fbc_supported(dev_priv)) + if (!HAS_FBC(dev_priv)) return; mutex_lock(&fbc->lock); @@ -555,7 +566,7 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, unsigned int stride) { /* This should have been caught earlier. */ - if (WARN_ON_ONCE((stride & (64 - 1)) != 0)) + if (drm_WARN_ON_ONCE(&dev_priv->drm, (stride & (64 - 1)) != 0)) return false; /* Below are the additional FBC restrictions. */ @@ -663,8 +674,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc, cache->fb.format = fb->format; cache->fb.stride = fb->pitches[0]; - WARN_ON(plane_state->flags & PLANE_HAS_FENCE && - !plane_state->vma->fence); + drm_WARN_ON(&dev_priv->drm, plane_state->flags & PLANE_HAS_FENCE && + !plane_state->vma->fence); if (plane_state->flags & PLANE_HAS_FENCE && plane_state->vma->fence) @@ -681,12 +692,37 @@ static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv) fbc->compressed_fb.size * fbc->threshold; } +static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) +{ + struct intel_fbc *fbc = &dev_priv->fbc; + + if (intel_vgpu_active(dev_priv)) { + fbc->no_fbc_reason = "VGPU is active"; + return false; + } + + if (!i915_modparams.enable_fbc) { + fbc->no_fbc_reason = "disabled per module param or by default"; + return false; + } + + if (fbc->underrun_detected) { + fbc->no_fbc_reason = "underrun detected"; + return false; + } + + return true; +} + static bool intel_fbc_can_activate(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; + if (!intel_fbc_can_enable(dev_priv)) + return false; + if (!cache->plane.visible) { fbc->no_fbc_reason = "primary plane not visible"; return false; @@ -785,28 +821,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return true; } -static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv) -{ - struct intel_fbc *fbc = &dev_priv->fbc; - - if (intel_vgpu_active(dev_priv)) { - fbc->no_fbc_reason = "VGPU is active"; - return false; - } - - if (!i915_modparams.enable_fbc) { - fbc->no_fbc_reason = "disabled per module param or by default"; - return false; - } - - if (fbc->underrun_detected) { - fbc->no_fbc_reason = "underrun detected"; - return false; - } - - return true; -} - static void intel_fbc_get_reg_params(struct intel_crtc *crtc, struct intel_fbc_reg_params *params) { @@ -867,16 +881,20 @@ static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state) return true; } -bool intel_fbc_pre_update(struct intel_crtc *crtc, - const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +bool intel_fbc_pre_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_plane_state *plane_state = + intel_atomic_get_new_plane_state(state, plane); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; const char *reason = "update pending"; bool need_vblank_wait = false; - if (!fbc_supported(dev_priv)) + if (!plane->has_fbc || !plane_state) return need_vblank_wait; mutex_lock(&fbc->lock); @@ -926,9 +944,9 @@ static void __intel_fbc_disable(struct drm_i915_private *dev_priv) struct intel_fbc *fbc = &dev_priv->fbc; struct intel_crtc *crtc = fbc->crtc; - WARN_ON(!mutex_is_locked(&fbc->lock)); - WARN_ON(!fbc->crtc); - WARN_ON(fbc->active); + drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); + drm_WARN_ON(&dev_priv->drm, !fbc->crtc); + drm_WARN_ON(&dev_priv->drm, fbc->active); DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe)); @@ -942,7 +960,7 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); struct intel_fbc *fbc = &dev_priv->fbc; - WARN_ON(!mutex_is_locked(&fbc->lock)); + drm_WARN_ON(&dev_priv->drm, !mutex_is_locked(&fbc->lock)); if (fbc->crtc != crtc) return; @@ -967,12 +985,16 @@ static void __intel_fbc_post_update(struct intel_crtc *crtc) intel_fbc_deactivate(dev_priv, "frontbuffer write"); } -void intel_fbc_post_update(struct intel_crtc *crtc) +void intel_fbc_post_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + const struct intel_plane_state *plane_state = + intel_atomic_get_new_plane_state(state, plane); struct intel_fbc *fbc = &dev_priv->fbc; - if (!fbc_supported(dev_priv)) + if (!plane->has_fbc || !plane_state) return; mutex_lock(&fbc->lock); @@ -994,7 +1016,7 @@ void intel_fbc_invalidate(struct drm_i915_private *dev_priv, { struct intel_fbc *fbc = &dev_priv->fbc; - if (!fbc_supported(dev_priv)) + if (!HAS_FBC(dev_priv)) return; if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP) @@ -1015,7 +1037,7 @@ void intel_fbc_flush(struct drm_i915_private *dev_priv, { struct intel_fbc *fbc = &dev_priv->fbc; - if (!fbc_supported(dev_priv)) + if (!HAS_FBC(dev_priv)) return; mutex_lock(&fbc->lock); @@ -1099,24 +1121,26 @@ out: /** * intel_fbc_enable: tries to enable FBC on the CRTC * @crtc: the CRTC - * @crtc_state: corresponding &drm_crtc_state for @crtc - * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc + * @state: corresponding &drm_crtc_state for @crtc * * This function checks if the given CRTC was chosen for FBC, then enables it if * possible. Notice that it doesn't activate FBC. It is valid to call * intel_fbc_enable multiple times for the same pipe without an * intel_fbc_disable in the middle, as long as it is deactivated. */ -void intel_fbc_enable(struct intel_crtc *crtc, - const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state) +void intel_fbc_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + const struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + const struct intel_plane_state *plane_state = + intel_atomic_get_new_plane_state(state, plane); struct intel_fbc *fbc = &dev_priv->fbc; struct intel_fbc_state_cache *cache = &fbc->state_cache; - const struct drm_framebuffer *fb = plane_state->hw.fb; - if (!fbc_supported(dev_priv)) + if (!plane->has_fbc || !plane_state) return; mutex_lock(&fbc->lock); @@ -1129,7 +1153,7 @@ void intel_fbc_enable(struct intel_crtc *crtc, __intel_fbc_disable(dev_priv); } - WARN_ON(fbc->active); + drm_WARN_ON(&dev_priv->drm, fbc->active); intel_fbc_update_state_cache(crtc, crtc_state, plane_state); @@ -1139,14 +1163,14 @@ void intel_fbc_enable(struct intel_crtc *crtc, if (intel_fbc_alloc_cfb(dev_priv, intel_fbc_calculate_cfb_size(dev_priv, cache), - fb->format->cpp[0])) { + plane_state->hw.fb->format->cpp[0])) { cache->plane.visible = false; fbc->no_fbc_reason = "not enough stolen memory"; goto out; } if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) && - fb->modifier != I915_FORMAT_MOD_X_TILED) + plane_state->hw.fb->modifier != I915_FORMAT_MOD_X_TILED) cache->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8; else @@ -1169,9 +1193,10 @@ out: void intel_fbc_disable(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_plane *plane = to_intel_plane(crtc->base.primary); struct intel_fbc *fbc = &dev_priv->fbc; - if (!fbc_supported(dev_priv)) + if (!plane->has_fbc) return; mutex_lock(&fbc->lock); @@ -1190,12 +1215,12 @@ void intel_fbc_global_disable(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; - if (!fbc_supported(dev_priv)) + if (!HAS_FBC(dev_priv)) return; mutex_lock(&fbc->lock); if (fbc->crtc) { - WARN_ON(fbc->crtc->active); + drm_WARN_ON(&dev_priv->drm, fbc->crtc->active); __intel_fbc_disable(dev_priv); } mutex_unlock(&fbc->lock); @@ -1267,7 +1292,7 @@ void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv) { struct intel_fbc *fbc = &dev_priv->fbc; - if (!fbc_supported(dev_priv)) + if (!HAS_FBC(dev_priv)) return; /* There's no guarantee that underrun_detected won't be set to true @@ -1348,7 +1373,8 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) /* This value was pulled out of someone's hat */ if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) - I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); + intel_de_write(dev_priv, FBC_CONTROL, + 500 << FBC_CTL_INTERVAL_SHIFT); /* We still don't have any sort of hardware state readout for FBC, so * deactivate it in case the BIOS activated it to make sure software diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h index c8a5e5098687..6dc1edefe81b 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.h +++ b/drivers/gpu/drm/i915/display/intel_fbc.h @@ -19,14 +19,13 @@ struct intel_plane_state; void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv, struct intel_atomic_state *state); bool intel_fbc_is_active(struct drm_i915_private *dev_priv); -bool intel_fbc_pre_update(struct intel_crtc *crtc, - const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state); -void intel_fbc_post_update(struct intel_crtc *crtc); +bool intel_fbc_pre_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); +void intel_fbc_post_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_fbc_init(struct drm_i915_private *dev_priv); -void intel_fbc_enable(struct intel_crtc *crtc, - const struct intel_crtc_state *crtc_state, - const struct intel_plane_state *plane_state); +void intel_fbc_enable(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_fbc_disable(struct intel_crtc *crtc); void intel_fbc_global_disable(struct drm_i915_private *dev_priv); void intel_fbc_invalidate(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 1e98e432c9fa..3bc804212a99 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -40,7 +40,6 @@ #include <drm/drm_crtc.h> #include <drm/drm_fb_helper.h> #include <drm/drm_fourcc.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "intel_display_types.h" @@ -191,7 +190,7 @@ static int intelfb_create(struct drm_fb_helper *helper, drm_framebuffer_put(&intel_fb->base); intel_fb = ifbdev->fb = NULL; } - if (!intel_fb || WARN_ON(!intel_fb_obj(&intel_fb->base))) { + if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(&intel_fb->base))) { DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n"); ret = intelfb_alloc(helper, sizes); if (ret) @@ -410,9 +409,9 @@ static bool intel_fbdev_init_bios(struct drm_device *dev, if (!crtc->state->active) continue; - WARN(!crtc->primary->state->fb, - "re-used BIOS config but lost an fb on crtc %d\n", - crtc->base.id); + drm_WARN(dev, !crtc->primary->state->fb, + "re-used BIOS config but lost an fb on crtc %d\n", + crtc->base.id); } @@ -439,7 +438,8 @@ int intel_fbdev_init(struct drm_device *dev) struct intel_fbdev *ifbdev; int ret; - if (WARN_ON(!HAS_DISPLAY(dev_priv) || !INTEL_DISPLAY_ENABLED(dev_priv))) + if (drm_WARN_ON(dev, !HAS_DISPLAY(dev_priv) || + !INTEL_DISPLAY_ENABLED(dev_priv))) return -ENODEV; ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); @@ -452,7 +452,7 @@ int intel_fbdev_init(struct drm_device *dev) if (!intel_fbdev_init_bios(dev, ifbdev)) ifbdev->preferred_bpp = 32; - ret = drm_fb_helper_init(dev, &ifbdev->helper, 4); + ret = drm_fb_helper_init(dev, &ifbdev->helper); if (ret) { kfree(ifbdev); return ret; @@ -461,8 +461,6 @@ int intel_fbdev_init(struct drm_device *dev) dev_priv->fbdev = ifbdev; INIT_WORK(&dev_priv->fbdev_suspend_work, intel_fbdev_suspend_worker); - drm_fb_helper_single_add_all_connectors(&ifbdev->helper); - return 0; } @@ -569,7 +567,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous * to all the printk activity. Try to keep it out of the hot * path of resume if possible. */ - WARN_ON(state != FBINFO_STATE_RUNNING); + drm_WARN_ON(dev, state != FBINFO_STATE_RUNNING); if (!console_trylock()) { /* Don't block our own workqueue as this can * be run in parallel with other i915.ko tasks. diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index 6c83b350525d..813a4f7033e1 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -95,15 +95,15 @@ static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) lockdep_assert_held(&dev_priv->irq_lock); - if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) + if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) return; enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); - I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); + intel_de_posting_read(dev_priv, reg); trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); - DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); + drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); } static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, @@ -118,11 +118,13 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, if (enable) { u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); - I915_WRITE(reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, + enable_mask | PIPE_FIFO_UNDERRUN_STATUS); + intel_de_posting_read(dev_priv, reg); } else { - if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) - DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); + if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) + drm_err(&dev_priv->drm, "pipe %c underrun\n", + pipe_name(pipe)); } } @@ -143,18 +145,18 @@ static void ivb_check_fifo_underruns(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - u32 err_int = I915_READ(GEN7_ERR_INT); + u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); lockdep_assert_held(&dev_priv->irq_lock); if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) return; - I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); - POSTING_READ(GEN7_ERR_INT); + intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); + intel_de_posting_read(dev_priv, GEN7_ERR_INT); trace_intel_cpu_fifo_underrun(dev_priv, pipe); - DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe)); + drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); } static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, @@ -163,7 +165,8 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, { struct drm_i915_private *dev_priv = to_i915(dev); if (enable) { - I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); + intel_de_write(dev_priv, GEN7_ERR_INT, + ERR_INT_FIFO_UNDERRUN(pipe)); if (!ivb_can_enable_err_int(dev)) return; @@ -173,9 +176,10 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev, ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB); if (old && - I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { - DRM_ERROR("uncleared fifo underrun on pipe %c\n", - pipe_name(pipe)); + intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { + drm_err(&dev_priv->drm, + "uncleared fifo underrun on pipe %c\n", + pipe_name(pipe)); } } } @@ -209,19 +213,20 @@ static void cpt_check_pch_fifo_underruns(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pch_transcoder = crtc->pipe; - u32 serr_int = I915_READ(SERR_INT); + u32 serr_int = intel_de_read(dev_priv, SERR_INT); lockdep_assert_held(&dev_priv->irq_lock); if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) return; - I915_WRITE(SERR_INT, SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); - POSTING_READ(SERR_INT); + intel_de_write(dev_priv, SERR_INT, + SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); + intel_de_posting_read(dev_priv, SERR_INT); trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); - DRM_ERROR("pch fifo underrun on pch transcoder %c\n", - pipe_name(pch_transcoder)); + drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n", + pipe_name(pch_transcoder)); } static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, @@ -231,8 +236,8 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, struct drm_i915_private *dev_priv = to_i915(dev); if (enable) { - I915_WRITE(SERR_INT, - SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); + intel_de_write(dev_priv, SERR_INT, + SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); if (!cpt_can_enable_serr_int(dev)) return; @@ -241,10 +246,11 @@ static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, } else { ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); - if (old && I915_READ(SERR_INT) & + if (old && intel_de_read(dev_priv, SERR_INT) & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) { - DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", - pipe_name(pch_transcoder)); + drm_err(&dev_priv->drm, + "uncleared pch fifo underrun on pch transcoder %c\n", + pipe_name(pch_transcoder)); } } } @@ -378,8 +384,8 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { trace_intel_cpu_fifo_underrun(dev_priv, pipe); - DRM_ERROR("CPU pipe %c FIFO underrun\n", - pipe_name(pipe)); + drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", + pipe_name(pipe)); } intel_fbc_handle_fifo_underrun_irq(dev_priv); @@ -400,8 +406,8 @@ void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, false)) { trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder); - DRM_ERROR("PCH transcoder %c FIFO underrun\n", - pipe_name(pch_transcoder)); + drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n", + pipe_name(pch_transcoder)); } } diff --git a/drivers/gpu/drm/i915/display/intel_global_state.c b/drivers/gpu/drm/i915/display/intel_global_state.c new file mode 100644 index 000000000000..a0cc894c3868 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_global_state.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2020 Intel Corporation + */ + +#include <linux/string.h> + +#include "i915_drv.h" +#include "intel_atomic.h" +#include "intel_display_types.h" +#include "intel_global_state.h" + +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, + struct intel_global_obj *obj, + struct intel_global_state *state, + const struct intel_global_state_funcs *funcs) +{ + memset(obj, 0, sizeof(*obj)); + + obj->state = state; + obj->funcs = funcs; + list_add_tail(&obj->head, &dev_priv->global_obj_list); +} + +void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv) +{ + struct intel_global_obj *obj, *next; + + list_for_each_entry_safe(obj, next, &dev_priv->global_obj_list, head) { + list_del(&obj->head); + obj->funcs->atomic_destroy_state(obj, obj->state); + } +} + +static void assert_global_state_write_locked(struct drm_i915_private *dev_priv) +{ + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) + drm_modeset_lock_assert_held(&crtc->base.mutex); +} + +static bool modeset_lock_is_held(struct drm_modeset_acquire_ctx *ctx, + struct drm_modeset_lock *lock) +{ + struct drm_modeset_lock *l; + + list_for_each_entry(l, &ctx->locked, head) { + if (lock == l) + return true; + } + + return false; +} + +static void assert_global_state_read_locked(struct intel_atomic_state *state) +{ + struct drm_modeset_acquire_ctx *ctx = state->base.acquire_ctx; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + if (modeset_lock_is_held(ctx, &crtc->base.mutex)) + return; + } + + WARN(1, "Global state not read locked\n"); +} + +struct intel_global_state * +intel_atomic_get_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj) +{ + int index, num_objs, i; + size_t size; + struct __intel_global_objs_state *arr; + struct intel_global_state *obj_state; + + for (i = 0; i < state->num_global_objs; i++) + if (obj == state->global_objs[i].ptr) + return state->global_objs[i].state; + + assert_global_state_read_locked(state); + + num_objs = state->num_global_objs + 1; + size = sizeof(*state->global_objs) * num_objs; + arr = krealloc(state->global_objs, size, GFP_KERNEL); + if (!arr) + return ERR_PTR(-ENOMEM); + + state->global_objs = arr; + index = state->num_global_objs; + memset(&state->global_objs[index], 0, sizeof(*state->global_objs)); + + obj_state = obj->funcs->atomic_duplicate_state(obj); + if (!obj_state) + return ERR_PTR(-ENOMEM); + + obj_state->changed = false; + + state->global_objs[index].state = obj_state; + state->global_objs[index].old_state = obj->state; + state->global_objs[index].new_state = obj_state; + state->global_objs[index].ptr = obj; + obj_state->state = state; + + state->num_global_objs = num_objs; + + DRM_DEBUG_ATOMIC("Added new global object %p state %p to %p\n", + obj, obj_state, state); + + return obj_state; +} + +struct intel_global_state * +intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj) +{ + int i; + + for (i = 0; i < state->num_global_objs; i++) + if (obj == state->global_objs[i].ptr) + return state->global_objs[i].old_state; + + return NULL; +} + +struct intel_global_state * +intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj) +{ + int i; + + for (i = 0; i < state->num_global_objs; i++) + if (obj == state->global_objs[i].ptr) + return state->global_objs[i].new_state; + + return NULL; +} + +void intel_atomic_swap_global_state(struct intel_atomic_state *state) +{ + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_global_state *old_obj_state, *new_obj_state; + struct intel_global_obj *obj; + int i; + + for_each_oldnew_global_obj_in_state(state, obj, old_obj_state, + new_obj_state, i) { + WARN_ON(obj->state != old_obj_state); + + /* + * If the new state wasn't modified (and properly + * locked for write access) we throw it away. + */ + if (!new_obj_state->changed) + continue; + + assert_global_state_write_locked(dev_priv); + + old_obj_state->state = state; + new_obj_state->state = NULL; + + state->global_objs[i].state = old_obj_state; + obj->state = new_obj_state; + } +} + +void intel_atomic_clear_global_state(struct intel_atomic_state *state) +{ + int i; + + for (i = 0; i < state->num_global_objs; i++) { + struct intel_global_obj *obj = state->global_objs[i].ptr; + + obj->funcs->atomic_destroy_state(obj, + state->global_objs[i].state); + state->global_objs[i].ptr = NULL; + state->global_objs[i].state = NULL; + state->global_objs[i].old_state = NULL; + state->global_objs[i].new_state = NULL; + } + state->num_global_objs = 0; +} + +int intel_atomic_lock_global_state(struct intel_global_state *obj_state) +{ + struct intel_atomic_state *state = obj_state->state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + int ret; + + ret = drm_modeset_lock(&crtc->base.mutex, + state->base.acquire_ctx); + if (ret) + return ret; + } + + obj_state->changed = true; + + return 0; +} + +int intel_atomic_serialize_global_state(struct intel_global_state *obj_state) +{ + struct intel_atomic_state *state = obj_state->state; + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc *crtc; + + for_each_intel_crtc(&dev_priv->drm, crtc) { + struct intel_crtc_state *crtc_state; + + crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + } + + obj_state->changed = true; + + return 0; +} diff --git a/drivers/gpu/drm/i915/display/intel_global_state.h b/drivers/gpu/drm/i915/display/intel_global_state.h new file mode 100644 index 000000000000..e6163a469029 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_global_state.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef __INTEL_GLOBAL_STATE_H__ +#define __INTEL_GLOBAL_STATE_H__ + +#include <linux/list.h> + +struct drm_i915_private; +struct intel_atomic_state; +struct intel_global_obj; +struct intel_global_state; + +struct intel_global_state_funcs { + struct intel_global_state *(*atomic_duplicate_state)(struct intel_global_obj *obj); + void (*atomic_destroy_state)(struct intel_global_obj *obj, + struct intel_global_state *state); +}; + +struct intel_global_obj { + struct list_head head; + struct intel_global_state *state; + const struct intel_global_state_funcs *funcs; +}; + +#define intel_for_each_global_obj(obj, dev_priv) \ + list_for_each_entry(obj, &(dev_priv)->global_obj_list, head) + +#define for_each_new_global_obj_in_state(__state, obj, new_obj_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->num_global_objs && \ + ((obj) = (__state)->global_objs[__i].ptr, \ + (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \ + (__i)++) \ + for_each_if(obj) + +#define for_each_old_global_obj_in_state(__state, obj, new_obj_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->num_global_objs && \ + ((obj) = (__state)->global_objs[__i].ptr, \ + (new_obj_state) = (__state)->global_objs[__i].old_state, 1); \ + (__i)++) \ + for_each_if(obj) + +#define for_each_oldnew_global_obj_in_state(__state, obj, old_obj_state, new_obj_state, __i) \ + for ((__i) = 0; \ + (__i) < (__state)->num_global_objs && \ + ((obj) = (__state)->global_objs[__i].ptr, \ + (old_obj_state) = (__state)->global_objs[__i].old_state, \ + (new_obj_state) = (__state)->global_objs[__i].new_state, 1); \ + (__i)++) \ + for_each_if(obj) + +struct intel_global_state { + struct intel_atomic_state *state; + bool changed; +}; + +struct __intel_global_objs_state { + struct intel_global_obj *ptr; + struct intel_global_state *state, *old_state, *new_state; +}; + +void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, + struct intel_global_obj *obj, + struct intel_global_state *state, + const struct intel_global_state_funcs *funcs); +void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv); + +struct intel_global_state * +intel_atomic_get_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj); +struct intel_global_state * +intel_atomic_get_old_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj); +struct intel_global_state * +intel_atomic_get_new_global_obj_state(struct intel_atomic_state *state, + struct intel_global_obj *obj); + +void intel_atomic_swap_global_state(struct intel_atomic_state *state); +void intel_atomic_clear_global_state(struct intel_atomic_state *state); +int intel_atomic_lock_global_state(struct intel_global_state *obj_state); +int intel_atomic_serialize_global_state(struct intel_global_state *obj_state); + +#endif diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 3d4d19ac1d14..1fd3a5a6296b 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -32,7 +32,6 @@ #include <linux/i2c.h> #include <drm/drm_hdcp.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "intel_display_types.h" @@ -143,8 +142,8 @@ to_intel_gmbus(struct i2c_adapter *i2c) void intel_gmbus_reset(struct drm_i915_private *dev_priv) { - I915_WRITE(GMBUS0, 0); - I915_WRITE(GMBUS4, 0); + intel_de_write(dev_priv, GMBUS0, 0); + intel_de_write(dev_priv, GMBUS4, 0); } static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -153,12 +152,12 @@ static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, u32 val; /* When using bit bashing for I2C, this bit needs to be set to 1 */ - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); if (!enable) val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -166,12 +165,12 @@ static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(SOUTH_DSPCLK_GATE_D); + val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); if (!enable) val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; else val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(SOUTH_DSPCLK_GATE_D, val); + intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); } static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, @@ -179,12 +178,12 @@ static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(GEN9_CLKGATE_DIS_4); + val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); if (!enable) val |= BXT_GMBUS_GATING_DIS; else val &= ~BXT_GMBUS_GATING_DIS; - I915_WRITE(GEN9_CLKGATE_DIS_4, val); + intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); } static u32 get_reserved(struct intel_gmbus *bus) @@ -337,14 +336,16 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) irq_en = 0; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_en); + intel_de_write_fw(dev_priv, GMBUS4, irq_en); status |= GMBUS_SATOER; - ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); + ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 2); if (ret) - ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); + ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, + 50); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); if (gmbus2 & GMBUS_SATOER) @@ -366,13 +367,13 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) irq_enable = GMBUS_IDLE_EN; add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); - I915_WRITE_FW(GMBUS4, irq_enable); + intel_de_write_fw(dev_priv, GMBUS4, irq_enable); ret = intel_wait_for_register_fw(&dev_priv->uncore, GMBUS2, GMBUS_ACTIVE, 0, 10); - I915_WRITE_FW(GMBUS4, 0); + intel_de_write_fw(dev_priv, GMBUS4, 0); remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); return ret; @@ -404,15 +405,12 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, len++; } size = len % 256 + 256; - I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); + intel_de_write_fw(dev_priv, GMBUS0, + gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); } - I915_WRITE_FW(GMBUS1, - gmbus1_index | - GMBUS_CYCLE_WAIT | - (size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_READ | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); while (len) { int ret; u32 val, loop = 0; @@ -421,7 +419,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (ret) return ret; - val = I915_READ_FW(GMBUS3); + val = intel_de_read_fw(dev_priv, GMBUS3); do { if (extra_byte_added && len == 1) break; @@ -432,7 +430,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, if (burst_read && len == size - 4) /* Reset the override bit */ - I915_WRITE_FW(GMBUS0, gmbus0_reg); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); } return 0; @@ -489,12 +487,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, len -= 1; } - I915_WRITE_FW(GMBUS3, val); - I915_WRITE_FW(GMBUS1, - gmbus1_index | GMBUS_CYCLE_WAIT | - (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | - (addr << GMBUS_SLAVE_ADDR_SHIFT) | - GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS1, + gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); while (len) { int ret; @@ -503,7 +498,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, val |= *buf++ << (8 * loop); } while (--len && ++loop < 4); - I915_WRITE_FW(GMBUS3, val); + intel_de_write_fw(dev_priv, GMBUS3, val); ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); if (ret) @@ -568,7 +563,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* GMBUS5 holds 16-bit index */ if (gmbus5) - I915_WRITE_FW(GMBUS5, gmbus5); + intel_de_write_fw(dev_priv, GMBUS5, gmbus5); if (msgs[1].flags & I2C_M_RD) ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, @@ -578,7 +573,7 @@ gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, /* Clear GMBUS5 after each index transfer */ if (gmbus5) - I915_WRITE_FW(GMBUS5, 0); + intel_de_write_fw(dev_priv, GMBUS5, 0); return ret; } @@ -601,7 +596,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, pch_gmbus_clock_gating(dev_priv, false); retry: - I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0); + intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); for (; i < num; i += inc) { inc = 1; @@ -629,18 +624,19 @@ retry: * a STOP on the very first cycle. To simplify the code we * unconditionally generate the STOP condition with an additional gmbus * cycle. */ - I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); /* Mark the GMBUS interface as disabled after waiting for idle. * We will re-enable it at the start of the next xfer, * till then let it sleep. */ if (gmbus_wait_idle(dev_priv)) { - DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n", - adapter->name); + drm_dbg_kms(&dev_priv->drm, + "GMBUS [%s] timed out waiting for idle\n", + adapter->name); ret = -ETIMEDOUT; } - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); ret = ret ?: i; goto out; @@ -660,8 +656,9 @@ clear_err: */ ret = -ENXIO; if (gmbus_wait_idle(dev_priv)) { - DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", - adapter->name); + drm_dbg_kms(&dev_priv->drm, + "GMBUS [%s] timed out after NAK\n", + adapter->name); ret = -ETIMEDOUT; } @@ -669,13 +666,13 @@ clear_err: * of resetting the GMBUS controller and so clearing the * BUS_ERROR raised by the slave's NAK. */ - I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT); - I915_WRITE_FW(GMBUS1, 0); - I915_WRITE_FW(GMBUS0, 0); + intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); + intel_de_write_fw(dev_priv, GMBUS1, 0); + intel_de_write_fw(dev_priv, GMBUS0, 0); - DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n", - adapter->name, msgs[i].addr, - (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); + drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", + adapter->name, msgs[i].addr, + (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); /* * Passive adapters sometimes NAK the first probe. Retry the first @@ -684,17 +681,19 @@ clear_err: * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. */ if (ret == -ENXIO && i == 0 && try++ == 0) { - DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n", - adapter->name); + drm_dbg_kms(&dev_priv->drm, + "GMBUS [%s] NAK on first message, retry\n", + adapter->name); goto retry; } goto out; timeout: - DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n", - bus->adapter.name, bus->reg0 & 0xff); - I915_WRITE_FW(GMBUS0, 0); + drm_dbg_kms(&dev_priv->drm, + "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", + bus->adapter.name, bus->reg0 & 0xff); + intel_de_write_fw(dev_priv, GMBUS0, 0); /* * Hardware may not support GMBUS over these pins? Try GPIO bitbanging @@ -908,7 +907,8 @@ err: struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin) { - if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))) + if (drm_WARN_ON(&dev_priv->drm, + !intel_gmbus_is_valid_pin(dev_priv, pin))) return NULL; return &dev_priv->gmbus[pin].adapter; @@ -929,9 +929,10 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) mutex_lock(&dev_priv->gmbus_mutex); bus->force_bit += force_bit ? 1 : -1; - DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n", - force_bit ? "en" : "dis", adapter->name, - bus->force_bit); + drm_dbg_kms(&dev_priv->drm, + "%sabling bit-banging on %s. force bit now %d\n", + force_bit ? "en" : "dis", adapter->name, + bus->force_bit); mutex_unlock(&dev_priv->gmbus_mutex); } diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 0fdbd39f6641..ee0f27ea2810 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -43,6 +43,7 @@ static int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, const struct intel_hdcp_shim *shim, u8 *bksv) { + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); int ret, i, tries = 2; /* HDCP spec states that we must retry the bksv if it is invalid */ @@ -54,7 +55,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, break; } if (i == tries) { - DRM_DEBUG_KMS("Bksv is invalid\n"); + drm_dbg_kms(&i915->drm, "Bksv is invalid\n"); return -ENODEV; } @@ -64,7 +65,7 @@ int intel_hdcp_read_valid_bksv(struct intel_digital_port *intel_dig_port, /* Is HDCP1.4 capable on Platform and Sink */ bool intel_hdcp_capable(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); const struct intel_hdcp_shim *shim = connector->hdcp.shim; bool capable = false; u8 bksv[5]; @@ -85,8 +86,8 @@ bool intel_hdcp_capable(struct intel_connector *connector) /* Is HDCP2.2 capable on Platform and Sink */ bool intel_hdcp2_capable(struct intel_connector *connector) { + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; bool capable = false; @@ -112,7 +113,8 @@ static inline bool intel_hdcp_in_use(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder, enum port port) { - return I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) & + return intel_de_read(dev_priv, + HDCP_STATUS(dev_priv, cpu_transcoder, port)) & HDCP_STATUS_ENC; } @@ -120,7 +122,8 @@ static inline bool intel_hdcp2_in_use(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder, enum port port) { - return I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & + return intel_de_read(dev_priv, + HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & LINK_ENCRYPTION_STATUS; } @@ -184,9 +187,9 @@ static bool hdcp_key_loadable(struct drm_i915_private *dev_priv) static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv) { - I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); - I915_WRITE(HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | - HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); + intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); + intel_de_write(dev_priv, HDCP_KEY_STATUS, + HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); } static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) @@ -194,7 +197,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) int ret; u32 val; - val = I915_READ(HDCP_KEY_STATUS); + val = intel_de_read(dev_priv, HDCP_KEY_STATUS); if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) return 0; @@ -203,7 +206,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) * out of reset. So if Key is not already loaded, its an error state. */ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) - if (!(I915_READ(HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) + if (!(intel_de_read(dev_priv, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) return -ENXIO; /* @@ -217,12 +220,13 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_LOAD_HDCP_KEYS, 1); if (ret) { - DRM_ERROR("Failed to initiate HDCP key load (%d)\n", - ret); + drm_err(&dev_priv->drm, + "Failed to initiate HDCP key load (%d)\n", + ret); return ret; } } else { - I915_WRITE(HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); + intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); } /* Wait for the keys to load (500us) */ @@ -235,7 +239,7 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) return -ENXIO; /* Send Aksv over to PCH display for use in authentication */ - I915_WRITE(HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); + intel_de_write(dev_priv, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); return 0; } @@ -243,9 +247,9 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv) /* Returns updated SHA-1 index */ static int intel_write_sha_text(struct drm_i915_private *dev_priv, u32 sha_text) { - I915_WRITE(HDCP_SHA_TEXT, sha_text); + intel_de_write(dev_priv, HDCP_SHA_TEXT, sha_text); if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { - DRM_ERROR("Timed out waiting for SHA1 ready\n"); + drm_err(&dev_priv->drm, "Timed out waiting for SHA1 ready\n"); return -ETIMEDOUT; } return 0; @@ -270,7 +274,8 @@ u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv, return HDCP_TRANSD_REP_PRESENT | HDCP_TRANSD_SHA1_M0; default: - DRM_ERROR("Unknown transcoder %d\n", cpu_transcoder); + drm_err(&dev_priv->drm, "Unknown transcoder %d\n", + cpu_transcoder); return -EINVAL; } } @@ -287,7 +292,7 @@ u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *dev_priv, case PORT_E: return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; default: - DRM_ERROR("Unknown port %d\n", port); + drm_err(&dev_priv->drm, "Unknown port %d\n", port); return -EINVAL; } } @@ -297,21 +302,19 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, const struct intel_hdcp_shim *shim, u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); - struct drm_i915_private *dev_priv; + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; enum port port = intel_dig_port->base.port; u32 vprime, sha_text, sha_leftovers, rep_ctl; int ret, i, j, sha_idx; - dev_priv = intel_dig_port->base.base.dev->dev_private; - /* Process V' values from the receiver */ for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { ret = shim->read_v_prime_part(intel_dig_port, i, &vprime); if (ret) return ret; - I915_WRITE(HDCP_SHA_V_PRIME(i), vprime); + intel_de_write(dev_priv, HDCP_SHA_V_PRIME(i), vprime); } /* @@ -328,7 +331,7 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, sha_text = 0; sha_leftovers = 0; rep_ctl = intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port); - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); + intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); for (i = 0; i < num_downstream; i++) { unsigned int sha_empty; u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; @@ -345,7 +348,8 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, /* Programming guide writes this every 64 bytes */ sha_idx += sizeof(sha_text); if (!(sha_idx % 64)) - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_32); /* Store the leftover bytes from the ksv in sha_text */ sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; @@ -377,7 +381,8 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, */ if (sha_leftovers == 0) { /* Write 16 bits of text, 16 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_16); ret = intel_write_sha_text(dev_priv, bstatus[0] << 8 | bstatus[1]); if (ret < 0) @@ -385,14 +390,16 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, sha_idx += sizeof(sha_text); /* Write 32 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_0); ret = intel_write_sha_text(dev_priv, 0); if (ret < 0) return ret; sha_idx += sizeof(sha_text); /* Write 16 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_16); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_16); ret = intel_write_sha_text(dev_priv, 0); if (ret < 0) return ret; @@ -400,7 +407,8 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, } else if (sha_leftovers == 1) { /* Write 24 bits of text, 8 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_24); sha_text |= bstatus[0] << 16 | bstatus[1] << 8; /* Only 24-bits of data, must be in the LSB */ sha_text = (sha_text & 0xffffff00) >> 8; @@ -410,14 +418,16 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, sha_idx += sizeof(sha_text); /* Write 32 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_0); ret = intel_write_sha_text(dev_priv, 0); if (ret < 0) return ret; sha_idx += sizeof(sha_text); /* Write 24 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_8); ret = intel_write_sha_text(dev_priv, 0); if (ret < 0) return ret; @@ -425,7 +435,8 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, } else if (sha_leftovers == 2) { /* Write 32 bits of text */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_32); sha_text |= bstatus[0] << 24 | bstatus[1] << 16; ret = intel_write_sha_text(dev_priv, sha_text); if (ret < 0) @@ -433,7 +444,8 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, sha_idx += sizeof(sha_text); /* Write 64 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_0); for (i = 0; i < 2; i++) { ret = intel_write_sha_text(dev_priv, 0); if (ret < 0) @@ -442,7 +454,8 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, } } else if (sha_leftovers == 3) { /* Write 32 bits of text */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_32); sha_text |= bstatus[0] << 24; ret = intel_write_sha_text(dev_priv, sha_text); if (ret < 0) @@ -450,32 +463,35 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, sha_idx += sizeof(sha_text); /* Write 8 bits of text, 24 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_8); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_8); ret = intel_write_sha_text(dev_priv, bstatus[1]); if (ret < 0) return ret; sha_idx += sizeof(sha_text); /* Write 32 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_0); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_0); ret = intel_write_sha_text(dev_priv, 0); if (ret < 0) return ret; sha_idx += sizeof(sha_text); /* Write 8 bits of M0 */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_24); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_TEXT_24); ret = intel_write_sha_text(dev_priv, 0); if (ret < 0) return ret; sha_idx += sizeof(sha_text); } else { - DRM_DEBUG_KMS("Invalid number of leftovers %d\n", - sha_leftovers); + drm_dbg_kms(&dev_priv->drm, "Invalid number of leftovers %d\n", + sha_leftovers); return -EINVAL; } - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); + intel_de_write(dev_priv, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ while ((sha_idx % 64) < (64 - sizeof(sha_text))) { ret = intel_write_sha_text(dev_priv, 0); @@ -495,14 +511,15 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, return ret; /* Tell the HW we're done with the hash and wait for it to ACK */ - I915_WRITE(HDCP_REP_CTL, rep_ctl | HDCP_SHA1_COMPLETE_HASH); + intel_de_write(dev_priv, HDCP_REP_CTL, + rep_ctl | HDCP_SHA1_COMPLETE_HASH); if (intel_de_wait_for_set(dev_priv, HDCP_REP_CTL, HDCP_SHA1_COMPLETE, 1)) { - DRM_ERROR("Timed out waiting for SHA1 complete\n"); + drm_err(&dev_priv->drm, "Timed out waiting for SHA1 complete\n"); return -ETIMEDOUT; } - if (!(I915_READ(HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { - DRM_DEBUG_KMS("SHA-1 mismatch, HDCP failed\n"); + if (!(intel_de_read(dev_priv, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { + drm_dbg_kms(&dev_priv->drm, "SHA-1 mismatch, HDCP failed\n"); return -ENXIO; } @@ -513,15 +530,16 @@ int intel_hdcp_validate_v_prime(struct intel_connector *connector, static int intel_hdcp_auth_downstream(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); const struct intel_hdcp_shim *shim = connector->hdcp.shim; - struct drm_device *dev = connector->base.dev; u8 bstatus[2], num_downstream, *ksv_fifo; int ret, i, tries = 3; ret = intel_hdcp_poll_ksv_fifo(intel_dig_port, shim); if (ret) { - DRM_DEBUG_KMS("KSV list failed to become ready (%d)\n", ret); + drm_dbg_kms(&dev_priv->drm, + "KSV list failed to become ready (%d)\n", ret); return ret; } @@ -531,7 +549,7 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { - DRM_DEBUG_KMS("Max Topology Limit Exceeded\n"); + drm_dbg_kms(&dev_priv->drm, "Max Topology Limit Exceeded\n"); return -EPERM; } @@ -544,13 +562,14 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) */ num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); if (num_downstream == 0) { - DRM_DEBUG_KMS("Repeater with zero downstream devices\n"); + drm_dbg_kms(&dev_priv->drm, + "Repeater with zero downstream devices\n"); return -EINVAL; } ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); if (!ksv_fifo) { - DRM_DEBUG_KMS("Out of mem: ksv_fifo\n"); + drm_dbg_kms(&dev_priv->drm, "Out of mem: ksv_fifo\n"); return -ENOMEM; } @@ -558,8 +577,9 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) if (ret) goto err; - if (drm_hdcp_check_ksvs_revoked(dev, ksv_fifo, num_downstream)) { - DRM_ERROR("Revoked Ksv(s) in ksv_fifo\n"); + if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, ksv_fifo, + num_downstream)) { + drm_err(&dev_priv->drm, "Revoked Ksv(s) in ksv_fifo\n"); ret = -EPERM; goto err; } @@ -577,12 +597,13 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector) } if (i == tries) { - DRM_DEBUG_KMS("V Prime validation failed.(%d)\n", ret); + drm_dbg_kms(&dev_priv->drm, + "V Prime validation failed.(%d)\n", ret); goto err; } - DRM_DEBUG_KMS("HDCP is enabled (%d downstream devices)\n", - num_downstream); + drm_dbg_kms(&dev_priv->drm, "HDCP is enabled (%d downstream devices)\n", + num_downstream); ret = 0; err: kfree(ksv_fifo); @@ -592,13 +613,12 @@ err: /* Implements Part 1 of the HDCP authorization procedure */ static int intel_hdcp_auth(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - struct drm_device *dev = connector->base.dev; const struct intel_hdcp_shim *shim = hdcp->shim; - struct drm_i915_private *dev_priv; enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; - enum port port; + enum port port = intel_dig_port->base.port; unsigned long r0_prime_gen_start; int ret, i, tries = 2; union { @@ -615,10 +635,6 @@ static int intel_hdcp_auth(struct intel_connector *connector) } ri; bool repeater_present, hdcp_capable; - dev_priv = intel_dig_port->base.base.dev->dev_private; - - port = intel_dig_port->base.port; - /* * Detects whether the display is HDCP capable. Although we check for * valid Bksv below, the HDCP over DP spec requires that we check @@ -630,28 +646,32 @@ static int intel_hdcp_auth(struct intel_connector *connector) if (ret) return ret; if (!hdcp_capable) { - DRM_DEBUG_KMS("Panel is not HDCP capable\n"); + drm_dbg_kms(&dev_priv->drm, + "Panel is not HDCP capable\n"); return -EINVAL; } } /* Initialize An with 2 random values and acquire it */ for (i = 0; i < 2; i++) - I915_WRITE(HDCP_ANINIT(dev_priv, cpu_transcoder, port), - get_random_u32()); - I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port), - HDCP_CONF_CAPTURE_AN); + intel_de_write(dev_priv, + HDCP_ANINIT(dev_priv, cpu_transcoder, port), + get_random_u32()); + intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), + HDCP_CONF_CAPTURE_AN); /* Wait for An to be acquired */ if (intel_de_wait_for_set(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port), HDCP_STATUS_AN_READY, 1)) { - DRM_ERROR("Timed out waiting for An\n"); + drm_err(&dev_priv->drm, "Timed out waiting for An\n"); return -ETIMEDOUT; } - an.reg[0] = I915_READ(HDCP_ANLO(dev_priv, cpu_transcoder, port)); - an.reg[1] = I915_READ(HDCP_ANHI(dev_priv, cpu_transcoder, port)); + an.reg[0] = intel_de_read(dev_priv, + HDCP_ANLO(dev_priv, cpu_transcoder, port)); + an.reg[1] = intel_de_read(dev_priv, + HDCP_ANHI(dev_priv, cpu_transcoder, port)); ret = shim->write_an_aksv(intel_dig_port, an.shim); if (ret) return ret; @@ -664,33 +684,34 @@ static int intel_hdcp_auth(struct intel_connector *connector) if (ret < 0) return ret; - if (drm_hdcp_check_ksvs_revoked(dev, bksv.shim, 1)) { - DRM_ERROR("BKSV is revoked\n"); + if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, bksv.shim, 1)) { + drm_err(&dev_priv->drm, "BKSV is revoked\n"); return -EPERM; } - I915_WRITE(HDCP_BKSVLO(dev_priv, cpu_transcoder, port), bksv.reg[0]); - I915_WRITE(HDCP_BKSVHI(dev_priv, cpu_transcoder, port), bksv.reg[1]); + intel_de_write(dev_priv, HDCP_BKSVLO(dev_priv, cpu_transcoder, port), + bksv.reg[0]); + intel_de_write(dev_priv, HDCP_BKSVHI(dev_priv, cpu_transcoder, port), + bksv.reg[1]); ret = shim->repeater_present(intel_dig_port, &repeater_present); if (ret) return ret; if (repeater_present) - I915_WRITE(HDCP_REP_CTL, - intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, - port)); + intel_de_write(dev_priv, HDCP_REP_CTL, + intel_hdcp_get_repeater_ctl(dev_priv, cpu_transcoder, port)); ret = shim->toggle_signalling(intel_dig_port, true); if (ret) return ret; - I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port), - HDCP_CONF_AUTH_AND_ENC); + intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), + HDCP_CONF_AUTH_AND_ENC); /* Wait for R0 ready */ - if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) & + if (wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) & (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { - DRM_ERROR("Timed out waiting for R0 ready\n"); + drm_err(&dev_priv->drm, "Timed out waiting for R0 ready\n"); return -ETIMEDOUT; } @@ -716,19 +737,21 @@ static int intel_hdcp_auth(struct intel_connector *connector) ret = shim->read_ri_prime(intel_dig_port, ri.shim); if (ret) return ret; - I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg); + intel_de_write(dev_priv, + HDCP_RPRIME(dev_priv, cpu_transcoder, port), + ri.reg); /* Wait for Ri prime match */ - if (!wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, - port)) & - (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) + if (!wait_for(intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port)) & + (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) break; } if (i == tries) { - DRM_DEBUG_KMS("Timed out waiting for Ri prime match (%x)\n", - I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, - port))); + drm_dbg_kms(&dev_priv->drm, + "Timed out waiting for Ri prime match (%x)\n", + intel_de_read(dev_priv, HDCP_STATUS(dev_priv, + cpu_transcoder, port))); return -ETIMEDOUT; } @@ -737,7 +760,7 @@ static int intel_hdcp_auth(struct intel_connector *connector) HDCP_STATUS(dev_priv, cpu_transcoder, port), HDCP_STATUS_ENC, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { - DRM_ERROR("Timed out waiting for encryption\n"); + drm_err(&dev_priv->drm, "Timed out waiting for encryption\n"); return -ETIMEDOUT; } @@ -749,52 +772,53 @@ static int intel_hdcp_auth(struct intel_connector *connector) if (repeater_present) return intel_hdcp_auth_downstream(connector); - DRM_DEBUG_KMS("HDCP is enabled (no repeater present)\n"); + drm_dbg_kms(&dev_priv->drm, "HDCP is enabled (no repeater present)\n"); return 0; } static int _intel_hdcp_disable(struct intel_connector *connector) { + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - struct drm_i915_private *dev_priv = connector->base.dev->dev_private; - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; - DRM_DEBUG_KMS("[%s:%d] HDCP is being disabled...\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n", + connector->base.name, connector->base.base.id); hdcp->hdcp_encrypted = false; - I915_WRITE(HDCP_CONF(dev_priv, cpu_transcoder, port), 0); + intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0); if (intel_de_wait_for_clear(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port), ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { - DRM_ERROR("Failed to disable HDCP, timeout clearing status\n"); + drm_err(&dev_priv->drm, + "Failed to disable HDCP, timeout clearing status\n"); return -ETIMEDOUT; } ret = hdcp->shim->toggle_signalling(intel_dig_port, false); if (ret) { - DRM_ERROR("Failed to disable HDCP signalling\n"); + drm_err(&dev_priv->drm, "Failed to disable HDCP signalling\n"); return ret; } - DRM_DEBUG_KMS("HDCP is disabled\n"); + drm_dbg_kms(&dev_priv->drm, "HDCP is disabled\n"); return 0; } static int _intel_hdcp_enable(struct intel_connector *connector) { + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - struct drm_i915_private *dev_priv = connector->base.dev->dev_private; int i, ret, tries = 3; - DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being enabled...\n", + connector->base.name, connector->base.base.id); if (!hdcp_key_loadable(dev_priv)) { - DRM_ERROR("HDCP key Load is not possible\n"); + drm_err(&dev_priv->drm, "HDCP key Load is not possible\n"); return -ENXIO; } @@ -805,7 +829,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector) intel_hdcp_clear_keys(dev_priv); } if (ret) { - DRM_ERROR("Could not load HDCP keys, (%d)\n", ret); + drm_err(&dev_priv->drm, "Could not load HDCP keys, (%d)\n", + ret); return ret; } @@ -817,13 +842,14 @@ static int _intel_hdcp_enable(struct intel_connector *connector) return 0; } - DRM_DEBUG_KMS("HDCP Auth failure (%d)\n", ret); + drm_dbg_kms(&dev_priv->drm, "HDCP Auth failure (%d)\n", ret); /* Ensuring HDCP encryption and signalling are stopped. */ _intel_hdcp_disable(connector); } - DRM_DEBUG_KMS("HDCP authentication failed (%d tries/%d)\n", tries, ret); + drm_dbg_kms(&dev_priv->drm, + "HDCP authentication failed (%d tries/%d)\n", tries, ret); return ret; } @@ -836,9 +862,9 @@ struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) /* Implements Part 3 of the HDCP authorization procedure */ static int intel_hdcp_check_link(struct intel_connector *connector) { + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - struct drm_i915_private *dev_priv = connector->base.dev->dev_private; - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder; int ret = 0; @@ -853,11 +879,12 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; } - if (WARN_ON(!intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) { - DRM_ERROR("%s:%d HDCP link stopped encryption,%x\n", - connector->base.name, connector->base.base.id, - I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, - port))); + if (drm_WARN_ON(&dev_priv->drm, + !intel_hdcp_in_use(dev_priv, cpu_transcoder, port))) { + drm_err(&dev_priv->drm, + "%s:%d HDCP link stopped encryption,%x\n", + connector->base.name, connector->base.base.id, + intel_de_read(dev_priv, HDCP_STATUS(dev_priv, cpu_transcoder, port))); ret = -ENXIO; hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); @@ -872,12 +899,13 @@ static int intel_hdcp_check_link(struct intel_connector *connector) goto out; } - DRM_DEBUG_KMS("[%s:%d] HDCP link failed, retrying authentication\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] HDCP link failed, retrying authentication\n", + connector->base.name, connector->base.base.id); ret = _intel_hdcp_disable(connector); if (ret) { - DRM_ERROR("Failed to disable hdcp (%d)\n", ret); + drm_err(&dev_priv->drm, "Failed to disable hdcp (%d)\n", ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -885,7 +913,7 @@ static int intel_hdcp_check_link(struct intel_connector *connector) ret = _intel_hdcp_enable(connector); if (ret) { - DRM_ERROR("Failed to enable hdcp (%d)\n", ret); + drm_err(&dev_priv->drm, "Failed to enable hdcp (%d)\n", ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -901,9 +929,9 @@ static void intel_hdcp_prop_work(struct work_struct *work) struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, prop_work); struct intel_connector *connector = intel_hdcp_to_connector(hdcp); - struct drm_device *dev = connector->base.dev; + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, NULL); mutex_lock(&hdcp->mutex); /* @@ -916,13 +944,13 @@ static void intel_hdcp_prop_work(struct work_struct *work) hdcp->value); mutex_unlock(&hdcp->mutex); - drm_modeset_unlock(&dev->mode_config.connection_mutex); + drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex); } bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) { - /* PORT E doesn't have HDCP, and PORT F is disabled */ - return INTEL_INFO(dev_priv)->display.has_hdcp && port < PORT_E; + return INTEL_INFO(dev_priv)->display.has_hdcp && + (INTEL_GEN(dev_priv) >= 12 || port < PORT_E); } static int @@ -944,7 +972,8 @@ hdcp2_prepare_ake_init(struct intel_connector *connector, ret = comp->ops->initiate_hdcp2_session(comp->mei_dev, data, ake_data); if (ret) - DRM_DEBUG_KMS("Prepare_ake_init failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -974,7 +1003,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, rx_cert, paired, ek_pub_km, msg_sz); if (ret < 0) - DRM_DEBUG_KMS("Verify rx_cert failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -998,7 +1028,7 @@ static int hdcp2_verify_hprime(struct intel_connector *connector, ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime); if (ret < 0) - DRM_DEBUG_KMS("Verify hprime failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1023,7 +1053,8 @@ hdcp2_store_pairing_info(struct intel_connector *connector, ret = comp->ops->store_pairing_info(comp->mei_dev, data, pairing_info); if (ret < 0) - DRM_DEBUG_KMS("Store pairing info failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Store pairing info failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1048,7 +1079,8 @@ hdcp2_prepare_lc_init(struct intel_connector *connector, ret = comp->ops->initiate_locality_check(comp->mei_dev, data, lc_init); if (ret < 0) - DRM_DEBUG_KMS("Prepare lc_init failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Prepare lc_init failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1073,7 +1105,8 @@ hdcp2_verify_lprime(struct intel_connector *connector, ret = comp->ops->verify_lprime(comp->mei_dev, data, rx_lprime); if (ret < 0) - DRM_DEBUG_KMS("Verify L_Prime failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify L_Prime failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1097,7 +1130,8 @@ static int hdcp2_prepare_skey(struct intel_connector *connector, ret = comp->ops->get_session_key(comp->mei_dev, data, ske_data); if (ret < 0) - DRM_DEBUG_KMS("Get session key failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Get session key failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1126,7 +1160,8 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, rep_topology, rep_send_ack); if (ret < 0) - DRM_DEBUG_KMS("Verify rep topology failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, + "Verify rep topology failed. %d\n", ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1151,7 +1186,7 @@ hdcp2_verify_mprime(struct intel_connector *connector, ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready); if (ret < 0) - DRM_DEBUG_KMS("Verify mprime failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Verify mprime failed. %d\n", ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1174,7 +1209,8 @@ static int hdcp2_authenticate_port(struct intel_connector *connector) ret = comp->ops->enable_hdcp_authentication(comp->mei_dev, data); if (ret < 0) - DRM_DEBUG_KMS("Enable hdcp auth failed. %d\n", ret); + drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n", + ret); mutex_unlock(&dev_priv->hdcp_comp_mutex); return ret; @@ -1209,9 +1245,9 @@ static int hdcp2_deauthenticate_port(struct intel_connector *connector) /* Authentication flow starts from here */ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - struct drm_device *dev = connector->base.dev; union { struct hdcp2_ake_init ake_init; struct hdcp2_ake_send_cert send_cert; @@ -1242,15 +1278,16 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) return ret; if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { - DRM_DEBUG_KMS("cert.rx_caps dont claim HDCP2.2\n"); + drm_dbg_kms(&dev_priv->drm, "cert.rx_caps dont claim HDCP2.2\n"); return -EINVAL; } hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); - if (drm_hdcp_check_ksvs_revoked(dev, msgs.send_cert.cert_rx.receiver_id, + if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, + msgs.send_cert.cert_rx.receiver_id, 1)) { - DRM_ERROR("Receiver ID is revoked\n"); + drm_err(&dev_priv->drm, "Receiver ID is revoked\n"); return -EPERM; } @@ -1297,7 +1334,7 @@ static int hdcp2_authentication_key_exchange(struct intel_connector *connector) static int hdcp2_locality_check(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; union { struct hdcp2_lc_init lc_init; @@ -1333,7 +1370,7 @@ static int hdcp2_locality_check(struct intel_connector *connector) static int hdcp2_session_key_exchange(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; struct hdcp2_ske_send_eks send_eks; int ret; @@ -1353,7 +1390,7 @@ static int hdcp2_session_key_exchange(struct intel_connector *connector) static int hdcp2_propagate_stream_management_info(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct intel_hdcp *hdcp = &connector->hdcp; union { struct hdcp2_rep_stream_manage stream_manage; @@ -1404,9 +1441,9 @@ int hdcp2_propagate_stream_management_info(struct intel_connector *connector) static int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - struct drm_device *dev = connector->base.dev; union { struct hdcp2_rep_send_receiverid_list recvid_list; struct hdcp2_rep_send_ack rep_ack; @@ -1425,7 +1462,7 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { - DRM_DEBUG_KMS("Topology Max Size Exceeded\n"); + drm_dbg_kms(&dev_priv->drm, "Topology Max Size Exceeded\n"); return -EINVAL; } @@ -1433,17 +1470,24 @@ int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) seq_num_v = drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); + if (!hdcp->hdcp2_encrypted && seq_num_v) { + drm_dbg_kms(&dev_priv->drm, + "Non zero Seq_num_v at first RecvId_List msg\n"); + return -EINVAL; + } + if (seq_num_v < hdcp->seq_num_v) { /* Roll over of the seq_num_v from repeater. Reauthenticate. */ - DRM_DEBUG_KMS("Seq_num_v roll over.\n"); + drm_dbg_kms(&dev_priv->drm, "Seq_num_v roll over.\n"); return -EINVAL; } device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | HDCP_2_2_DEV_COUNT_LO(rx_info[1])); - if (drm_hdcp_check_ksvs_revoked(dev, msgs.recvid_list.receiver_ids, + if (drm_hdcp_check_ksvs_revoked(&dev_priv->drm, + msgs.recvid_list.receiver_ids, device_cnt)) { - DRM_ERROR("Revoked receiver ID(s) is in list\n"); + drm_err(&dev_priv->drm, "Revoked receiver ID(s) is in list\n"); return -EPERM; } @@ -1475,26 +1519,28 @@ static int hdcp2_authenticate_repeater(struct intel_connector *connector) static int hdcp2_authenticate_sink(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; const struct intel_hdcp_shim *shim = hdcp->shim; int ret; ret = hdcp2_authentication_key_exchange(connector); if (ret < 0) { - DRM_DEBUG_KMS("AKE Failed. Err : %d\n", ret); + drm_dbg_kms(&i915->drm, "AKE Failed. Err : %d\n", ret); return ret; } ret = hdcp2_locality_check(connector); if (ret < 0) { - DRM_DEBUG_KMS("Locality Check failed. Err : %d\n", ret); + drm_dbg_kms(&i915->drm, + "Locality Check failed. Err : %d\n", ret); return ret; } ret = hdcp2_session_key_exchange(connector); if (ret < 0) { - DRM_DEBUG_KMS("SKE Failed. Err : %d\n", ret); + drm_dbg_kms(&i915->drm, "SKE Failed. Err : %d\n", ret); return ret; } @@ -1509,7 +1555,8 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) if (hdcp->is_repeater) { ret = hdcp2_authenticate_repeater(connector); if (ret < 0) { - DRM_DEBUG_KMS("Repeater Auth Failed. Err: %d\n", ret); + drm_dbg_kms(&i915->drm, + "Repeater Auth Failed. Err: %d\n", ret); return ret; } } @@ -1524,31 +1571,32 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector) static int hdcp2_enable_encryption(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = connector->encoder->port; + enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; - WARN_ON(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & - LINK_ENCRYPTION_STATUS); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & + LINK_ENCRYPTION_STATUS); if (hdcp->shim->toggle_signalling) { ret = hdcp->shim->toggle_signalling(intel_dig_port, true); if (ret) { - DRM_ERROR("Failed to enable HDCP signalling. %d\n", - ret); + drm_err(&dev_priv->drm, + "Failed to enable HDCP signalling. %d\n", + ret); return ret; } } - if (I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & + if (intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & LINK_AUTH_STATUS) { /* Link is Authenticated. Now set for Encryption */ - I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port), - I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder, - port)) | - CTL_LINK_ENCRYPTION_REQ); + intel_de_write(dev_priv, + HDCP2_CTL(dev_priv, cpu_transcoder, port), + intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) | CTL_LINK_ENCRYPTION_REQ); } ret = intel_de_wait_for_set(dev_priv, @@ -1562,19 +1610,18 @@ static int hdcp2_enable_encryption(struct intel_connector *connector) static int hdcp2_disable_encryption(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = connector->encoder->port; + enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder = hdcp->cpu_transcoder; int ret; - WARN_ON(!(I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & - LINK_ENCRYPTION_STATUS)); + drm_WARN_ON(&dev_priv->drm, !(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) & + LINK_ENCRYPTION_STATUS)); - I915_WRITE(HDCP2_CTL(dev_priv, cpu_transcoder, port), - I915_READ(HDCP2_CTL(dev_priv, cpu_transcoder, port)) & - ~CTL_LINK_ENCRYPTION_REQ); + intel_de_write(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port), + intel_de_read(dev_priv, HDCP2_CTL(dev_priv, cpu_transcoder, port)) & ~CTL_LINK_ENCRYPTION_REQ); ret = intel_de_wait_for_clear(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, @@ -1582,13 +1629,14 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) LINK_ENCRYPTION_STATUS, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); if (ret == -ETIMEDOUT) - DRM_DEBUG_KMS("Disable Encryption Timedout"); + drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout"); if (hdcp->shim->toggle_signalling) { ret = hdcp->shim->toggle_signalling(intel_dig_port, false); if (ret) { - DRM_ERROR("Failed to disable HDCP signalling. %d\n", - ret); + drm_err(&dev_priv->drm, + "Failed to disable HDCP signalling. %d\n", + ret); return ret; } } @@ -1598,6 +1646,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector) static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector) { + struct drm_i915_private *i915 = to_i915(connector->base.dev); int ret, i, tries = 3; for (i = 0; i < tries; i++) { @@ -1606,10 +1655,10 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector) break; /* Clearing the mei hdcp session */ - DRM_DEBUG_KMS("HDCP2.2 Auth %d of %d Failed.(%d)\n", - i + 1, tries, ret); + drm_dbg_kms(&i915->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", + i + 1, tries, ret); if (hdcp2_deauthenticate_port(connector) < 0) - DRM_DEBUG_KMS("Port deauth failed.\n"); + drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); } if (i != tries) { @@ -1620,9 +1669,10 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector) msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); ret = hdcp2_enable_encryption(connector); if (ret < 0) { - DRM_DEBUG_KMS("Encryption Enable Failed.(%d)\n", ret); + drm_dbg_kms(&i915->drm, + "Encryption Enable Failed.(%d)\n", ret); if (hdcp2_deauthenticate_port(connector) < 0) - DRM_DEBUG_KMS("Port deauth failed.\n"); + drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); } } @@ -1631,23 +1681,24 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector) static int _intel_hdcp2_enable(struct intel_connector *connector) { + struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; int ret; - DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being enabled. Type: %d\n", - connector->base.name, connector->base.base.id, - hdcp->content_type); + drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being enabled. Type: %d\n", + connector->base.name, connector->base.base.id, + hdcp->content_type); ret = hdcp2_authenticate_and_encrypt(connector); if (ret) { - DRM_DEBUG_KMS("HDCP2 Type%d Enabling Failed. (%d)\n", - hdcp->content_type, ret); + drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", + hdcp->content_type, ret); return ret; } - DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is enabled. Type %d\n", - connector->base.name, connector->base.base.id, - hdcp->content_type); + drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is enabled. Type %d\n", + connector->base.name, connector->base.base.id, + hdcp->content_type); hdcp->hdcp2_encrypted = true; return 0; @@ -1655,15 +1706,16 @@ static int _intel_hdcp2_enable(struct intel_connector *connector) static int _intel_hdcp2_disable(struct intel_connector *connector) { + struct drm_i915_private *i915 = to_i915(connector->base.dev); int ret; - DRM_DEBUG_KMS("[%s:%d] HDCP2.2 is being Disabled\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n", + connector->base.name, connector->base.base.id); ret = hdcp2_disable_encryption(connector); if (hdcp2_deauthenticate_port(connector) < 0) - DRM_DEBUG_KMS("Port deauth failed.\n"); + drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); connector->hdcp.hdcp2_encrypted = false; @@ -1673,10 +1725,10 @@ static int _intel_hdcp2_disable(struct intel_connector *connector) /* Implements the Link Integrity Check for HDCP2.2 */ static int intel_hdcp2_check_link(struct intel_connector *connector) { - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; - enum port port = connector->encoder->port; + enum port port = intel_dig_port->base.port; enum transcoder cpu_transcoder; int ret = 0; @@ -1690,10 +1742,11 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) goto out; } - if (WARN_ON(!intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) { - DRM_ERROR("HDCP2.2 link stopped the encryption, %x\n", - I915_READ(HDCP2_STATUS(dev_priv, cpu_transcoder, - port))); + if (drm_WARN_ON(&dev_priv->drm, + !intel_hdcp2_in_use(dev_priv, cpu_transcoder, port))) { + drm_err(&dev_priv->drm, + "HDCP2.2 link stopped the encryption, %x\n", + intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port))); ret = -ENXIO; hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); @@ -1713,25 +1766,29 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) goto out; - DRM_DEBUG_KMS("HDCP2.2 Downstream topology change\n"); + drm_dbg_kms(&dev_priv->drm, + "HDCP2.2 Downstream topology change\n"); ret = hdcp2_authenticate_repeater_topology(connector); if (!ret) { hdcp->value = DRM_MODE_CONTENT_PROTECTION_ENABLED; schedule_work(&hdcp->prop_work); goto out; } - DRM_DEBUG_KMS("[%s:%d] Repeater topology auth failed.(%d)\n", - connector->base.name, connector->base.base.id, - ret); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] Repeater topology auth failed.(%d)\n", + connector->base.name, connector->base.base.id, + ret); } else { - DRM_DEBUG_KMS("[%s:%d] HDCP2.2 link failed, retrying auth\n", - connector->base.name, connector->base.base.id); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] HDCP2.2 link failed, retrying auth\n", + connector->base.name, connector->base.base.id); } ret = _intel_hdcp2_disable(connector); if (ret) { - DRM_ERROR("[%s:%d] Failed to disable hdcp2.2 (%d)\n", - connector->base.name, connector->base.base.id, ret); + drm_err(&dev_priv->drm, + "[%s:%d] Failed to disable hdcp2.2 (%d)\n", + connector->base.name, connector->base.base.id, ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -1739,9 +1796,10 @@ static int intel_hdcp2_check_link(struct intel_connector *connector) ret = _intel_hdcp2_enable(connector); if (ret) { - DRM_DEBUG_KMS("[%s:%d] Failed to enable hdcp2.2 (%d)\n", - connector->base.name, connector->base.base.id, - ret); + drm_dbg_kms(&dev_priv->drm, + "[%s:%d] Failed to enable hdcp2.2 (%d)\n", + connector->base.name, connector->base.base.id, + ret); hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; schedule_work(&hdcp->prop_work); goto out; @@ -1772,7 +1830,7 @@ static int i915_hdcp_component_bind(struct device *i915_kdev, { struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); - DRM_DEBUG("I915 HDCP comp bind\n"); + drm_dbg(&dev_priv->drm, "I915 HDCP comp bind\n"); mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data; dev_priv->hdcp_master->mei_dev = mei_kdev; @@ -1786,7 +1844,7 @@ static void i915_hdcp_component_unbind(struct device *i915_kdev, { struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev); - DRM_DEBUG("I915 HDCP comp unbind\n"); + drm_dbg(&dev_priv->drm, "I915 HDCP comp unbind\n"); mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv->hdcp_master = NULL; mutex_unlock(&dev_priv->hdcp_comp_mutex); @@ -1830,7 +1888,7 @@ static inline int initialize_hdcp_port_data(struct intel_connector *connector, if (INTEL_GEN(dev_priv) < 12) data->fw_ddi = - intel_get_mei_fw_ddi_index(connector->encoder->port); + intel_get_mei_fw_ddi_index(intel_attached_encoder(connector)->port); else /* * As per ME FW API expectation, for GEN 12+, fw_ddi is filled @@ -1854,7 +1912,7 @@ static inline int initialize_hdcp_port_data(struct intel_connector *connector, sizeof(struct hdcp2_streamid_type), GFP_KERNEL); if (!data->streams) { - DRM_ERROR("Out of Memory\n"); + drm_err(&dev_priv->drm, "Out of Memory\n"); return -ENOMEM; } @@ -1881,14 +1939,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv) return; mutex_lock(&dev_priv->hdcp_comp_mutex); - WARN_ON(dev_priv->hdcp_comp_added); + drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added); dev_priv->hdcp_comp_added = true; mutex_unlock(&dev_priv->hdcp_comp_mutex); ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops, I915_COMPONENT_HDCP); if (ret < 0) { - DRM_DEBUG_KMS("Failed at component add(%d)\n", ret); + drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n", + ret); mutex_lock(&dev_priv->hdcp_comp_mutex); dev_priv->hdcp_comp_added = false; mutex_unlock(&dev_priv->hdcp_comp_mutex); @@ -1899,12 +1958,13 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv) static void intel_hdcp2_init(struct intel_connector *connector, const struct intel_hdcp_shim *shim) { + struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_hdcp *hdcp = &connector->hdcp; int ret; ret = initialize_hdcp_port_data(connector, shim); if (ret) { - DRM_DEBUG_KMS("Mei hdcp data init failed\n"); + drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n"); return; } @@ -1954,7 +2014,8 @@ int intel_hdcp_enable(struct intel_connector *connector, return -ENOENT; mutex_lock(&hdcp->mutex); - WARN_ON(hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); + drm_WARN_ON(&dev_priv->drm, + hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); hdcp->content_type = content_type; if (INTEL_GEN(dev_priv) >= 12) { @@ -2014,6 +2075,46 @@ int intel_hdcp_disable(struct intel_connector *connector) return ret; } +void intel_hdcp_update_pipe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct intel_hdcp *hdcp = &connector->hdcp; + bool content_protection_type_changed = + (conn_state->hdcp_content_type != hdcp->content_type && + conn_state->content_protection != + DRM_MODE_CONTENT_PROTECTION_UNDESIRED); + + /* + * During the HDCP encryption session if Type change is requested, + * disable the HDCP and reenable it with new TYPE value. + */ + if (conn_state->content_protection == + DRM_MODE_CONTENT_PROTECTION_UNDESIRED || + content_protection_type_changed) + intel_hdcp_disable(connector); + + /* + * Mark the hdcp state as DESIRED after the hdcp disable of type + * change procedure. + */ + if (content_protection_type_changed) { + mutex_lock(&hdcp->mutex); + hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; + schedule_work(&hdcp->prop_work); + mutex_unlock(&hdcp->mutex); + } + + if (conn_state->content_protection == + DRM_MODE_CONTENT_PROTECTION_DESIRED || + content_protection_type_changed) + intel_hdcp_enable(connector, + crtc_state->cpu_transcoder, + (u8)conn_state->hdcp_content_type); +} + void intel_hdcp_component_fini(struct drm_i915_private *dev_priv) { mutex_lock(&dev_priv->hdcp_comp_mutex); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h index f3c3272e712a..7c12ad609b1f 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h @@ -8,12 +8,12 @@ #include <linux/types.h> -#include <drm/i915_drm.h> - struct drm_connector; struct drm_connector_state; struct drm_i915_private; struct intel_connector; +struct intel_crtc_state; +struct intel_encoder; struct intel_hdcp_shim; enum port; enum transcoder; @@ -26,6 +26,9 @@ int intel_hdcp_init(struct intel_connector *connector, int intel_hdcp_enable(struct intel_connector *connector, enum transcoder cpu_transcoder, u8 content_type); int intel_hdcp_disable(struct intel_connector *connector); +void intel_hdcp_update_pipe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state); bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port); bool intel_hdcp_capable(struct intel_connector *connector); bool intel_hdcp2_capable(struct intel_connector *connector); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 93ac0f296852..39930232b253 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -36,7 +36,6 @@ #include <drm/drm_edid.h> #include <drm/drm_hdcp.h> #include <drm/drm_scdc_helper.h> -#include <drm/i915_drm.h> #include <drm/intel_lpe_audio.h> #include "i915_debugfs.h" @@ -45,6 +44,7 @@ #include "intel_audio.h" #include "intel_connector.h" #include "intel_ddi.h" +#include "intel_display_debugfs.h" #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dpio_phy.h" @@ -72,17 +72,19 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; - WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, - "HDMI port enabled, expecting disabled\n"); + drm_WARN(dev, + intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, + "HDMI port enabled, expecting disabled\n"); } static void assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { - WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & - TRANS_DDI_FUNC_ENABLE, - "HDMI transcoder function enabled, expecting disabled\n"); + drm_WARN(&dev_priv->drm, + intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & + TRANS_DDI_FUNC_ENABLE, + "HDMI transcoder function enabled, expecting disabled\n"); } struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) @@ -215,32 +217,33 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, { const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(VIDEO_DIP_CTL); + u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); val &= ~g4x_infoframe_enable(type); - I915_WRITE(VIDEO_DIP_CTL, val); + intel_de_write(dev_priv, VIDEO_DIP_CTL, val); for (i = 0; i < len; i += 4) { - I915_WRITE(VIDEO_DIP_DATA, *data); + intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(VIDEO_DIP_DATA, 0); + intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(VIDEO_DIP_CTL, val); - POSTING_READ(VIDEO_DIP_CTL); + intel_de_write(dev_priv, VIDEO_DIP_CTL, val); + intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); } static void g4x_read_infoframe(struct intel_encoder *encoder, @@ -252,22 +255,22 @@ static void g4x_read_infoframe(struct intel_encoder *encoder, u32 val, *data = frame; int i; - val = I915_READ(VIDEO_DIP_CTL); + val = intel_de_read(dev_priv, VIDEO_DIP_CTL); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(VIDEO_DIP_CTL, val); + intel_de_write(dev_priv, VIDEO_DIP_CTL, val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(VIDEO_DIP_DATA); + *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); } static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(VIDEO_DIP_CTL); + u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -288,32 +291,34 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); val &= ~g4x_infoframe_enable(type); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); + intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), + *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); + intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); } static void ibx_read_infoframe(struct intel_encoder *encoder, @@ -326,15 +331,15 @@ static void ibx_read_infoframe(struct intel_encoder *encoder, u32 val, *data = frame; int i; - val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); + val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); + intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); + *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); } static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, @@ -343,7 +348,7 @@ static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; i915_reg_t reg = TVIDEO_DIP_CTL(pipe); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -365,10 +370,11 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); @@ -378,22 +384,23 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, if (type != HDMI_INFOFRAME_TYPE_AVI) val &= ~g4x_infoframe_enable(type); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); + intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), + *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); + intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); } static void cpt_read_infoframe(struct intel_encoder *encoder, @@ -406,15 +413,15 @@ static void cpt_read_infoframe(struct intel_encoder *encoder, u32 val, *data = frame; int i; - val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); + val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); + intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); + *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); } static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, @@ -422,7 +429,7 @@ static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; - u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); + u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -441,32 +448,35 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); val &= ~g4x_infoframe_enable(type); - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); + intel_de_write(dev_priv, + VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < VIDEO_DIP_DATA_SIZE; i += 4) - I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); + intel_de_write(dev_priv, + VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); val |= g4x_infoframe_enable(type); val &= ~VIDEO_DIP_FREQ_MASK; val |= VIDEO_DIP_FREQ_VSYNC; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); } static void vlv_read_infoframe(struct intel_encoder *encoder, @@ -479,15 +489,16 @@ static void vlv_read_infoframe(struct intel_encoder *encoder, u32 val, *data = frame; int i; - val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); + val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); - I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); + intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); for (i = 0; i < len; i += 4) - *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); + *data++ = intel_de_read(dev_priv, + VLV_TVIDEO_DIP_DATA(crtc->pipe)); } static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, @@ -495,7 +506,7 @@ static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; - u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); + u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); if ((val & VIDEO_DIP_ENABLE) == 0) return 0; @@ -519,28 +530,30 @@ static void hsw_write_infoframe(struct intel_encoder *encoder, i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); int data_size; int i; - u32 val = I915_READ(ctl_reg); + u32 val = intel_de_read(dev_priv, ctl_reg); data_size = hsw_dip_data_size(dev_priv, type); - WARN_ON(len > data_size); + drm_WARN_ON(&dev_priv->drm, len > data_size); val &= ~hsw_infoframe_enable(type); - I915_WRITE(ctl_reg, val); + intel_de_write(dev_priv, ctl_reg, val); for (i = 0; i < len; i += 4) { - I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, - type, i >> 2), *data); + intel_de_write(dev_priv, + hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), + *data); data++; } /* Write every possible data byte to force correct ECC calculation. */ for (; i < data_size; i += 4) - I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, - type, i >> 2), 0); + intel_de_write(dev_priv, + hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), + 0); val |= hsw_infoframe_enable(type); - I915_WRITE(ctl_reg, val); - POSTING_READ(ctl_reg); + intel_de_write(dev_priv, ctl_reg, val); + intel_de_posting_read(dev_priv, ctl_reg); } static void hsw_read_infoframe(struct intel_encoder *encoder, @@ -553,18 +566,19 @@ static void hsw_read_infoframe(struct intel_encoder *encoder, u32 val, *data = frame; int i; - val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); + val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder)); for (i = 0; i < len; i += 4) - *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, - type, i >> 2)); + *data++ = intel_de_read(dev_priv, + hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); } static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, const struct intel_crtc_state *pipe_config) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); + u32 val = intel_de_read(dev_priv, + HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); u32 mask; mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | @@ -655,12 +669,12 @@ static void intel_write_infoframe(struct intel_encoder *encoder, intel_hdmi_infoframe_enable(type)) == 0) return; - if (WARN_ON(frame->any.type != type)) + if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) return; /* see comment above for the reason for this offset */ len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); - if (WARN_ON(len < 0)) + if (drm_WARN_ON(encoder->base.dev, len < 0)) return; /* Insert the 'hole' (see big comment above) at position 3 */ @@ -734,8 +748,8 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, drm_hdmi_avi_infoframe_colorspace(frame, conn_state); /* nonsense combination */ - WARN_ON(crtc_state->limited_color_range && - crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); + drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && + crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { drm_hdmi_avi_infoframe_quant_range(frame, connector, @@ -753,7 +767,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, /* TODO: handle pixel repetition for YCBCR420 outputs */ ret = hdmi_avi_infoframe_check(frame); - if (WARN_ON(ret)) + if (drm_WARN_ON(encoder->base.dev, ret)) return false; return true; @@ -774,13 +788,13 @@ intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); - if (WARN_ON(ret)) + if (drm_WARN_ON(encoder->base.dev, ret)) return false; frame->sdi = HDMI_SPD_SDI_PC; ret = hdmi_spd_infoframe_check(frame); - if (WARN_ON(ret)) + if (drm_WARN_ON(encoder->base.dev, ret)) return false; return true; @@ -806,11 +820,11 @@ intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, conn_state->connector, &crtc_state->hw.adjusted_mode); - if (WARN_ON(ret)) + if (drm_WARN_ON(encoder->base.dev, ret)) return false; ret = hdmi_vendor_infoframe_check(frame); - if (WARN_ON(ret)) + if (drm_WARN_ON(encoder->base.dev, ret)) return false; return true; @@ -844,7 +858,7 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, } ret = hdmi_drm_infoframe_check(frame); - if (WARN_ON(ret)) + if (drm_WARN_ON(&dev_priv->drm, ret)) return false; return true; @@ -859,7 +873,7 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; i915_reg_t reg = VIDEO_DIP_CTL; - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); assert_hdmi_port_disabled(intel_hdmi); @@ -885,8 +899,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, } val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); return; } @@ -904,8 +918,8 @@ static void g4x_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -982,7 +996,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, else return false; - I915_WRITE(reg, crtc_state->infoframes.gcp); + intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); return true; } @@ -1007,7 +1021,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, else return; - crtc_state->infoframes.gcp = I915_READ(reg); + crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); } static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, @@ -1042,7 +1056,7 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); assert_hdmi_port_disabled(intel_hdmi); @@ -1056,15 +1070,15 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); return; } if (port != (val & VIDEO_DIP_PORT_MASK)) { - WARN(val & VIDEO_DIP_ENABLE, - "DIP already enabled on port %c\n", - (val & VIDEO_DIP_PORT_MASK) >> 29); + drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, + "DIP already enabled on port %c\n", + (val & VIDEO_DIP_PORT_MASK) >> 29); val &= ~VIDEO_DIP_PORT_MASK; val |= port; } @@ -1077,8 +1091,8 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1100,7 +1114,7 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); assert_hdmi_port_disabled(intel_hdmi); @@ -1113,8 +1127,8 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); return; } @@ -1126,8 +1140,8 @@ static void cpt_set_infoframes(struct intel_encoder *encoder, if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1149,7 +1163,7 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); u32 port = VIDEO_DIP_PORT(encoder->port); assert_hdmi_port_disabled(intel_hdmi); @@ -1163,15 +1177,15 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); return; } if (port != (val & VIDEO_DIP_PORT_MASK)) { - WARN(val & VIDEO_DIP_ENABLE, - "DIP already enabled on port %c\n", - (val & VIDEO_DIP_PORT_MASK) >> 29); + drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, + "DIP already enabled on port %c\n", + (val & VIDEO_DIP_PORT_MASK) >> 29); val &= ~VIDEO_DIP_PORT_MASK; val |= port; } @@ -1184,8 +1198,8 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1205,7 +1219,7 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); assert_hdmi_transcoder_func_disabled(dev_priv, crtc_state->cpu_transcoder); @@ -1216,16 +1230,16 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, VIDEO_DIP_ENABLE_DRM_GLK); if (!enable) { - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); return; } if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) val |= VIDEO_DIP_ENABLE_GCP_HSW; - I915_WRITE(reg, val); - POSTING_READ(reg); + intel_de_write(dev_priv, reg, val); + intel_de_posting_read(dev_priv, reg); intel_write_infoframe(encoder, crtc_state, HDMI_INFOFRAME_TYPE_AVI, @@ -1260,10 +1274,9 @@ void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, unsigned int offset, void *buffer, size_t size) { + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); struct intel_hdmi *hdmi = &intel_dig_port->hdmi; - struct drm_i915_private *dev_priv = - intel_dig_port->base.base.dev->dev_private; - struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, + struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; u8 start = offset & 0xff; @@ -1290,10 +1303,9 @@ static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, unsigned int offset, void *buffer, size_t size) { + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); struct intel_hdmi *hdmi = &intel_dig_port->hdmi; - struct drm_i915_private *dev_priv = - intel_dig_port->base.base.dev->dev_private; - struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, + struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; u8 *write_buf; @@ -1325,10 +1337,9 @@ static int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, u8 *an) { + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); struct intel_hdmi *hdmi = &intel_dig_port->hdmi; - struct drm_i915_private *dev_priv = - intel_dig_port->base.base.dev->dev_private; - struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, + struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, hdmi->ddc_bus); int ret; @@ -1447,7 +1458,7 @@ int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); + struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); struct drm_crtc *crtc = connector->base.state->crtc; struct intel_crtc *intel_crtc = container_of(crtc, struct intel_crtc, base); @@ -1455,7 +1466,7 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) int ret; for (;;) { - scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); + scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe)); if (scanline > 100 && scanline < 200) break; usleep_range(25, 50); @@ -1507,8 +1518,7 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, static bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) { - struct drm_i915_private *dev_priv = - intel_dig_port->base.base.dev->dev_private; + struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); struct intel_connector *connector = intel_dig_port->hdmi.attached_connector; enum port port = intel_dig_port->base.port; @@ -1523,14 +1533,13 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) if (ret) return false; - I915_WRITE(HDCP_RPRIME(dev_priv, cpu_transcoder, port), ri.reg); + intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); /* Wait for Ri prime match */ - if (wait_for(I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, port)) & + if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", - I915_READ(HDCP_STATUS(dev_priv, cpu_transcoder, - port))); + intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); return false; } return true; @@ -1767,8 +1776,8 @@ static void intel_hdmi_prepare(struct intel_encoder *encoder, else hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); - I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); } static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, @@ -1802,7 +1811,7 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); - tmp = I915_READ(intel_hdmi->hdmi_reg); + tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); if (tmp & SDVO_HSYNC_ACTIVE_HIGH) flags |= DRM_MODE_FLAG_PHSYNC; @@ -1863,7 +1872,7 @@ static void intel_enable_hdmi_audio(struct intel_encoder *encoder, { struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); - WARN_ON(!pipe_config->has_hdmi_sink); + drm_WARN_ON(encoder->base.dev, !pipe_config->has_hdmi_sink); DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", pipe_name(crtc->pipe)); intel_audio_codec_enable(encoder, pipe_config, conn_state); @@ -1878,14 +1887,14 @@ static void g4x_enable_hdmi(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; if (pipe_config->has_audio) temp |= HDMI_AUDIO_ENABLE; - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); if (pipe_config->has_audio) intel_enable_hdmi_audio(encoder, pipe_config, conn_state); @@ -1900,7 +1909,7 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; if (pipe_config->has_audio) @@ -1910,10 +1919,10 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); /* * HW workaround, need to toggle enable bit off and on @@ -1924,17 +1933,18 @@ static void ibx_enable_hdmi(struct intel_encoder *encoder, */ if (pipe_config->pipe_bpp > 24 && pipe_config->pixel_multiplier > 1) { - I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, + temp & ~SDVO_ENABLE); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); /* * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); } if (pipe_config->has_audio) @@ -1952,7 +1962,7 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, enum pipe pipe = crtc->pipe; u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); temp |= SDVO_ENABLE; if (pipe_config->has_audio) @@ -1969,27 +1979,25 @@ static void cpt_enable_hdmi(struct intel_encoder *encoder, */ if (pipe_config->pipe_bpp > 24) { - I915_WRITE(TRANS_CHICKEN1(pipe), - I915_READ(TRANS_CHICKEN1(pipe)) | - TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); + intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), + intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); temp &= ~SDVO_COLOR_FORMAT_MASK; temp |= SDVO_COLOR_FORMAT_8bpc; } - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); if (pipe_config->pipe_bpp > 24) { temp &= ~SDVO_COLOR_FORMAT_MASK; temp |= HDMI_COLOR_FORMAT_12bpc; - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); - I915_WRITE(TRANS_CHICKEN1(pipe), - I915_READ(TRANS_CHICKEN1(pipe)) & - ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); + intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), + intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); } if (pipe_config->has_audio) @@ -2014,11 +2022,11 @@ static void intel_disable_hdmi(struct intel_encoder *encoder, struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); u32 temp; - temp = I915_READ(intel_hdmi->hdmi_reg); + temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); /* * HW workaround for IBX, we need to move the port @@ -2039,14 +2047,14 @@ static void intel_disable_hdmi(struct intel_encoder *encoder, * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); temp &= ~SDVO_ENABLE; - I915_WRITE(intel_hdmi->hdmi_reg, temp); - POSTING_READ(intel_hdmi->hdmi_reg); + intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); + intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); intel_wait_for_vblank_if_active(dev_priv, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); @@ -2090,9 +2098,7 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder, static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - const struct ddi_vbt_port_info *info = - &dev_priv->vbt.ddi_port_info[encoder->port]; - int max_tmds_clock; + int max_tmds_clock, vbt_max_tmds_clock; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) max_tmds_clock = 594000; @@ -2103,15 +2109,23 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) else max_tmds_clock = 165000; - if (info->max_tmds_clock) - max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); + vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); + if (vbt_max_tmds_clock) + max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); return max_tmds_clock; } +static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, + const struct drm_connector_state *conn_state) +{ + return hdmi->has_hdmi_sink && + READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; +} + static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_downstream_limits, - bool force_dvi) + bool has_hdmi_sink) { struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); @@ -2127,7 +2141,7 @@ static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, if (info->max_tmds_clock) max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); - else if (!hdmi->has_hdmi_sink || force_dvi) + else if (!has_hdmi_sink) max_tmds_clock = min(max_tmds_clock, 165000); } @@ -2137,13 +2151,14 @@ static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, static enum drm_mode_status hdmi_port_clock_valid(struct intel_hdmi *hdmi, int clock, bool respect_downstream_limits, - bool force_dvi) + bool has_hdmi_sink) { struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); if (clock < 25000) return MODE_CLOCK_LOW; - if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) + if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, + has_hdmi_sink)) return MODE_CLOCK_HIGH; /* BXT DPLL can't generate 223-240 MHz */ @@ -2165,16 +2180,13 @@ intel_hdmi_mode_valid(struct drm_connector *connector, struct drm_device *dev = intel_hdmi_to_dev(hdmi); struct drm_i915_private *dev_priv = to_i915(dev); enum drm_mode_status status; - int clock; + int clock = mode->clock; int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; - bool force_dvi = - READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; + bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); if (mode->flags & DRM_MODE_FLAG_DBLSCAN) return MODE_NO_DBLESCAN; - clock = mode->clock; - if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) clock *= 2; @@ -2188,18 +2200,18 @@ intel_hdmi_mode_valid(struct drm_connector *connector, clock /= 2; /* check if we can do 8bpc */ - status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); + status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink); - if (hdmi->has_hdmi_sink && !force_dvi) { + if (has_hdmi_sink) { /* if we can't do 8bpc we may still be able to do 12bpc */ if (status != MODE_OK && !HAS_GMCH(dev_priv)) status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, - true, force_dvi); + true, has_hdmi_sink); /* if we can't do 8,12bpc we may still be able to do 10bpc */ if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, - true, force_dvi); + true, has_hdmi_sink); } if (status != MODE_OK) return status; @@ -2263,14 +2275,9 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, } } - /* Display WA #1139: glk */ - if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && - adjusted_mode->htotal > 5460) - return false; - - /* Display Wa_1405510057:icl */ + /* Display Wa_1405510057:icl,ehl */ if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && - bpc == 10 && INTEL_GEN(dev_priv) >= 11 && + bpc == 10 && IS_GEN(dev_priv, 11) && (adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start) % 8 == 2) return false; @@ -2315,7 +2322,7 @@ static int intel_hdmi_port_clock(int clock, int bpc) static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, - int clock, bool force_dvi) + int clock) { struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); int bpc; @@ -2324,7 +2331,7 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, if (hdmi_deep_color_possible(crtc_state, bpc) && hdmi_port_clock_valid(intel_hdmi, intel_hdmi_port_clock(clock, bpc), - true, force_dvi) == MODE_OK) + true, crtc_state->has_hdmi_sink) == MODE_OK) return bpc; } @@ -2332,8 +2339,7 @@ static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, } static int intel_hdmi_compute_clock(struct intel_encoder *encoder, - struct intel_crtc_state *crtc_state, - bool force_dvi) + struct intel_crtc_state *crtc_state) { struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); const struct drm_display_mode *adjusted_mode = @@ -2347,8 +2353,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder, if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) clock /= 2; - bpc = intel_hdmi_compute_bpc(encoder, crtc_state, - clock, force_dvi); + bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); @@ -2364,7 +2369,7 @@ static int intel_hdmi_compute_clock(struct intel_encoder *encoder, bpc, crtc_state->pipe_bpp); if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, - false, force_dvi) != MODE_OK) { + false, crtc_state->has_hdmi_sink) != MODE_OK) { DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n", crtc_state->port_clock); return -EINVAL; @@ -2412,14 +2417,14 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; struct intel_digital_connector_state *intel_conn_state = to_intel_digital_connector_state(conn_state); - bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; int ret; if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; - pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; + pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, + conn_state); if (pipe_config->has_hdmi_sink) pipe_config->has_infoframe = true; @@ -2448,7 +2453,7 @@ int intel_hdmi_compute_config(struct intel_encoder *encoder, intel_conn_state->force_audio == HDMI_AUDIO_ON; } - ret = intel_hdmi_compute_clock(encoder, pipe_config, force_dvi); + ret = intel_hdmi_compute_clock(encoder, pipe_config); if (ret) return ret; @@ -2808,7 +2813,7 @@ intel_hdmi_connector_register(struct drm_connector *connector) if (ret) return ret; - i915_debugfs_connector_add(connector); + intel_connector_debugfs_add(connector); intel_hdmi_create_i2c_symlink(connector); @@ -3002,7 +3007,7 @@ static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) else if (intel_phy_is_tc(dev_priv, phy)) return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); - WARN(1, "Unknown port:%c\n", port_name(port)); + drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); return GMBUS_PIN_2_BXT; } @@ -3052,17 +3057,17 @@ static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, return ddc_pin; } -static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, - enum port port) +static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) { - const struct ddi_vbt_port_info *info = - &dev_priv->vbt.ddi_port_info[port]; + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum port port = encoder->port; u8 ddc_pin; - if (info->alternate_ddc_pin) { + ddc_pin = intel_bios_alternate_ddc_pin(encoder); + if (ddc_pin) { DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", - info->alternate_ddc_pin, port_name(port)); - return info->alternate_ddc_pin; + ddc_pin, port_name(port)); + return ddc_pin; } if (HAS_PCH_MCC(dev_priv)) @@ -3139,16 +3144,16 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", intel_encoder->base.base.id, intel_encoder->base.name); - if (INTEL_GEN(dev_priv) < 12 && WARN_ON(port == PORT_A)) + if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) return; - if (WARN(intel_dig_port->max_lanes < 4, - "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, - intel_encoder->base.name)) + if (drm_WARN(dev, intel_dig_port->max_lanes < 4, + "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", + intel_dig_port->max_lanes, intel_encoder->base.base.id, + intel_encoder->base.name)) return; - intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); + intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); drm_connector_init_with_ddc(dev, connector, @@ -3165,6 +3170,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, connector->ycbcr_420_allowed = true; intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; if (HAS_DDI(dev_priv)) intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; @@ -3188,8 +3194,9 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, * generated on the port when a cable is not attached. */ if (IS_G45(dev_priv)) { - u32 temp = I915_READ(PEG_BAND_GAP_DATA); - I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); + u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); + intel_de_write(dev_priv, PEG_BAND_GAP_DATA, + (temp & ~0xf) | 0xd); } cec_fill_conn_info_from_drm(&conn_info, connector); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h index d3659d0b408b..8ff1f76a63df 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.h +++ b/drivers/gpu/drm/i915/display/intel_hdmi.h @@ -9,8 +9,6 @@ #include <linux/hdmi.h> #include <linux/types.h> -#include <drm/i915_drm.h> - #include "i915_reg.h" struct drm_connector; diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c index 99d3a3c7989e..a091442efba4 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug.c @@ -23,8 +23,6 @@ #include <linux/kernel.h> -#include <drm/i915_drm.h> - #include "i915_drv.h" #include "intel_display_types.h" #include "intel_hotplug.h" @@ -89,29 +87,16 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, enum port port) { - switch (port) { - case PORT_A: - return HPD_PORT_A; - case PORT_B: - return HPD_PORT_B; - case PORT_C: - return HPD_PORT_C; - case PORT_D: - return HPD_PORT_D; - case PORT_E: - return HPD_PORT_E; - case PORT_F: - if (IS_CNL_WITH_PORT_F(dev_priv)) - return HPD_PORT_E; - return HPD_PORT_F; - case PORT_G: - return HPD_PORT_G; - case PORT_H: - return HPD_PORT_H; - case PORT_I: - return HPD_PORT_I; + enum phy phy = intel_port_to_phy(dev_priv, port); + + switch (phy) { + case PHY_F: + return IS_CNL_WITH_PORT_F(dev_priv) ? HPD_PORT_E : HPD_PORT_F; + case PHY_A ... PHY_E: + case PHY_G ... PHY_I: + return HPD_PORT_A + phy - PHY_A; default: - MISSING_CASE(port); + MISSING_CASE(phy); return HPD_NONE; } } @@ -120,6 +105,20 @@ enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, #define HPD_STORM_REENABLE_DELAY (2 * 60 * 1000) #define HPD_RETRY_DELAY 1000 +static enum hpd_pin +intel_connector_hpd_pin(struct intel_connector *connector) +{ + struct intel_encoder *encoder = intel_attached_encoder(connector); + + /* + * MST connectors get their encoder attached dynamically + * so need to make sure we have an encoder here. But since + * MST encoders have their hpd_pin set to HPD_NONE we don't + * have to special case them beyond that. + */ + return encoder ? encoder->hpd_pin : HPD_NONE; +} + /** * intel_hpd_irq_storm_detect - gather stats and detect HPD IRQ storm on a pin * @dev_priv: private driver data pointer @@ -171,10 +170,13 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv, hpd->stats[pin].count += increment; if (hpd->stats[pin].count > threshold) { hpd->stats[pin].state = HPD_MARK_DISABLED; - DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", pin); + drm_dbg_kms(&dev_priv->drm, + "HPD interrupt storm detected on PIN %d\n", pin); storm = true; } else { - DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", pin, + drm_dbg_kms(&dev_priv->drm, + "Received HPD interrupt on PIN %d - cnt: %d\n", + pin, hpd->stats[pin].count); } @@ -185,37 +187,32 @@ static void intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv) { struct drm_device *dev = &dev_priv->drm; - struct intel_connector *intel_connector; - struct intel_encoder *intel_encoder; - struct drm_connector *connector; struct drm_connector_list_iter conn_iter; - enum hpd_pin pin; + struct intel_connector *connector; bool hpd_disabled = false; lockdep_assert_held(&dev_priv->irq_lock); drm_connector_list_iter_begin(dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { - if (connector->polled != DRM_CONNECTOR_POLL_HPD) - continue; + for_each_intel_connector_iter(connector, &conn_iter) { + enum hpd_pin pin; - intel_connector = to_intel_connector(connector); - intel_encoder = intel_connector->encoder; - if (!intel_encoder) + if (connector->base.polled != DRM_CONNECTOR_POLL_HPD) continue; - pin = intel_encoder->hpd_pin; + pin = intel_connector_hpd_pin(connector); if (pin == HPD_NONE || dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED) continue; - DRM_INFO("HPD interrupt storm detected on connector %s: " + drm_info(&dev_priv->drm, + "HPD interrupt storm detected on connector %s: " "switching from hotplug detection to polling\n", - connector->name); + connector->base.name); dev_priv->hotplug.stats[pin].state = HPD_DISABLED; - connector->polled = DRM_CONNECTOR_POLL_CONNECT - | DRM_CONNECTOR_POLL_DISCONNECT; + connector->base.polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; hpd_disabled = true; } drm_connector_list_iter_end(&conn_iter); @@ -234,40 +231,38 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work) container_of(work, typeof(*dev_priv), hotplug.reenable_work.work); struct drm_device *dev = &dev_priv->drm; + struct drm_connector_list_iter conn_iter; + struct intel_connector *connector; intel_wakeref_t wakeref; enum hpd_pin pin; wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); spin_lock_irq(&dev_priv->irq_lock); - for_each_hpd_pin(pin) { - struct drm_connector *connector; - struct drm_connector_list_iter conn_iter; - if (dev_priv->hotplug.stats[pin].state != HPD_DISABLED) + drm_connector_list_iter_begin(dev, &conn_iter); + for_each_intel_connector_iter(connector, &conn_iter) { + pin = intel_connector_hpd_pin(connector); + if (pin == HPD_NONE || + dev_priv->hotplug.stats[pin].state != HPD_DISABLED) continue; - dev_priv->hotplug.stats[pin].state = HPD_ENABLED; - - drm_connector_list_iter_begin(dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { - struct intel_connector *intel_connector = to_intel_connector(connector); - - /* Don't check MST ports, they don't have pins */ - if (!intel_connector->mst_port && - intel_connector->encoder->hpd_pin == pin) { - if (connector->polled != intel_connector->polled) - DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", - connector->name); - connector->polled = intel_connector->polled; - if (!connector->polled) - connector->polled = DRM_CONNECTOR_POLL_HPD; - } - } - drm_connector_list_iter_end(&conn_iter); + if (connector->base.polled != connector->polled) + drm_dbg(&dev_priv->drm, + "Reenabling HPD on connector %s\n", + connector->base.name); + connector->base.polled = connector->polled; } + drm_connector_list_iter_end(&conn_iter); + + for_each_hpd_pin(pin) { + if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) + dev_priv->hotplug.stats[pin].state = HPD_ENABLED; + } + if (dev_priv->display_irqs_enabled && dev_priv->display.hpd_irq_setup) dev_priv->display.hpd_irq_setup(dev_priv); + spin_unlock_irq(&dev_priv->irq_lock); intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); @@ -281,7 +276,7 @@ intel_encoder_hotplug(struct intel_encoder *encoder, struct drm_device *dev = connector->base.dev; enum drm_connector_status old_status; - WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); + drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex)); old_status = connector->base.status; connector->base.status = @@ -290,11 +285,12 @@ intel_encoder_hotplug(struct intel_encoder *encoder, if (old_status == connector->base.status) return INTEL_HOTPLUG_UNCHANGED; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", - connector->base.base.id, - connector->base.name, - drm_get_connector_status_name(old_status), - drm_get_connector_status_name(connector->base.status)); + drm_dbg_kms(&to_i915(dev)->drm, + "[CONNECTOR:%d:%s] status updated from %s to %s\n", + connector->base.base.id, + connector->base.name, + drm_get_connector_status_name(old_status), + drm_get_connector_status_name(connector->base.status)); return INTEL_HOTPLUG_CHANGED; } @@ -361,16 +357,14 @@ static void i915_hotplug_work_func(struct work_struct *work) container_of(work, struct drm_i915_private, hotplug.hotplug_work.work); struct drm_device *dev = &dev_priv->drm; - struct intel_connector *intel_connector; - struct intel_encoder *intel_encoder; - struct drm_connector *connector; struct drm_connector_list_iter conn_iter; + struct intel_connector *connector; u32 changed = 0, retry = 0; u32 hpd_event_bits; u32 hpd_retry_bits; mutex_lock(&dev->mode_config.mutex); - DRM_DEBUG_KMS("running encoder hotplug functions\n"); + drm_dbg_kms(&dev_priv->drm, "running encoder hotplug functions\n"); spin_lock_irq(&dev_priv->irq_lock); @@ -385,21 +379,25 @@ static void i915_hotplug_work_func(struct work_struct *work) spin_unlock_irq(&dev_priv->irq_lock); drm_connector_list_iter_begin(dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { + for_each_intel_connector_iter(connector, &conn_iter) { + enum hpd_pin pin; u32 hpd_bit; - intel_connector = to_intel_connector(connector); - if (!intel_connector->encoder) + pin = intel_connector_hpd_pin(connector); + if (pin == HPD_NONE) continue; - intel_encoder = intel_connector->encoder; - hpd_bit = BIT(intel_encoder->hpd_pin); + + hpd_bit = BIT(pin); if ((hpd_event_bits | hpd_retry_bits) & hpd_bit) { - DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", - connector->name, intel_encoder->hpd_pin); + struct intel_encoder *encoder = + intel_attached_encoder(connector); + + drm_dbg_kms(&dev_priv->drm, + "Connector %s (pin %i) received hotplug event.\n", + connector->base.name, pin); - switch (intel_encoder->hotplug(intel_encoder, - intel_connector, - hpd_event_bits & hpd_bit)) { + switch (encoder->hotplug(encoder, connector, + hpd_event_bits & hpd_bit)) { case INTEL_HOTPLUG_UNCHANGED: break; case INTEL_HOTPLUG_CHANGED: @@ -481,9 +479,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, long_hpd = long_mask & BIT(pin); - DRM_DEBUG_DRIVER("digital hpd on [ENCODER:%d:%s] - %s\n", - encoder->base.base.id, encoder->base.name, - long_hpd ? "long" : "short"); + drm_dbg(&dev_priv->drm, + "digital hpd on [ENCODER:%d:%s] - %s\n", + encoder->base.base.id, encoder->base.name, + long_hpd ? "long" : "short"); queue_dig = true; if (long_hpd) { @@ -509,8 +508,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, * hotplug bits itself. So only WARN about unexpected * interrupts on saner platforms. */ - WARN_ONCE(!HAS_GMCH(dev_priv), - "Received HPD interrupt on pin %d although disabled\n", pin); + drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv), + "Received HPD interrupt on pin %d although disabled\n", + pin); continue; } @@ -601,8 +601,8 @@ static void i915_hpd_poll_init_work(struct work_struct *work) container_of(work, struct drm_i915_private, hotplug.poll_init_work); struct drm_device *dev = &dev_priv->drm; - struct drm_connector *connector; struct drm_connector_list_iter conn_iter; + struct intel_connector *connector; bool enabled; mutex_lock(&dev->mode_config.mutex); @@ -610,23 +610,18 @@ static void i915_hpd_poll_init_work(struct work_struct *work) enabled = READ_ONCE(dev_priv->hotplug.poll_enabled); drm_connector_list_iter_begin(dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { - struct intel_connector *intel_connector = - to_intel_connector(connector); - connector->polled = intel_connector->polled; - - /* MST has a dynamic intel_connector->encoder and it's reprobing - * is all handled by the MST helpers. */ - if (intel_connector->mst_port) + for_each_intel_connector_iter(connector, &conn_iter) { + enum hpd_pin pin; + + pin = intel_connector_hpd_pin(connector); + if (pin == HPD_NONE) continue; - if (!connector->polled && I915_HAS_HOTPLUG(dev_priv) && - intel_connector->encoder->hpd_pin > HPD_NONE) { - connector->polled = enabled ? - DRM_CONNECTOR_POLL_CONNECT | - DRM_CONNECTOR_POLL_DISCONNECT : - DRM_CONNECTOR_POLL_HPD; - } + connector->base.polled = connector->polled; + + if (enabled && connector->base.polled == DRM_CONNECTOR_POLL_HPD) + connector->base.polled = DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT; } drm_connector_list_iter_end(&conn_iter); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.h b/drivers/gpu/drm/i915/display/intel_hotplug.h index 087b5f57b321..1e6b4fda2900 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug.h +++ b/drivers/gpu/drm/i915/display/intel_hotplug.h @@ -8,8 +8,6 @@ #include <linux/types.h> -#include <drm/i915_drm.h> - struct drm_i915_private; struct intel_connector; struct intel_encoder; diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 0b67f7887cd0..ad5cc13037ae 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -71,6 +71,7 @@ #include <drm/intel_lpe_audio.h> #include "i915_drv.h" +#include "intel_de.h" #include "intel_lpe_audio.h" #define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->lpe_audio.platdev != NULL) @@ -126,7 +127,8 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv) kfree(pdata); if (IS_ERR(platdev)) { - DRM_ERROR("Failed to allocate LPE audio platform device\n"); + drm_err(&dev_priv->drm, + "Failed to allocate LPE audio platform device\n"); return platdev; } @@ -166,7 +168,7 @@ static int lpe_audio_irq_init(struct drm_i915_private *dev_priv) { int irq = dev_priv->lpe_audio.irq; - WARN_ON(!intel_irqs_enabled(dev_priv)); + drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)); irq_set_chip_and_handler_name(irq, &lpe_audio_irqchip, handle_simple_irq, @@ -189,7 +191,8 @@ static bool lpe_audio_detect(struct drm_i915_private *dev_priv) }; if (!pci_dev_present(atom_hdaudio_ids)) { - DRM_INFO("HDaudio controller not detected, using LPE audio instead\n"); + drm_info(&dev_priv->drm, + "HDaudio controller not detected, using LPE audio instead\n"); lpe_present = true; } } @@ -202,18 +205,19 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv) dev_priv->lpe_audio.irq = irq_alloc_desc(0); if (dev_priv->lpe_audio.irq < 0) { - DRM_ERROR("Failed to allocate IRQ desc: %d\n", + drm_err(&dev_priv->drm, "Failed to allocate IRQ desc: %d\n", dev_priv->lpe_audio.irq); ret = dev_priv->lpe_audio.irq; goto err; } - DRM_DEBUG("irq = %d\n", dev_priv->lpe_audio.irq); + drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->lpe_audio.irq); ret = lpe_audio_irq_init(dev_priv); if (ret) { - DRM_ERROR("Failed to initialize irqchip for lpe audio: %d\n", + drm_err(&dev_priv->drm, + "Failed to initialize irqchip for lpe audio: %d\n", ret); goto err_free_irq; } @@ -222,7 +226,8 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv) if (IS_ERR(dev_priv->lpe_audio.platdev)) { ret = PTR_ERR(dev_priv->lpe_audio.platdev); - DRM_ERROR("Failed to create lpe audio platform device: %d\n", + drm_err(&dev_priv->drm, + "Failed to create lpe audio platform device: %d\n", ret); goto err_free_irq; } @@ -230,7 +235,8 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv) /* enable chicken bit; at least this is required for Dell Wyse 3040 * with DP outputs (but only sometimes by some reason!) */ - I915_WRITE(VLV_AUD_CHICKEN_BIT_REG, VLV_CHICKEN_BIT_DBG_ENABLE); + intel_de_write(dev_priv, VLV_AUD_CHICKEN_BIT_REG, + VLV_CHICKEN_BIT_DBG_ENABLE); return 0; err_free_irq: @@ -257,8 +263,8 @@ void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv) ret = generic_handle_irq(dev_priv->lpe_audio.irq); if (ret) - DRM_ERROR_RATELIMITED("error handling LPE audio irq: %d\n", - ret); + drm_err_ratelimited(&dev_priv->drm, + "error handling LPE audio irq: %d\n", ret); } /** @@ -276,7 +282,8 @@ int intel_lpe_audio_init(struct drm_i915_private *dev_priv) if (lpe_audio_detect(dev_priv)) { ret = lpe_audio_setup(dev_priv); if (ret < 0) - DRM_ERROR("failed to setup LPE Audio bridge\n"); + drm_err(&dev_priv->drm, + "failed to setup LPE Audio bridge\n"); } return ret; } @@ -334,7 +341,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, spin_lock_irqsave(&pdata->lpe_audio_slock, irqflags); - audio_enable = I915_READ(VLV_AUD_PORT_EN_DBG(port)); + audio_enable = intel_de_read(dev_priv, VLV_AUD_PORT_EN_DBG(port)); if (eld != NULL) { memcpy(ppdata->eld, eld, HDMI_MAX_ELD_BYTES); @@ -343,8 +350,8 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, ppdata->dp_output = dp_output; /* Unmute the amp for both DP and HDMI */ - I915_WRITE(VLV_AUD_PORT_EN_DBG(port), - audio_enable & ~VLV_AMP_MUTE); + intel_de_write(dev_priv, VLV_AUD_PORT_EN_DBG(port), + audio_enable & ~VLV_AMP_MUTE); } else { memset(ppdata->eld, 0, HDMI_MAX_ELD_BYTES); ppdata->pipe = -1; @@ -352,8 +359,8 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, ppdata->dp_output = false; /* Mute the amp for both DP and HDMI */ - I915_WRITE(VLV_AUD_PORT_EN_DBG(port), - audio_enable | VLV_AMP_MUTE); + intel_de_write(dev_priv, VLV_AUD_PORT_EN_DBG(port), + audio_enable | VLV_AMP_MUTE); } if (pdata->notify_audio_lpe) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 10696bb99dcf..9a067effcfa0 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -37,7 +37,6 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "intel_atomic.h" @@ -85,7 +84,7 @@ bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(lvds_reg); + val = intel_de_read(dev_priv, lvds_reg); /* asserts want to know the pipe even if the port is disabled */ if (HAS_PCH_CPT(dev_priv)) @@ -125,7 +124,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); - tmp = I915_READ(lvds_encoder->reg); + tmp = intel_de_read(dev_priv, lvds_encoder->reg); if (tmp & LVDS_HSYNC_POLARITY) flags |= DRM_MODE_FLAG_NHSYNC; else @@ -143,7 +142,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, /* gen2/3 store dither state in pfit control, needs to match */ if (INTEL_GEN(dev_priv) < 4) { - tmp = I915_READ(PFIT_CONTROL); + tmp = intel_de_read(dev_priv, PFIT_CONTROL); pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; } @@ -156,18 +155,18 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, { u32 val; - pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; + pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; - val = I915_READ(PP_ON_DELAYS(0)); + val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); - val = I915_READ(PP_OFF_DELAYS(0)); + val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); - val = I915_READ(PP_DIVISOR(0)); + val = intel_de_read(dev_priv, PP_DIVISOR(0)); pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); /* @@ -182,8 +181,9 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, if (INTEL_GEN(dev_priv) <= 4 && pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { - DRM_DEBUG_KMS("Panel power timings uninitialized, " - "setting defaults\n"); + drm_dbg_kms(&dev_priv->drm, + "Panel power timings uninitialized, " + "setting defaults\n"); /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ pps->t1_t2 = 40 * 10; pps->t5 = 200 * 10; @@ -192,10 +192,10 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, pps->tx = 200 * 10; } - DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " - "divider %d port %d powerdown_on_reset %d\n", - pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, - pps->divider, pps->port, pps->powerdown_on_reset); + drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " + "divider %d port %d powerdown_on_reset %d\n", + pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, + pps->divider, pps->port, pps->powerdown_on_reset); } static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, @@ -203,25 +203,21 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(PP_CONTROL(0)); - WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); + val = intel_de_read(dev_priv, PP_CONTROL(0)); + drm_WARN_ON(&dev_priv->drm, + (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); if (pps->powerdown_on_reset) val |= PANEL_POWER_RESET; - I915_WRITE(PP_CONTROL(0), val); + intel_de_write(dev_priv, PP_CONTROL(0), val); - I915_WRITE(PP_ON_DELAYS(0), - REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | - REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | - REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); + intel_de_write(dev_priv, PP_ON_DELAYS(0), + REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); - I915_WRITE(PP_OFF_DELAYS(0), - REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | - REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); + intel_de_write(dev_priv, PP_OFF_DELAYS(0), + REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); - I915_WRITE(PP_DIVISOR(0), - REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | - REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, - DIV_ROUND_UP(pps->t4, 1000) + 1)); + intel_de_write(dev_priv, PP_DIVISOR(0), + REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); } static void intel_pre_enable_lvds(struct intel_encoder *encoder, @@ -299,7 +295,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) temp |= LVDS_VSYNC_POLARITY; - I915_WRITE(lvds_encoder->reg, temp); + intel_de_write(dev_priv, lvds_encoder->reg, temp); } /* @@ -313,13 +309,16 @@ static void intel_enable_lvds(struct intel_encoder *encoder, struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); struct drm_i915_private *dev_priv = to_i915(dev); - I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); + intel_de_write(dev_priv, lvds_encoder->reg, + intel_de_read(dev_priv, lvds_encoder->reg) | LVDS_PORT_EN); - I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); - POSTING_READ(lvds_encoder->reg); + intel_de_write(dev_priv, PP_CONTROL(0), + intel_de_read(dev_priv, PP_CONTROL(0)) | PANEL_POWER_ON); + intel_de_posting_read(dev_priv, lvds_encoder->reg); if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) - DRM_ERROR("timed out waiting for panel to power on\n"); + drm_err(&dev_priv->drm, + "timed out waiting for panel to power on\n"); intel_panel_enable_backlight(pipe_config, conn_state); } @@ -331,12 +330,15 @@ static void intel_disable_lvds(struct intel_encoder *encoder, struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); + intel_de_write(dev_priv, PP_CONTROL(0), + intel_de_read(dev_priv, PP_CONTROL(0)) & ~PANEL_POWER_ON); if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) - DRM_ERROR("timed out waiting for panel to power off\n"); + drm_err(&dev_priv->drm, + "timed out waiting for panel to power off\n"); - I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); - POSTING_READ(lvds_encoder->reg); + intel_de_write(dev_priv, lvds_encoder->reg, + intel_de_read(dev_priv, lvds_encoder->reg) & ~LVDS_PORT_EN); + intel_de_posting_read(dev_priv, lvds_encoder->reg); } static void gmch_disable_lvds(struct intel_encoder *encoder, @@ -398,7 +400,7 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, /* Should never happen!! */ if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { - DRM_ERROR("Can't support LVDS on pipe A\n"); + drm_err(&dev_priv->drm, "Can't support LVDS on pipe A\n"); return -EINVAL; } @@ -408,8 +410,9 @@ static int intel_lvds_compute_config(struct intel_encoder *intel_encoder, lvds_bpp = 6*3; if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { - DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", - pipe_config->pipe_bpp, lvds_bpp); + drm_dbg_kms(&dev_priv->drm, + "forcing display bpp (was %d) to LVDS (%d)\n", + pipe_config->pipe_bpp, lvds_bpp); pipe_config->pipe_bpp = lvds_bpp; } @@ -791,7 +794,7 @@ static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) * we need to check "the value to be set" in VBT when LVDS * register is uninitialized. */ - val = I915_READ(lvds_encoder->reg); + val = intel_de_read(dev_priv, lvds_encoder->reg); if (HAS_PCH_CPT(dev_priv)) val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT); else @@ -827,13 +830,14 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) /* Skip init on machines we know falsely report LVDS */ if (dmi_check_system(intel_no_lvds)) { - WARN(!dev_priv->vbt.int_lvds_support, - "Useless DMI match. Internal LVDS support disabled by VBT\n"); + drm_WARN(dev, !dev_priv->vbt.int_lvds_support, + "Useless DMI match. Internal LVDS support disabled by VBT\n"); return; } if (!dev_priv->vbt.int_lvds_support) { - DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n"); + drm_dbg_kms(&dev_priv->drm, + "Internal LVDS support disabled by VBT\n"); return; } @@ -842,7 +846,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) else lvds_reg = LVDS; - lvds = I915_READ(lvds_reg); + lvds = intel_de_read(dev_priv, lvds_reg); if (HAS_PCH_SPLIT(dev_priv)) { if ((lvds & LVDS_DETECTED) == 0) @@ -852,10 +856,12 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) pin = GMBUS_PIN_PANEL; if (!intel_bios_is_lvds_present(dev_priv, &pin)) { if ((lvds & LVDS_PORT_EN) == 0) { - DRM_DEBUG_KMS("LVDS is not present in VBT\n"); + drm_dbg_kms(&dev_priv->drm, + "LVDS is not present in VBT\n"); return; } - DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); + drm_dbg_kms(&dev_priv->drm, + "LVDS is not present in VBT, but enabled anyway\n"); } lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); @@ -969,7 +975,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) */ fixed_mode = intel_encoder_current_mode(intel_encoder); if (fixed_mode) { - DRM_DEBUG_KMS("using current (BIOS) mode: "); + drm_dbg_kms(&dev_priv->drm, "using current (BIOS) mode: "); drm_mode_debug_printmodeline(fixed_mode); fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; } @@ -985,8 +991,8 @@ out: intel_panel_setup_backlight(connector, INVALID_PIPE); lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); - DRM_DEBUG_KMS("detected %s-link lvds configuration\n", - lvds_encoder->is_dual_link ? "dual" : "single"); + drm_dbg_kms(&dev_priv->drm, "detected %s-link lvds configuration\n", + lvds_encoder->is_dual_link ? "dual" : "single"); lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; @@ -995,7 +1001,7 @@ out: failed: mutex_unlock(&dev->mode_config.mutex); - DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); + drm_dbg_kms(&dev_priv->drm, "No LVDS modes found, disabling.\n"); drm_connector_cleanup(connector); drm_encoder_cleanup(encoder); kfree(lvds_encoder); diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c index e59b4992ba1b..cc6b00959586 100644 --- a/drivers/gpu/drm/i915/display/intel_opregion.c +++ b/drivers/gpu/drm/i915/display/intel_opregion.c @@ -30,11 +30,10 @@ #include <linux/firmware.h> #include <acpi/video.h> -#include <drm/i915_drm.h> - #include "display/intel_panel.h" #include "i915_drv.h" +#include "intel_acpi.h" #include "intel_display_types.h" #include "intel_opregion.h" @@ -242,29 +241,6 @@ struct opregion_asle_ext { #define SWSCI_SBCB_POST_VBE_PM SWSCI_FUNCTION_CODE(SWSCI_SBCB, 19) #define SWSCI_SBCB_ENABLE_DISABLE_AUDIO SWSCI_FUNCTION_CODE(SWSCI_SBCB, 21) -/* - * ACPI Specification, Revision 5.0, Appendix B.3.2 _DOD (Enumerate All Devices - * Attached to the Display Adapter). - */ -#define ACPI_DISPLAY_INDEX_SHIFT 0 -#define ACPI_DISPLAY_INDEX_MASK (0xf << 0) -#define ACPI_DISPLAY_PORT_ATTACHMENT_SHIFT 4 -#define ACPI_DISPLAY_PORT_ATTACHMENT_MASK (0xf << 4) -#define ACPI_DISPLAY_TYPE_SHIFT 8 -#define ACPI_DISPLAY_TYPE_MASK (0xf << 8) -#define ACPI_DISPLAY_TYPE_OTHER (0 << 8) -#define ACPI_DISPLAY_TYPE_VGA (1 << 8) -#define ACPI_DISPLAY_TYPE_TV (2 << 8) -#define ACPI_DISPLAY_TYPE_EXTERNAL_DIGITAL (3 << 8) -#define ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL (4 << 8) -#define ACPI_VENDOR_SPECIFIC_SHIFT 12 -#define ACPI_VENDOR_SPECIFIC_MASK (0xf << 12) -#define ACPI_BIOS_CAN_DETECT (1 << 16) -#define ACPI_DEPENDS_ON_VGA (1 << 17) -#define ACPI_PIPE_ID_SHIFT 18 -#define ACPI_PIPE_ID_MASK (7 << 18) -#define ACPI_DEVICE_ID_SCHEME (1 << 31) - #define MAX_DSLP 1500 static int swsci(struct drm_i915_private *dev_priv, @@ -311,7 +287,7 @@ static int swsci(struct drm_i915_private *dev_priv, /* The spec tells us to do this, but we are the only user... */ scic = swsci->scic; if (scic & SWSCI_SCIC_INDICATOR) { - DRM_DEBUG_DRIVER("SWSCI request already in progress\n"); + drm_dbg(&dev_priv->drm, "SWSCI request already in progress\n"); return -EBUSY; } @@ -335,7 +311,7 @@ static int swsci(struct drm_i915_private *dev_priv, /* Poll for the result. */ #define C (((scic = swsci->scic) & SWSCI_SCIC_INDICATOR) == 0) if (wait_for(C, dslp)) { - DRM_DEBUG_DRIVER("SWSCI request timed out\n"); + drm_dbg(&dev_priv->drm, "SWSCI request timed out\n"); return -ETIMEDOUT; } @@ -344,7 +320,7 @@ static int swsci(struct drm_i915_private *dev_priv, /* Note: scic == 0 is an error! */ if (scic != SWSCI_SCIC_EXIT_STATUS_SUCCESS) { - DRM_DEBUG_DRIVER("SWSCI request error %u\n", scic); + drm_dbg(&dev_priv->drm, "SWSCI request error %u\n", scic); return -EIO; } @@ -403,8 +379,9 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL; break; default: - WARN_ONCE(1, "unsupported intel_encoder type %d\n", - intel_encoder->type); + drm_WARN_ONCE(&dev_priv->drm, 1, + "unsupported intel_encoder type %d\n", + intel_encoder->type); return -EINVAL; } @@ -448,10 +425,11 @@ static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp) struct opregion_asle *asle = dev_priv->opregion.asle; struct drm_device *dev = &dev_priv->drm; - DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp); + drm_dbg(&dev_priv->drm, "bclp = 0x%08x\n", bclp); if (acpi_video_get_backlight_type() == acpi_backlight_native) { - DRM_DEBUG_KMS("opregion backlight request ignored\n"); + drm_dbg_kms(&dev_priv->drm, + "opregion backlight request ignored\n"); return 0; } @@ -468,7 +446,8 @@ static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp) * Update backlight on all connectors that support backlight (usually * only one). */ - DRM_DEBUG_KMS("updating opregion backlight %d/255\n", bclp); + drm_dbg_kms(&dev_priv->drm, "updating opregion backlight %d/255\n", + bclp); drm_connector_list_iter_begin(dev, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) intel_panel_set_backlight_acpi(connector->base.state, bclp, 255); @@ -485,13 +464,13 @@ static u32 asle_set_als_illum(struct drm_i915_private *dev_priv, u32 alsi) { /* alsi is the current ALS reading in lux. 0 indicates below sensor range, 0xffff indicates above sensor range. 1-0xfffe are valid */ - DRM_DEBUG_DRIVER("Illum is not supported\n"); + drm_dbg(&dev_priv->drm, "Illum is not supported\n"); return ASLC_ALS_ILLUM_FAILED; } static u32 asle_set_pwm_freq(struct drm_i915_private *dev_priv, u32 pfmb) { - DRM_DEBUG_DRIVER("PWM freq is not supported\n"); + drm_dbg(&dev_priv->drm, "PWM freq is not supported\n"); return ASLC_PWM_FREQ_FAILED; } @@ -499,30 +478,36 @@ static u32 asle_set_pfit(struct drm_i915_private *dev_priv, u32 pfit) { /* Panel fitting is currently controlled by the X code, so this is a noop until modesetting support works fully */ - DRM_DEBUG_DRIVER("Pfit is not supported\n"); + drm_dbg(&dev_priv->drm, "Pfit is not supported\n"); return ASLC_PFIT_FAILED; } static u32 asle_set_supported_rotation_angles(struct drm_i915_private *dev_priv, u32 srot) { - DRM_DEBUG_DRIVER("SROT is not supported\n"); + drm_dbg(&dev_priv->drm, "SROT is not supported\n"); return ASLC_ROTATION_ANGLES_FAILED; } static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer) { if (!iuer) - DRM_DEBUG_DRIVER("Button array event is not supported (nothing)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (nothing)\n"); if (iuer & ASLE_IUER_ROTATION_LOCK_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (rotation lock)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (rotation lock)\n"); if (iuer & ASLE_IUER_VOLUME_DOWN_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (volume down)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (volume down)\n"); if (iuer & ASLE_IUER_VOLUME_UP_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (volume up)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (volume up)\n"); if (iuer & ASLE_IUER_WINDOWS_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (windows)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (windows)\n"); if (iuer & ASLE_IUER_POWER_BTN) - DRM_DEBUG_DRIVER("Button array event is not supported (power)\n"); + drm_dbg(&dev_priv->drm, + "Button array event is not supported (power)\n"); return ASLC_BUTTON_ARRAY_FAILED; } @@ -530,9 +515,11 @@ static u32 asle_set_button_array(struct drm_i915_private *dev_priv, u32 iuer) static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer) { if (iuer & ASLE_IUER_CONVERTIBLE) - DRM_DEBUG_DRIVER("Convertible is not supported (clamshell)\n"); + drm_dbg(&dev_priv->drm, + "Convertible is not supported (clamshell)\n"); else - DRM_DEBUG_DRIVER("Convertible is not supported (slate)\n"); + drm_dbg(&dev_priv->drm, + "Convertible is not supported (slate)\n"); return ASLC_CONVERTIBLE_FAILED; } @@ -540,16 +527,17 @@ static u32 asle_set_convertible(struct drm_i915_private *dev_priv, u32 iuer) static u32 asle_set_docking(struct drm_i915_private *dev_priv, u32 iuer) { if (iuer & ASLE_IUER_DOCKING) - DRM_DEBUG_DRIVER("Docking is not supported (docked)\n"); + drm_dbg(&dev_priv->drm, "Docking is not supported (docked)\n"); else - DRM_DEBUG_DRIVER("Docking is not supported (undocked)\n"); + drm_dbg(&dev_priv->drm, + "Docking is not supported (undocked)\n"); return ASLC_DOCKING_FAILED; } static u32 asle_isct_state(struct drm_i915_private *dev_priv) { - DRM_DEBUG_DRIVER("ISCT is not supported\n"); + drm_dbg(&dev_priv->drm, "ISCT is not supported\n"); return ASLC_ISCT_STATE_FAILED; } @@ -569,8 +557,8 @@ static void asle_work(struct work_struct *work) aslc_req = asle->aslc; if (!(aslc_req & ASLC_REQ_MSK)) { - DRM_DEBUG_DRIVER("No request on ASLC interrupt 0x%08x\n", - aslc_req); + drm_dbg(&dev_priv->drm, + "No request on ASLC interrupt 0x%08x\n", aslc_req); return; } @@ -662,54 +650,12 @@ static void set_did(struct intel_opregion *opregion, int i, u32 val) } } -static u32 acpi_display_type(struct intel_connector *connector) -{ - u32 display_type; - - switch (connector->base.connector_type) { - case DRM_MODE_CONNECTOR_VGA: - case DRM_MODE_CONNECTOR_DVIA: - display_type = ACPI_DISPLAY_TYPE_VGA; - break; - case DRM_MODE_CONNECTOR_Composite: - case DRM_MODE_CONNECTOR_SVIDEO: - case DRM_MODE_CONNECTOR_Component: - case DRM_MODE_CONNECTOR_9PinDIN: - case DRM_MODE_CONNECTOR_TV: - display_type = ACPI_DISPLAY_TYPE_TV; - break; - case DRM_MODE_CONNECTOR_DVII: - case DRM_MODE_CONNECTOR_DVID: - case DRM_MODE_CONNECTOR_DisplayPort: - case DRM_MODE_CONNECTOR_HDMIA: - case DRM_MODE_CONNECTOR_HDMIB: - display_type = ACPI_DISPLAY_TYPE_EXTERNAL_DIGITAL; - break; - case DRM_MODE_CONNECTOR_LVDS: - case DRM_MODE_CONNECTOR_eDP: - case DRM_MODE_CONNECTOR_DSI: - display_type = ACPI_DISPLAY_TYPE_INTERNAL_DIGITAL; - break; - case DRM_MODE_CONNECTOR_Unknown: - case DRM_MODE_CONNECTOR_VIRTUAL: - display_type = ACPI_DISPLAY_TYPE_OTHER; - break; - default: - MISSING_CASE(connector->base.connector_type); - display_type = ACPI_DISPLAY_TYPE_OTHER; - break; - } - - return display_type; -} - static void intel_didl_outputs(struct drm_i915_private *dev_priv) { struct intel_opregion *opregion = &dev_priv->opregion; struct intel_connector *connector; struct drm_connector_list_iter conn_iter; int i = 0, max_outputs; - int display_index[16] = {}; /* * In theory, did2, the extended didl, gets added at opregion version @@ -721,29 +667,22 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv) max_outputs = ARRAY_SIZE(opregion->acpi->didl) + ARRAY_SIZE(opregion->acpi->did2); + intel_acpi_device_id_update(dev_priv); + drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); for_each_intel_connector_iter(connector, &conn_iter) { - u32 device_id, type; - - device_id = acpi_display_type(connector); - - /* Use display type specific display index. */ - type = (device_id & ACPI_DISPLAY_TYPE_MASK) - >> ACPI_DISPLAY_TYPE_SHIFT; - device_id |= display_index[type]++ << ACPI_DISPLAY_INDEX_SHIFT; - - connector->acpi_device_id = device_id; if (i < max_outputs) - set_did(opregion, i, device_id); + set_did(opregion, i, connector->acpi_device_id); i++; } drm_connector_list_iter_end(&conn_iter); - DRM_DEBUG_KMS("%d outputs detected\n", i); + drm_dbg_kms(&dev_priv->drm, "%d outputs detected\n", i); if (i > max_outputs) - DRM_ERROR("More than %d outputs in connector list\n", - max_outputs); + drm_err(&dev_priv->drm, + "More than %d outputs in connector list\n", + max_outputs); /* If fewer than max outputs, the list must be null terminated */ if (i < max_outputs) @@ -823,7 +762,9 @@ static void swsci_setup(struct drm_i915_private *dev_priv) if (requested_callbacks) { u32 req = opregion->swsci_sbcb_sub_functions; if ((req & tmp) != req) - DRM_DEBUG_DRIVER("SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n", req, tmp); + drm_dbg(&dev_priv->drm, + "SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x)\n", + req, tmp); /* XXX: for now, trust the requested callbacks */ /* opregion->swsci_sbcb_sub_functions &= tmp; */ } else { @@ -831,9 +772,10 @@ static void swsci_setup(struct drm_i915_private *dev_priv) } } - DRM_DEBUG_DRIVER("SWSCI GBDA callbacks %08x, SBCB callbacks %08x\n", - opregion->swsci_gbda_sub_functions, - opregion->swsci_sbcb_sub_functions); + drm_dbg(&dev_priv->drm, + "SWSCI GBDA callbacks %08x, SBCB callbacks %08x\n", + opregion->swsci_gbda_sub_functions, + opregion->swsci_sbcb_sub_functions); } static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id) @@ -867,15 +809,17 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) ret = request_firmware(&fw, name, &dev_priv->drm.pdev->dev); if (ret) { - DRM_ERROR("Requesting VBT firmware \"%s\" failed (%d)\n", - name, ret); + drm_err(&dev_priv->drm, + "Requesting VBT firmware \"%s\" failed (%d)\n", + name, ret); return ret; } if (intel_bios_is_valid_vbt(fw->data, fw->size)) { opregion->vbt_firmware = kmemdup(fw->data, fw->size, GFP_KERNEL); if (opregion->vbt_firmware) { - DRM_DEBUG_KMS("Found valid VBT firmware \"%s\"\n", name); + drm_dbg_kms(&dev_priv->drm, + "Found valid VBT firmware \"%s\"\n", name); opregion->vbt = opregion->vbt_firmware; opregion->vbt_size = fw->size; ret = 0; @@ -883,7 +827,8 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv) ret = -ENOMEM; } } else { - DRM_DEBUG_KMS("Invalid VBT firmware \"%s\"\n", name); + drm_dbg_kms(&dev_priv->drm, "Invalid VBT firmware \"%s\"\n", + name); ret = -EINVAL; } @@ -910,9 +855,10 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400); pci_read_config_dword(pdev, ASLS, &asls); - DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls); + drm_dbg(&dev_priv->drm, "graphic opregion physical addr: 0x%x\n", + asls); if (asls == 0) { - DRM_DEBUG_DRIVER("ACPI OpRegion not supported!\n"); + drm_dbg(&dev_priv->drm, "ACPI OpRegion not supported!\n"); return -ENOTSUPP; } @@ -925,21 +871,21 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) memcpy(buf, base, sizeof(buf)); if (memcmp(buf, OPREGION_SIGNATURE, 16)) { - DRM_DEBUG_DRIVER("opregion signature mismatch\n"); + drm_dbg(&dev_priv->drm, "opregion signature mismatch\n"); err = -EINVAL; goto err_out; } opregion->header = base; opregion->lid_state = base + ACPI_CLID; - DRM_DEBUG_DRIVER("ACPI OpRegion version %u.%u.%u\n", - opregion->header->over.major, - opregion->header->over.minor, - opregion->header->over.revision); + drm_dbg(&dev_priv->drm, "ACPI OpRegion version %u.%u.%u\n", + opregion->header->over.major, + opregion->header->over.minor, + opregion->header->over.revision); mboxes = opregion->header->mboxes; if (mboxes & MBOX_ACPI) { - DRM_DEBUG_DRIVER("Public ACPI methods supported\n"); + drm_dbg(&dev_priv->drm, "Public ACPI methods supported\n"); opregion->acpi = base + OPREGION_ACPI_OFFSET; /* * Indicate we handle monitor hotplug events ourselves so we do @@ -951,20 +897,20 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) } if (mboxes & MBOX_SWSCI) { - DRM_DEBUG_DRIVER("SWSCI supported\n"); + drm_dbg(&dev_priv->drm, "SWSCI supported\n"); opregion->swsci = base + OPREGION_SWSCI_OFFSET; swsci_setup(dev_priv); } if (mboxes & MBOX_ASLE) { - DRM_DEBUG_DRIVER("ASLE supported\n"); + drm_dbg(&dev_priv->drm, "ASLE supported\n"); opregion->asle = base + OPREGION_ASLE_OFFSET; opregion->asle->ardy = ASLE_ARDY_NOT_READY; } if (mboxes & MBOX_ASLE_EXT) - DRM_DEBUG_DRIVER("ASLE extension supported\n"); + drm_dbg(&dev_priv->drm, "ASLE extension supported\n"); if (intel_load_vbt_firmware(dev_priv) == 0) goto out; @@ -984,7 +930,7 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) */ if (opregion->header->over.major > 2 || opregion->header->over.minor >= 1) { - WARN_ON(rvda < OPREGION_SIZE); + drm_WARN_ON(&dev_priv->drm, rvda < OPREGION_SIZE); rvda += asls; } @@ -995,12 +941,14 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) vbt = opregion->rvda; vbt_size = opregion->asle->rvds; if (intel_bios_is_valid_vbt(vbt, vbt_size)) { - DRM_DEBUG_KMS("Found valid VBT in ACPI OpRegion (RVDA)\n"); + drm_dbg_kms(&dev_priv->drm, + "Found valid VBT in ACPI OpRegion (RVDA)\n"); opregion->vbt = vbt; opregion->vbt_size = vbt_size; goto out; } else { - DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (RVDA)\n"); + drm_dbg_kms(&dev_priv->drm, + "Invalid VBT in ACPI OpRegion (RVDA)\n"); memunmap(opregion->rvda); opregion->rvda = NULL; } @@ -1018,11 +966,13 @@ int intel_opregion_setup(struct drm_i915_private *dev_priv) OPREGION_ASLE_EXT_OFFSET : OPREGION_SIZE; vbt_size -= OPREGION_VBT_OFFSET; if (intel_bios_is_valid_vbt(vbt, vbt_size)) { - DRM_DEBUG_KMS("Found valid VBT in ACPI OpRegion (Mailbox #4)\n"); + drm_dbg_kms(&dev_priv->drm, + "Found valid VBT in ACPI OpRegion (Mailbox #4)\n"); opregion->vbt = vbt; opregion->vbt_size = vbt_size; } else { - DRM_DEBUG_KMS("Invalid VBT in ACPI OpRegion (Mailbox #4)\n"); + drm_dbg_kms(&dev_priv->drm, + "Invalid VBT in ACPI OpRegion (Mailbox #4)\n"); } out: @@ -1058,20 +1008,22 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) ret = swsci(dev_priv, SWSCI_GBDA_PANEL_DETAILS, 0x0, &panel_details); if (ret) { - DRM_DEBUG_KMS("Failed to get panel details from OpRegion (%d)\n", - ret); + drm_dbg_kms(&dev_priv->drm, + "Failed to get panel details from OpRegion (%d)\n", + ret); return ret; } ret = (panel_details >> 8) & 0xff; if (ret > 0x10) { - DRM_DEBUG_KMS("Invalid OpRegion panel type 0x%x\n", ret); + drm_dbg_kms(&dev_priv->drm, + "Invalid OpRegion panel type 0x%x\n", ret); return -EINVAL; } /* fall back to VBT panel type? */ if (ret == 0x0) { - DRM_DEBUG_KMS("No panel type in OpRegion\n"); + drm_dbg_kms(&dev_priv->drm, "No panel type in OpRegion\n"); return -ENODEV; } @@ -1081,7 +1033,8 @@ intel_opregion_get_panel_type(struct drm_i915_private *dev_priv) * via a quirk list :( */ if (!dmi_check_system(intel_use_opregion_panel_type)) { - DRM_DEBUG_KMS("Ignoring OpRegion panel type (%d)\n", ret - 1); + drm_dbg_kms(&dev_priv->drm, + "Ignoring OpRegion panel type (%d)\n", ret - 1); return -ENODEV; } diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index e40c3a0e2cd7..481187223101 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -27,7 +27,6 @@ */ #include <drm/drm_fourcc.h> -#include <drm/i915_drm.h> #include "gem/i915_gem_pm.h" #include "gt/intel_ring.h" @@ -204,9 +203,10 @@ static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, /* WA_OVERLAY_CLKGATE:alm */ if (enable) - I915_WRITE(DSPCLK_GATE_D, 0); + intel_de_write(dev_priv, DSPCLK_GATE_D, 0); else - I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); + intel_de_write(dev_priv, DSPCLK_GATE_D, + OVRUNIT_CLOCK_GATE_DISABLE); /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ pci_bus_read_config_byte(pdev->bus, @@ -247,7 +247,7 @@ static int intel_overlay_on(struct intel_overlay *overlay) struct i915_request *rq; u32 *cs; - WARN_ON(overlay->active); + drm_WARN_ON(&dev_priv->drm, overlay->active); rq = alloc_request(overlay, NULL); if (IS_ERR(rq)) @@ -315,15 +315,15 @@ static int intel_overlay_continue(struct intel_overlay *overlay, u32 flip_addr = overlay->flip_addr; u32 tmp, *cs; - WARN_ON(!overlay->active); + drm_WARN_ON(&dev_priv->drm, !overlay->active); if (load_polyphase_filter) flip_addr |= OFC_UPDATE; /* check for underruns */ - tmp = I915_READ(DOVSTA); + tmp = intel_de_read(dev_priv, DOVSTA); if (tmp & (1 << 17)) - DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); + drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp); rq = alloc_request(overlay, NULL); if (IS_ERR(rq)) @@ -456,7 +456,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay) if (!overlay->old_vma) return 0; - if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { + if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { intel_overlay_release_old_vid_tail(overlay); return 0; } @@ -759,7 +759,8 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, struct i915_vma *vma; int ret, tmp_width; - WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); + drm_WARN_ON(&dev_priv->drm, + !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); ret = intel_overlay_release_old_vid(overlay); if (ret != 0) @@ -857,7 +858,8 @@ int intel_overlay_switch_off(struct intel_overlay *overlay) struct drm_i915_private *dev_priv = overlay->i915; int ret; - WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); + drm_WARN_ON(&dev_priv->drm, + !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); ret = intel_overlay_recover_from_interrupt(overlay); if (ret != 0) @@ -891,7 +893,7 @@ static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, static void update_pfit_vscale_ratio(struct intel_overlay *overlay) { struct drm_i915_private *dev_priv = overlay->i915; - u32 pfit_control = I915_READ(PFIT_CONTROL); + u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL); u32 ratio; /* XXX: This is not the same logic as in the xorg driver, but more in @@ -899,12 +901,12 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) */ if (INTEL_GEN(dev_priv) >= 4) { /* on i965 use the PGM reg to read out the autoscaler values */ - ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; + ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; } else { if (pfit_control & VERT_AUTO_SCALE) - ratio = I915_READ(PFIT_AUTO_RATIOS); + ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); else - ratio = I915_READ(PFIT_PGM_RATIOS); + ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS); ratio >>= PFIT_VERT_SCALE_SHIFT; } @@ -1066,7 +1068,7 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, overlay = dev_priv->overlay; if (!overlay) { - DRM_DEBUG("userspace bug: no overlay\n"); + drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); return -ENODEV; } @@ -1090,7 +1092,8 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, drm_modeset_lock_all(dev); if (i915_gem_object_is_tiled(new_bo)) { - DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); + drm_dbg_kms(&dev_priv->drm, + "buffer used for overlay image can not be tiled\n"); ret = -EINVAL; goto out_unlock; } @@ -1225,7 +1228,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, overlay = dev_priv->overlay; if (!overlay) { - DRM_DEBUG("userspace bug: no overlay\n"); + drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n"); return -ENODEV; } @@ -1239,12 +1242,12 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, attrs->saturation = overlay->saturation; if (!IS_GEN(dev_priv, 2)) { - attrs->gamma0 = I915_READ(OGAMC0); - attrs->gamma1 = I915_READ(OGAMC1); - attrs->gamma2 = I915_READ(OGAMC2); - attrs->gamma3 = I915_READ(OGAMC3); - attrs->gamma4 = I915_READ(OGAMC4); - attrs->gamma5 = I915_READ(OGAMC5); + attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); + attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); + attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); + attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); + attrs->gamma4 = intel_de_read(dev_priv, OGAMC4); + attrs->gamma5 = intel_de_read(dev_priv, OGAMC5); } } else { if (attrs->brightness < -128 || attrs->brightness > 127) @@ -1274,12 +1277,12 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, if (ret) goto out_unlock; - I915_WRITE(OGAMC0, attrs->gamma0); - I915_WRITE(OGAMC1, attrs->gamma1); - I915_WRITE(OGAMC2, attrs->gamma2); - I915_WRITE(OGAMC3, attrs->gamma3); - I915_WRITE(OGAMC4, attrs->gamma4); - I915_WRITE(OGAMC5, attrs->gamma5); + intel_de_write(dev_priv, OGAMC0, attrs->gamma0); + intel_de_write(dev_priv, OGAMC1, attrs->gamma1); + intel_de_write(dev_priv, OGAMC2, attrs->gamma2); + intel_de_write(dev_priv, OGAMC3, attrs->gamma3); + intel_de_write(dev_priv, OGAMC4, attrs->gamma4); + intel_de_write(dev_priv, OGAMC5, attrs->gamma5); } } overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; @@ -1369,7 +1372,7 @@ void intel_overlay_setup(struct drm_i915_private *dev_priv) update_reg_attrs(overlay, overlay->regs); dev_priv->overlay = overlay; - DRM_INFO("Initialized overlay support.\n"); + drm_info(&dev_priv->drm, "Initialized overlay support.\n"); return; out_free: @@ -1389,7 +1392,7 @@ void intel_overlay_cleanup(struct drm_i915_private *dev_priv) * Furthermore modesetting teardown happens beforehand so the * hardware should be off already. */ - WARN_ON(overlay->active); + drm_WARN_ON(&dev_priv->drm, overlay->active); i915_gem_object_put(overlay->reg_bo); i915_active_fini(&overlay->last_flip); @@ -1419,8 +1422,8 @@ intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) if (error == NULL) return NULL; - error->dovsta = I915_READ(DOVSTA); - error->isr = I915_READ(GEN2_ISR); + error->dovsta = intel_de_read(dev_priv, DOVSTA); + error->isr = intel_de_read(dev_priv, GEN2_ISR); error->base = overlay->flip_addr; memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 7b3ec6eb3382..276f43870802 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -96,8 +96,9 @@ intel_panel_edid_downclock_mode(struct intel_connector *connector, if (!downclock_mode) return NULL; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] using downclock mode from EDID: ", - connector->base.base.id, connector->base.name); + drm_dbg_kms(&dev_priv->drm, + "[CONNECTOR:%d:%s] using downclock mode from EDID: ", + connector->base.base.id, connector->base.name); drm_mode_debug_printmodeline(downclock_mode); return downclock_mode; @@ -122,8 +123,9 @@ intel_panel_edid_fixed_mode(struct intel_connector *connector) if (!fixed_mode) return NULL; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] using preferred mode from EDID: ", - connector->base.base.id, connector->base.name); + drm_dbg_kms(&dev_priv->drm, + "[CONNECTOR:%d:%s] using preferred mode from EDID: ", + connector->base.base.id, connector->base.name); drm_mode_debug_printmodeline(fixed_mode); return fixed_mode; @@ -138,8 +140,9 @@ intel_panel_edid_fixed_mode(struct intel_connector *connector) fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] using first mode from EDID: ", - connector->base.base.id, connector->base.name); + drm_dbg_kms(&dev_priv->drm, + "[CONNECTOR:%d:%s] using first mode from EDID: ", + connector->base.base.id, connector->base.name); drm_mode_debug_printmodeline(fixed_mode); return fixed_mode; @@ -162,8 +165,8 @@ intel_panel_vbt_fixed_mode(struct intel_connector *connector) fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s] using mode from VBT: ", - connector->base.base.id, connector->base.name); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] using mode from VBT: ", + connector->base.base.id, connector->base.name); drm_mode_debug_printmodeline(fixed_mode); info->width_mm = fixed_mode->width_mm; @@ -423,15 +426,15 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, } break; default: - WARN(1, "bad panel fit mode: %d\n", fitting_mode); + drm_WARN(&dev_priv->drm, 1, "bad panel fit mode: %d\n", + fitting_mode); return; } /* 965+ wants fuzzy fitting */ /* FIXME: handle multiple panels by failing gracefully */ if (INTEL_GEN(dev_priv) >= 4) - pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | - PFIT_FILTER_FUZZY); + pfit_control |= PFIT_PIPE(intel_crtc->pipe) | PFIT_FILTER_FUZZY; out: if ((pfit_control & PFIT_ENABLE) == 0) { @@ -520,7 +523,7 @@ static u32 intel_panel_compute_brightness(struct intel_connector *connector, struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; - WARN_ON(panel->backlight.max == 0); + drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); if (i915_modparams.invert_brightness < 0) return val; @@ -537,14 +540,14 @@ static u32 lpt_get_backlight(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; + return intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; } static u32 pch_get_backlight(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; + return intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; } static u32 i9xx_get_backlight(struct intel_connector *connector) @@ -553,7 +556,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector) struct intel_panel *panel = &connector->panel; u32 val; - val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; + val = intel_de_read(dev_priv, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; if (INTEL_GEN(dev_priv) < 4) val >>= 1; @@ -569,10 +572,10 @@ static u32 i9xx_get_backlight(struct intel_connector *connector) static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum pipe pipe) { - if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) + if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) return 0; - return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; + return intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; } static u32 vlv_get_backlight(struct intel_connector *connector) @@ -588,7 +591,8 @@ static u32 bxt_get_backlight(struct intel_connector *connector) struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; - return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); + return intel_de_read(dev_priv, + BXT_BLC_PWM_DUTY(panel->backlight.controller)); } static u32 pwm_get_backlight(struct intel_connector *connector) @@ -605,8 +609,8 @@ static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; - I915_WRITE(BLC_PWM_PCH_CTL2, val | level); + u32 val = intel_de_read(dev_priv, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; + intel_de_write(dev_priv, BLC_PWM_PCH_CTL2, val | level); } static void pch_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -615,8 +619,8 @@ static void pch_set_backlight(const struct drm_connector_state *conn_state, u32 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); u32 tmp; - tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; - I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); + tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; + intel_de_write(dev_priv, BLC_PWM_CPU_CTL, tmp | level); } static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -626,7 +630,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 struct intel_panel *panel = &connector->panel; u32 tmp, mask; - WARN_ON(panel->backlight.max == 0); + drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); if (panel->backlight.combination_mode) { u8 lbpc; @@ -643,8 +647,8 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV; } - tmp = I915_READ(BLC_PWM_CTL) & ~mask; - I915_WRITE(BLC_PWM_CTL, tmp | level); + tmp = intel_de_read(dev_priv, BLC_PWM_CTL) & ~mask; + intel_de_write(dev_priv, BLC_PWM_CTL, tmp | level); } static void vlv_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -654,8 +658,8 @@ static void vlv_set_backlight(const struct drm_connector_state *conn_state, u32 enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe; u32 tmp; - tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; - I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); + tmp = intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; + intel_de_write(dev_priv, VLV_BLC_PWM_CTL(pipe), tmp | level); } static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -664,7 +668,8 @@ static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); struct intel_panel *panel = &connector->panel; - I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level); + intel_de_write(dev_priv, + BXT_BLC_PWM_DUTY(panel->backlight.controller), level); } static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) @@ -709,7 +714,7 @@ void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state mutex_lock(&dev_priv->backlight_lock); - WARN_ON(panel->backlight.max == 0); + drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); hw_level = clamp_user_to_hw(connector, user_level, user_max); panel->backlight.level = hw_level; @@ -742,14 +747,16 @@ static void lpt_disable_backlight(const struct drm_connector_state *old_conn_sta * This needs rework if we need to add support for CPU PWM on PCH split * platforms. */ - tmp = I915_READ(BLC_PWM_CPU_CTL2); + tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); if (tmp & BLM_PWM_ENABLE) { - DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n"); - I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); + drm_dbg_kms(&dev_priv->drm, + "cpu backlight was enabled, disabling\n"); + intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, + tmp & ~BLM_PWM_ENABLE); } - tmp = I915_READ(BLC_PWM_PCH_CTL1); - I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); + tmp = intel_de_read(dev_priv, BLC_PWM_PCH_CTL1); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); } static void pch_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -760,11 +767,11 @@ static void pch_disable_backlight(const struct drm_connector_state *old_conn_sta intel_panel_actually_set_backlight(old_conn_state, 0); - tmp = I915_READ(BLC_PWM_CPU_CTL2); - I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); + tmp = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); + intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); - tmp = I915_READ(BLC_PWM_PCH_CTL1); - I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); + tmp = intel_de_read(dev_priv, BLC_PWM_PCH_CTL1); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); } static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -779,8 +786,8 @@ static void i965_disable_backlight(const struct drm_connector_state *old_conn_st intel_panel_actually_set_backlight(old_conn_state, 0); - tmp = I915_READ(BLC_PWM_CTL2); - I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); + tmp = intel_de_read(dev_priv, BLC_PWM_CTL2); + intel_de_write(dev_priv, BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); } static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -792,8 +799,9 @@ static void vlv_disable_backlight(const struct drm_connector_state *old_conn_sta intel_panel_actually_set_backlight(old_conn_state, 0); - tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe)); - I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE); + tmp = intel_de_read(dev_priv, VLV_BLC_PWM_CTL2(pipe)); + intel_de_write(dev_priv, VLV_BLC_PWM_CTL2(pipe), + tmp & ~BLM_PWM_ENABLE); } static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -805,14 +813,15 @@ static void bxt_disable_backlight(const struct drm_connector_state *old_conn_sta intel_panel_actually_set_backlight(old_conn_state, 0); - tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), - tmp & ~BXT_BLC_PWM_ENABLE); + tmp = intel_de_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); + intel_de_write(dev_priv, BXT_BLC_PWM_CTL(panel->backlight.controller), + tmp & ~BXT_BLC_PWM_ENABLE); if (panel->backlight.controller == 1) { - val = I915_READ(UTIL_PIN_CTL); + val = intel_de_read(dev_priv, UTIL_PIN_CTL); val &= ~UTIL_PIN_ENABLE; - I915_WRITE(UTIL_PIN_CTL, val); + intel_de_write(dev_priv, UTIL_PIN_CTL, val); } } @@ -825,9 +834,10 @@ static void cnp_disable_backlight(const struct drm_connector_state *old_conn_sta intel_panel_actually_set_backlight(old_conn_state, 0); - tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), - tmp & ~BXT_BLC_PWM_ENABLE); + tmp = intel_de_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); + intel_de_write(dev_priv, BXT_BLC_PWM_CTL(panel->backlight.controller), + tmp & ~BXT_BLC_PWM_ENABLE); } static void pwm_disable_backlight(const struct drm_connector_state *old_conn_state) @@ -857,7 +867,8 @@ void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_st * another client is not activated. */ if (dev_priv->drm.switch_power_state == DRM_SWITCH_POWER_CHANGING) { - DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); + drm_dbg(&dev_priv->drm, + "Skipping backlight disable on vga switch\n"); return; } @@ -879,31 +890,31 @@ static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, struct intel_panel *panel = &connector->panel; u32 pch_ctl1, pch_ctl2, schicken; - pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(dev_priv, BLC_PWM_PCH_CTL1); if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { - DRM_DEBUG_KMS("pch backlight already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "pch backlight already enabled\n"); pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; - I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, pch_ctl1); } if (HAS_PCH_LPT(dev_priv)) { - schicken = I915_READ(SOUTH_CHICKEN2); + schicken = intel_de_read(dev_priv, SOUTH_CHICKEN2); if (panel->backlight.alternate_pwm_increment) schicken |= LPT_PWM_GRANULARITY; else schicken &= ~LPT_PWM_GRANULARITY; - I915_WRITE(SOUTH_CHICKEN2, schicken); + intel_de_write(dev_priv, SOUTH_CHICKEN2, schicken); } else { - schicken = I915_READ(SOUTH_CHICKEN1); + schicken = intel_de_read(dev_priv, SOUTH_CHICKEN1); if (panel->backlight.alternate_pwm_increment) schicken |= SPT_PWM_GRANULARITY; else schicken &= ~SPT_PWM_GRANULARITY; - I915_WRITE(SOUTH_CHICKEN1, schicken); + intel_de_write(dev_priv, SOUTH_CHICKEN1, schicken); } pch_ctl2 = panel->backlight.max << 16; - I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL2, pch_ctl2); pch_ctl1 = 0; if (panel->backlight.active_low_pwm) @@ -913,9 +924,10 @@ static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state, if (HAS_PCH_LPT(dev_priv)) pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE; - I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); - POSTING_READ(BLC_PWM_PCH_CTL1); - I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, + pch_ctl1 | BLM_PCH_PWM_ENABLE); /* This won't stick until the above enable. */ intel_panel_actually_set_backlight(conn_state, panel->backlight.level); @@ -930,41 +942,42 @@ static void pch_enable_backlight(const struct intel_crtc_state *crtc_state, enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 cpu_ctl2, pch_ctl1, pch_ctl2; - cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); + cpu_ctl2 = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); if (cpu_ctl2 & BLM_PWM_ENABLE) { - DRM_DEBUG_KMS("cpu backlight already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "cpu backlight already enabled\n"); cpu_ctl2 &= ~BLM_PWM_ENABLE; - I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); + intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, cpu_ctl2); } - pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(dev_priv, BLC_PWM_PCH_CTL1); if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { - DRM_DEBUG_KMS("pch backlight already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "pch backlight already enabled\n"); pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; - I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, pch_ctl1); } if (cpu_transcoder == TRANSCODER_EDP) cpu_ctl2 = BLM_TRANSCODER_EDP; else cpu_ctl2 = BLM_PIPE(cpu_transcoder); - I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); - POSTING_READ(BLC_PWM_CPU_CTL2); - I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); + intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, cpu_ctl2); + intel_de_posting_read(dev_priv, BLC_PWM_CPU_CTL2); + intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); /* This won't stick until the above enable. */ intel_panel_actually_set_backlight(conn_state, panel->backlight.level); pch_ctl2 = panel->backlight.max << 16; - I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL2, pch_ctl2); pch_ctl1 = 0; if (panel->backlight.active_low_pwm) pch_ctl1 |= BLM_PCH_POLARITY; - I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); - POSTING_READ(BLC_PWM_PCH_CTL1); - I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, pch_ctl1); + intel_de_posting_read(dev_priv, BLC_PWM_PCH_CTL1); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, + pch_ctl1 | BLM_PCH_PWM_ENABLE); } static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -975,10 +988,10 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, struct intel_panel *panel = &connector->panel; u32 ctl, freq; - ctl = I915_READ(BLC_PWM_CTL); + ctl = intel_de_read(dev_priv, BLC_PWM_CTL); if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { - DRM_DEBUG_KMS("backlight already enabled\n"); - I915_WRITE(BLC_PWM_CTL, 0); + drm_dbg_kms(&dev_priv->drm, "backlight already enabled\n"); + intel_de_write(dev_priv, BLC_PWM_CTL, 0); } freq = panel->backlight.max; @@ -991,8 +1004,8 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, if (IS_PINEVIEW(dev_priv) && panel->backlight.active_low_pwm) ctl |= BLM_POLARITY_PNV; - I915_WRITE(BLC_PWM_CTL, ctl); - POSTING_READ(BLC_PWM_CTL); + intel_de_write(dev_priv, BLC_PWM_CTL, ctl); + intel_de_posting_read(dev_priv, BLC_PWM_CTL); /* XXX: combine this into above write? */ intel_panel_actually_set_backlight(conn_state, panel->backlight.level); @@ -1003,7 +1016,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, * that has backlight. */ if (IS_GEN(dev_priv, 2)) - I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); + intel_de_write(dev_priv, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); } static void i965_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -1015,11 +1028,11 @@ static void i965_enable_backlight(const struct intel_crtc_state *crtc_state, enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe; u32 ctl, ctl2, freq; - ctl2 = I915_READ(BLC_PWM_CTL2); + ctl2 = intel_de_read(dev_priv, BLC_PWM_CTL2); if (ctl2 & BLM_PWM_ENABLE) { - DRM_DEBUG_KMS("backlight already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "backlight already enabled\n"); ctl2 &= ~BLM_PWM_ENABLE; - I915_WRITE(BLC_PWM_CTL2, ctl2); + intel_de_write(dev_priv, BLC_PWM_CTL2, ctl2); } freq = panel->backlight.max; @@ -1027,16 +1040,16 @@ static void i965_enable_backlight(const struct intel_crtc_state *crtc_state, freq /= 0xff; ctl = freq << 16; - I915_WRITE(BLC_PWM_CTL, ctl); + intel_de_write(dev_priv, BLC_PWM_CTL, ctl); ctl2 = BLM_PIPE(pipe); if (panel->backlight.combination_mode) ctl2 |= BLM_COMBINATION_MODE; if (panel->backlight.active_low_pwm) ctl2 |= BLM_POLARITY_I965; - I915_WRITE(BLC_PWM_CTL2, ctl2); - POSTING_READ(BLC_PWM_CTL2); - I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); + intel_de_write(dev_priv, BLC_PWM_CTL2, ctl2); + intel_de_posting_read(dev_priv, BLC_PWM_CTL2); + intel_de_write(dev_priv, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); intel_panel_actually_set_backlight(conn_state, panel->backlight.level); } @@ -1050,15 +1063,15 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state, enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; u32 ctl, ctl2; - ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); + ctl2 = intel_de_read(dev_priv, VLV_BLC_PWM_CTL2(pipe)); if (ctl2 & BLM_PWM_ENABLE) { - DRM_DEBUG_KMS("backlight already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "backlight already enabled\n"); ctl2 &= ~BLM_PWM_ENABLE; - I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); + intel_de_write(dev_priv, VLV_BLC_PWM_CTL2(pipe), ctl2); } ctl = panel->backlight.max << 16; - I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl); + intel_de_write(dev_priv, VLV_BLC_PWM_CTL(pipe), ctl); /* XXX: combine this into above write? */ intel_panel_actually_set_backlight(conn_state, panel->backlight.level); @@ -1066,9 +1079,10 @@ static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state, ctl2 = 0; if (panel->backlight.active_low_pwm) ctl2 |= BLM_POLARITY_I965; - I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); - POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); - I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); + intel_de_write(dev_priv, VLV_BLC_PWM_CTL2(pipe), ctl2); + intel_de_posting_read(dev_priv, VLV_BLC_PWM_CTL2(pipe)); + intel_de_write(dev_priv, VLV_BLC_PWM_CTL2(pipe), + ctl2 | BLM_PWM_ENABLE); } static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -1082,30 +1096,34 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state, /* Controller 1 uses the utility pin. */ if (panel->backlight.controller == 1) { - val = I915_READ(UTIL_PIN_CTL); + val = intel_de_read(dev_priv, UTIL_PIN_CTL); if (val & UTIL_PIN_ENABLE) { - DRM_DEBUG_KMS("util pin already enabled\n"); + drm_dbg_kms(&dev_priv->drm, + "util pin already enabled\n"); val &= ~UTIL_PIN_ENABLE; - I915_WRITE(UTIL_PIN_CTL, val); + intel_de_write(dev_priv, UTIL_PIN_CTL, val); } val = 0; if (panel->backlight.util_pin_active_low) val |= UTIL_PIN_POLARITY; - I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) | - UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE); + intel_de_write(dev_priv, UTIL_PIN_CTL, + val | UTIL_PIN_PIPE(pipe) | UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE); } - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); + pwm_ctl = intel_de_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); if (pwm_ctl & BXT_BLC_PWM_ENABLE) { - DRM_DEBUG_KMS("backlight already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "backlight already enabled\n"); pwm_ctl &= ~BXT_BLC_PWM_ENABLE; - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), - pwm_ctl); + intel_de_write(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller), + pwm_ctl); } - I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller), - panel->backlight.max); + intel_de_write(dev_priv, + BXT_BLC_PWM_FREQ(panel->backlight.controller), + panel->backlight.max); intel_panel_actually_set_backlight(conn_state, panel->backlight.level); @@ -1113,10 +1131,12 @@ static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state, if (panel->backlight.active_low_pwm) pwm_ctl |= BXT_BLC_PWM_POLARITY; - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); - POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), - pwm_ctl | BXT_BLC_PWM_ENABLE); + intel_de_write(dev_priv, BXT_BLC_PWM_CTL(panel->backlight.controller), + pwm_ctl); + intel_de_posting_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); + intel_de_write(dev_priv, BXT_BLC_PWM_CTL(panel->backlight.controller), + pwm_ctl | BXT_BLC_PWM_ENABLE); } static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -1127,16 +1147,19 @@ static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state, struct intel_panel *panel = &connector->panel; u32 pwm_ctl; - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); + pwm_ctl = intel_de_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); if (pwm_ctl & BXT_BLC_PWM_ENABLE) { - DRM_DEBUG_KMS("backlight already enabled\n"); + drm_dbg_kms(&dev_priv->drm, "backlight already enabled\n"); pwm_ctl &= ~BXT_BLC_PWM_ENABLE; - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), - pwm_ctl); + intel_de_write(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller), + pwm_ctl); } - I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller), - panel->backlight.max); + intel_de_write(dev_priv, + BXT_BLC_PWM_FREQ(panel->backlight.controller), + panel->backlight.max); intel_panel_actually_set_backlight(conn_state, panel->backlight.level); @@ -1144,10 +1167,12 @@ static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state, if (panel->backlight.active_low_pwm) pwm_ctl |= BXT_BLC_PWM_POLARITY; - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); - POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); - I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), - pwm_ctl | BXT_BLC_PWM_ENABLE); + intel_de_write(dev_priv, BXT_BLC_PWM_CTL(panel->backlight.controller), + pwm_ctl); + intel_de_posting_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); + intel_de_write(dev_priv, BXT_BLC_PWM_CTL(panel->backlight.controller), + pwm_ctl | BXT_BLC_PWM_ENABLE); } static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state, @@ -1194,7 +1219,7 @@ void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state, if (!panel->backlight.present) return; - DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); + drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(pipe)); mutex_lock(&dev_priv->backlight_lock); @@ -1219,7 +1244,7 @@ static u32 intel_panel_get_backlight(struct intel_connector *connector) mutex_unlock(&dev_priv->backlight_lock); - DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); + drm_dbg(&dev_priv->drm, "get backlight PWM = %d\n", val); return val; } @@ -1237,7 +1262,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta mutex_lock(&dev_priv->backlight_lock); - WARN_ON(panel->backlight.max == 0); + drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); hw_level = scale_user_to_hw(connector, user_level, user_max); panel->backlight.level = hw_level; @@ -1380,7 +1405,8 @@ static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz); + return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(dev_priv)->rawclk_freq), + pwm_freq_hz); } /* @@ -1441,7 +1467,8 @@ static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz * 128); + return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(dev_priv)->rawclk_freq), + pwm_freq_hz * 128); } /* @@ -1458,7 +1485,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) int clock; if (IS_PINEVIEW(dev_priv)) - clock = KHz(dev_priv->rawclk_freq); + clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq); else clock = KHz(dev_priv->cdclk.hw.cdclk); @@ -1476,7 +1503,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) int clock; if (IS_G4X(dev_priv)) - clock = KHz(dev_priv->rawclk_freq); + clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq); else clock = KHz(dev_priv->cdclk.hw.cdclk); @@ -1493,14 +1520,14 @@ static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) struct drm_i915_private *dev_priv = to_i915(connector->base.dev); int mul, clock; - if ((I915_READ(CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) { + if ((intel_de_read(dev_priv, CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) { if (IS_CHERRYVIEW(dev_priv)) clock = KHz(19200); else clock = MHz(25); mul = 16; } else { - clock = KHz(dev_priv->rawclk_freq); + clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq); mul = 128; } @@ -1515,22 +1542,26 @@ static u32 get_backlight_max_vbt(struct intel_connector *connector) u32 pwm; if (!panel->backlight.hz_to_pwm) { - DRM_DEBUG_KMS("backlight frequency conversion not supported\n"); + drm_dbg_kms(&dev_priv->drm, + "backlight frequency conversion not supported\n"); return 0; } if (pwm_freq_hz) { - DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", - pwm_freq_hz); + drm_dbg_kms(&dev_priv->drm, + "VBT defined backlight frequency %u Hz\n", + pwm_freq_hz); } else { pwm_freq_hz = 200; - DRM_DEBUG_KMS("default backlight frequency %u Hz\n", - pwm_freq_hz); + drm_dbg_kms(&dev_priv->drm, + "default backlight frequency %u Hz\n", + pwm_freq_hz); } pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz); if (!pwm) { - DRM_DEBUG_KMS("backlight frequency conversion failed\n"); + drm_dbg_kms(&dev_priv->drm, + "backlight frequency conversion failed\n"); return 0; } @@ -1546,7 +1577,7 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector) struct intel_panel *panel = &connector->panel; int min; - WARN_ON(panel->backlight.max == 0); + drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0); /* * XXX: If the vbt value is 255, it makes min equal to max, which leads @@ -1557,8 +1588,9 @@ static u32 get_backlight_min_vbt(struct intel_connector *connector) */ min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64); if (min != dev_priv->vbt.backlight.min_brightness) { - DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n", - dev_priv->vbt.backlight.min_brightness, min); + drm_dbg_kms(&dev_priv->drm, + "clamping VBT min backlight %d/255 to %d/255\n", + dev_priv->vbt.backlight.min_brightness, min); } /* vbt value is a coefficient in range [0..255] */ @@ -1573,18 +1605,18 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus bool alt, cpu_mode; if (HAS_PCH_LPT(dev_priv)) - alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; + alt = intel_de_read(dev_priv, SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; else - alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; + alt = intel_de_read(dev_priv, SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; panel->backlight.alternate_pwm_increment = alt; - pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(dev_priv, BLC_PWM_PCH_CTL1); panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; - pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); + pch_ctl2 = intel_de_read(dev_priv, BLC_PWM_PCH_CTL2); panel->backlight.max = pch_ctl2 >> 16; - cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); + cpu_ctl2 = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); if (!panel->backlight.max) panel->backlight.max = get_backlight_max_vbt(connector); @@ -1608,13 +1640,16 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus panel->backlight.max); if (cpu_mode) { - DRM_DEBUG_KMS("CPU backlight register was enabled, switching to PCH override\n"); + drm_dbg_kms(&dev_priv->drm, + "CPU backlight register was enabled, switching to PCH override\n"); /* Write converted CPU PWM value to PCH override register */ lpt_set_backlight(connector->base.state, panel->backlight.level); - I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE); + intel_de_write(dev_priv, BLC_PWM_PCH_CTL1, + pch_ctl1 | BLM_PCH_OVERRIDE_ENABLE); - I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 & ~BLM_PWM_ENABLE); + intel_de_write(dev_priv, BLC_PWM_CPU_CTL2, + cpu_ctl2 & ~BLM_PWM_ENABLE); } return 0; @@ -1626,10 +1661,10 @@ static int pch_setup_backlight(struct intel_connector *connector, enum pipe unus struct intel_panel *panel = &connector->panel; u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; - pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); + pch_ctl1 = intel_de_read(dev_priv, BLC_PWM_PCH_CTL1); panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; - pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); + pch_ctl2 = intel_de_read(dev_priv, BLC_PWM_PCH_CTL2); panel->backlight.max = pch_ctl2 >> 16; if (!panel->backlight.max) @@ -1645,7 +1680,7 @@ static int pch_setup_backlight(struct intel_connector *connector, enum pipe unus panel->backlight.level = clamp(val, panel->backlight.min, panel->backlight.max); - cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); + cpu_ctl2 = intel_de_read(dev_priv, BLC_PWM_CPU_CTL2); panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) && (pch_ctl1 & BLM_PCH_PWM_ENABLE); @@ -1658,7 +1693,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu struct intel_panel *panel = &connector->panel; u32 ctl, val; - ctl = I915_READ(BLC_PWM_CTL); + ctl = intel_de_read(dev_priv, BLC_PWM_CTL); if (IS_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; @@ -1697,11 +1732,11 @@ static int i965_setup_backlight(struct intel_connector *connector, enum pipe unu struct intel_panel *panel = &connector->panel; u32 ctl, ctl2, val; - ctl2 = I915_READ(BLC_PWM_CTL2); + ctl2 = intel_de_read(dev_priv, BLC_PWM_CTL2); panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE; panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; - ctl = I915_READ(BLC_PWM_CTL); + ctl = intel_de_read(dev_priv, BLC_PWM_CTL); panel->backlight.max = ctl >> 16; if (!panel->backlight.max) @@ -1731,13 +1766,13 @@ static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe struct intel_panel *panel = &connector->panel; u32 ctl, ctl2, val; - if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) + if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)) return -ENODEV; - ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); + ctl2 = intel_de_read(dev_priv, VLV_BLC_PWM_CTL2(pipe)); panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; - ctl = I915_READ(VLV_BLC_PWM_CTL(pipe)); + ctl = intel_de_read(dev_priv, VLV_BLC_PWM_CTL(pipe)); panel->backlight.max = ctl >> 16; if (!panel->backlight.max) @@ -1767,18 +1802,20 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) panel->backlight.controller = dev_priv->vbt.backlight.controller; - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); + pwm_ctl = intel_de_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); /* Controller 1 uses the utility pin. */ if (panel->backlight.controller == 1) { - val = I915_READ(UTIL_PIN_CTL); + val = intel_de_read(dev_priv, UTIL_PIN_CTL); panel->backlight.util_pin_active_low = val & UTIL_PIN_POLARITY; } panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY; panel->backlight.max = - I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller)); + intel_de_read(dev_priv, + BXT_BLC_PWM_FREQ(panel->backlight.controller)); if (!panel->backlight.max) panel->backlight.max = get_backlight_max_vbt(connector); @@ -1812,11 +1849,13 @@ cnp_setup_backlight(struct intel_connector *connector, enum pipe unused) */ panel->backlight.controller = 0; - pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); + pwm_ctl = intel_de_read(dev_priv, + BXT_BLC_PWM_CTL(panel->backlight.controller)); panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY; panel->backlight.max = - I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller)); + intel_de_read(dev_priv, + BXT_BLC_PWM_FREQ(panel->backlight.controller)); if (!panel->backlight.max) panel->backlight.max = get_backlight_max_vbt(connector); @@ -1843,6 +1882,7 @@ static int pwm_setup_backlight(struct intel_connector *connector, struct drm_i915_private *dev_priv = to_i915(dev); struct intel_panel *panel = &connector->panel; const char *desc; + u32 level, ns; int retval; /* Get the right PWM chip for DSI backlight according to VBT */ @@ -1855,7 +1895,8 @@ static int pwm_setup_backlight(struct intel_connector *connector, } if (IS_ERR(panel->backlight.pwm)) { - DRM_ERROR("Failed to get the %s PWM chip\n", desc); + drm_err(&dev_priv->drm, "Failed to get the %s PWM chip\n", + desc); panel->backlight.pwm = NULL; return -ENODEV; } @@ -1866,23 +1907,27 @@ static int pwm_setup_backlight(struct intel_connector *connector, */ pwm_apply_args(panel->backlight.pwm); - retval = pwm_config(panel->backlight.pwm, CRC_PMIC_PWM_PERIOD_NS, - CRC_PMIC_PWM_PERIOD_NS); + panel->backlight.min = 0; /* 0% */ + panel->backlight.max = 100; /* 100% */ + level = intel_panel_compute_brightness(connector, 100); + ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); + + retval = pwm_config(panel->backlight.pwm, ns, CRC_PMIC_PWM_PERIOD_NS); if (retval < 0) { - DRM_ERROR("Failed to configure the pwm chip\n"); + drm_err(&dev_priv->drm, "Failed to configure the pwm chip\n"); pwm_put(panel->backlight.pwm); panel->backlight.pwm = NULL; return retval; } - panel->backlight.min = 0; /* 0% */ - panel->backlight.max = 100; /* 100% */ - panel->backlight.level = DIV_ROUND_UP( - pwm_get_duty_cycle(panel->backlight.pwm) * 100, - CRC_PMIC_PWM_PERIOD_NS); + level = DIV_ROUND_UP(pwm_get_duty_cycle(panel->backlight.pwm) * 100, + CRC_PMIC_PWM_PERIOD_NS); + panel->backlight.level = + intel_panel_compute_brightness(connector, level); panel->backlight.enabled = panel->backlight.level != 0; - DRM_INFO("Using %s PWM for LCD backlight control\n", desc); + drm_info(&dev_priv->drm, "Using %s PWM for LCD backlight control\n", + desc); return 0; } @@ -1913,15 +1958,17 @@ int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe) if (!dev_priv->vbt.backlight.present) { if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) { - DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n"); + drm_dbg_kms(&dev_priv->drm, + "no backlight present per VBT, but present per quirk\n"); } else { - DRM_DEBUG_KMS("no backlight present per VBT\n"); + drm_dbg_kms(&dev_priv->drm, + "no backlight present per VBT\n"); return 0; } } /* ensure intel_panel has been initialized first */ - if (WARN_ON(!panel->backlight.setup)) + if (drm_WARN_ON(&dev_priv->drm, !panel->backlight.setup)) return -ENODEV; /* set level and max in panel struct */ @@ -1930,17 +1977,19 @@ int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe) mutex_unlock(&dev_priv->backlight_lock); if (ret) { - DRM_DEBUG_KMS("failed to setup backlight for connector %s\n", - connector->name); + drm_dbg_kms(&dev_priv->drm, + "failed to setup backlight for connector %s\n", + connector->name); return ret; } panel->backlight.present = true; - DRM_DEBUG_KMS("Connector %s backlight initialized, %s, brightness %u/%u\n", - connector->name, - enableddisabled(panel->backlight.enabled), - panel->backlight.level, panel->backlight.max); + drm_dbg_kms(&dev_priv->drm, + "Connector %s backlight initialized, %s, brightness %u/%u\n", + connector->name, + enableddisabled(panel->backlight.enabled), + panel->backlight.level, panel->backlight.max); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 520408e83681..a9a5df2fee4d 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -110,8 +110,8 @@ static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, *source = INTEL_PIPE_CRC_SOURCE_DP_D; break; default: - WARN(1, "nonexisting DP port %c\n", - port_name(dig_port->base.port)); + drm_WARN(dev, 1, "nonexisting DP port %c\n", + port_name(dig_port->base.port)); break; } break; @@ -172,7 +172,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, * - DisplayPort scrambling: used for EMI reduction */ if (need_stable_symbols) { - u32 tmp = I915_READ(PORT_DFT2_G4X); + u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X); tmp |= DC_BALANCE_RESET_VLV; switch (pipe) { @@ -188,7 +188,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, default: return -EINVAL; } - I915_WRITE(PORT_DFT2_G4X, tmp); + intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); } return 0; @@ -237,7 +237,7 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, enum pipe pipe) { - u32 tmp = I915_READ(PORT_DFT2_G4X); + u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X); switch (pipe) { case PIPE_A: @@ -254,7 +254,7 @@ static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, } if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) tmp &= ~DC_BALANCE_RESET_VLV; - I915_WRITE(PORT_DFT2_G4X, tmp); + intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); } static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, @@ -328,7 +328,8 @@ put_state: drm_atomic_state_put(state); unlock: - WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); + drm_WARN(&dev_priv->drm, ret, + "Toggling workaround to %i returns %i\n", enable, ret); drm_modeset_drop_locks(&ctx); drm_modeset_acquire_fini(&ctx); } @@ -440,15 +441,11 @@ display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) return 0; } -void intel_display_crc_init(struct drm_i915_private *dev_priv) +void intel_crtc_crc_init(struct intel_crtc *crtc) { - enum pipe pipe; + struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc; - for_each_pipe(dev_priv, pipe) { - struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; - - spin_lock_init(&pipe_crc->lock); - } + spin_lock_init(&pipe_crc->lock); } static int i8xx_crc_source_valid(struct drm_i915_private *dev_priv, @@ -570,7 +567,7 @@ int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, enum intel_pipe_crc_source source; if (display_crc_ctl_parse_source(source_name, &source) < 0) { - DRM_DEBUG_DRIVER("unknown source %s\n", source_name); + drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name); return -EINVAL; } @@ -586,7 +583,8 @@ int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name) { struct drm_i915_private *dev_priv = to_i915(crtc->dev); - struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc; enum intel_display_power_domain power_domain; enum intel_pipe_crc_source source; intel_wakeref_t wakeref; @@ -595,14 +593,15 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name) bool enable; if (display_crc_ctl_parse_source(source_name, &source) < 0) { - DRM_DEBUG_DRIVER("unknown source %s\n", source_name); + drm_dbg(&dev_priv->drm, "unknown source %s\n", source_name); return -EINVAL; } power_domain = POWER_DOMAIN_PIPE(crtc->index); wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); if (!wakeref) { - DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); + drm_dbg_kms(&dev_priv->drm, + "Trying to capture CRC while pipe is off\n"); return -EIO; } @@ -615,8 +614,8 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name) goto out; pipe_crc->source = source; - I915_WRITE(PIPE_CRC_CTL(crtc->index), val); - POSTING_READ(PIPE_CRC_CTL(crtc->index)); + intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); if (!source) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) @@ -638,7 +637,7 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc) { struct drm_crtc *crtc = &intel_crtc->base; struct drm_i915_private *dev_priv = to_i915(crtc->dev); - struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; + struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc; u32 val = 0; if (!crtc->crc.opened) @@ -650,22 +649,22 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc) /* Don't need pipe_crc->lock here, IRQs are not generated. */ pipe_crc->skipped = 0; - I915_WRITE(PIPE_CRC_CTL(crtc->index), val); - POSTING_READ(PIPE_CRC_CTL(crtc->index)); + intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), val); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); } void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc) { struct drm_crtc *crtc = &intel_crtc->base; struct drm_i915_private *dev_priv = to_i915(crtc->dev); - struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; + struct intel_pipe_crc *pipe_crc = &intel_crtc->pipe_crc; /* Swallow crc's until we stop generating them. */ spin_lock_irq(&pipe_crc->lock); pipe_crc->skipped = INT_MIN; spin_unlock_irq(&pipe_crc->lock); - I915_WRITE(PIPE_CRC_CTL(crtc->index), 0); - POSTING_READ(PIPE_CRC_CTL(crtc->index)); + intel_de_write(dev_priv, PIPE_CRC_CTL(crtc->index), 0); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(crtc->index)); intel_synchronize_irq(dev_priv); } diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.h b/drivers/gpu/drm/i915/display/intel_pipe_crc.h index db258a756fc6..43012b189415 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.h @@ -13,7 +13,7 @@ struct drm_i915_private; struct intel_crtc; #ifdef CONFIG_DEBUG_FS -void intel_display_crc_init(struct drm_i915_private *dev_priv); +void intel_crtc_crc_init(struct intel_crtc *crtc); int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name); int intel_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name, size_t *values_cnt); @@ -22,7 +22,7 @@ const char *const *intel_crtc_get_crc_sources(struct drm_crtc *crtc, void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc); void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc); #else -static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} +static inline void intel_crtc_crc_init(struct intel_crtc *crtc) {} #define intel_crtc_set_crc_source NULL #define intel_crtc_verify_crc_source NULL #define intel_crtc_get_crc_sources NULL diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 83025052c965..fd9b146e3aba 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -59,11 +59,28 @@ * get called by the frontbuffer tracking code. Note that because of locking * issues the self-refresh re-enable code is done from a work queue, which * must be correctly synchronized/cancelled when shutting down the pipe." + * + * DC3CO (DC3 clock off) + * + * On top of PSR2, GEN12 adds a intermediate power savings state that turns + * clock off automatically during PSR2 idle state. + * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep + * entry/exit allows the HW to enter a low-power state even when page flipping + * periodically (for instance a 30fps video playback scenario). + * + * Every time a flips occurs PSR2 will get out of deep sleep state(if it was), + * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6 + * frames, if no other flip occurs and the function above is executed, DC3CO is + * disabled and PSR2 is configured to enter deep sleep, resetting again in case + * of another flip. + * Front buffer modifications do not trigger DC3CO activation on purpose as it + * would bring a lot of complexity and most of the moderns systems will only + * use page flips. */ -static bool psr_global_enabled(u32 debug) +static bool psr_global_enabled(struct drm_i915_private *i915) { - switch (debug & I915_PSR_DEBUG_MODE_MASK) { + switch (i915->psr.debug & I915_PSR_DEBUG_MODE_MASK) { case I915_PSR_DEBUG_DEFAULT: return i915_modparams.enable_psr; case I915_PSR_DEBUG_DISABLE: @@ -77,8 +94,8 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, const struct intel_crtc_state *crtc_state) { /* Cannot enable DSC and PSR2 simultaneously */ - WARN_ON(crtc_state->dsc.compression_enable && - crtc_state->has_psr2); + drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable && + crtc_state->has_psr2); switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { case I915_PSR_DEBUG_DISABLE: @@ -114,10 +131,10 @@ static void psr_irq_control(struct drm_i915_private *dev_priv) EDP_PSR_PRE_ENTRY(trans_shift); /* Warning: it is masking/setting reserved bits too */ - val = I915_READ(imr_reg); + val = intel_de_read(dev_priv, imr_reg); val &= ~EDP_PSR_TRANS_MASK(trans_shift); val |= ~mask; - I915_WRITE(imr_reg, val); + intel_de_write(dev_priv, imr_reg, val); } static void psr_event_print(u32 val, bool psr2_enabled) @@ -174,20 +191,24 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) if (psr_iir & EDP_PSR_PRE_ENTRY(trans_shift)) { dev_priv->psr.last_entry_attempt = time_ns; - DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n", - transcoder_name(cpu_transcoder)); + drm_dbg_kms(&dev_priv->drm, + "[transcoder %s] PSR entry attempt in 2 vblanks\n", + transcoder_name(cpu_transcoder)); } if (psr_iir & EDP_PSR_POST_EXIT(trans_shift)) { dev_priv->psr.last_exit = time_ns; - DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", - transcoder_name(cpu_transcoder)); + drm_dbg_kms(&dev_priv->drm, + "[transcoder %s] PSR exit completed\n", + transcoder_name(cpu_transcoder)); if (INTEL_GEN(dev_priv) >= 9) { - u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); + u32 val = intel_de_read(dev_priv, + PSR_EVENT(cpu_transcoder)); bool psr2_enabled = dev_priv->psr.psr2_enabled; - I915_WRITE(PSR_EVENT(cpu_transcoder), val); + intel_de_write(dev_priv, PSR_EVENT(cpu_transcoder), + val); psr_event_print(val, psr2_enabled); } } @@ -195,7 +216,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) if (psr_iir & EDP_PSR_ERROR(trans_shift)) { u32 val; - DRM_WARN("[transcoder %s] PSR aux error\n", + drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", transcoder_name(cpu_transcoder)); dev_priv->psr.irq_aux_error = true; @@ -208,9 +229,9 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) * again so we don't care about unmask the interruption * or unset irq_aux_error. */ - val = I915_READ(imr_reg); + val = intel_de_read(dev_priv, imr_reg); val |= EDP_PSR_ERROR(trans_shift); - I915_WRITE(imr_reg, val); + intel_de_write(dev_priv, imr_reg, val); schedule_work(&dev_priv->psr.work); } @@ -270,7 +291,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) to_i915(dp_to_dig_port(intel_dp)->base.base.dev); if (dev_priv->psr.dp) { - DRM_WARN("More than one eDP panel found, PSR support should be extended\n"); + drm_warn(&dev_priv->drm, + "More than one eDP panel found, PSR support should be extended\n"); return; } @@ -279,16 +301,18 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) if (!intel_dp->psr_dpcd[0]) return; - DRM_DEBUG_KMS("eDP panel supports PSR version %x\n", - intel_dp->psr_dpcd[0]); + drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", + intel_dp->psr_dpcd[0]); - if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { - DRM_DEBUG_KMS("PSR support not currently available for this panel\n"); + if (drm_dp_has_quirk(&intel_dp->desc, 0, DP_DPCD_QUIRK_NO_PSR)) { + drm_dbg_kms(&dev_priv->drm, + "PSR support not currently available for this panel\n"); return; } if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { - DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n"); + drm_dbg_kms(&dev_priv->drm, + "Panel lacks power state control, PSR cannot be enabled\n"); return; } @@ -316,8 +340,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) * GTC first. */ dev_priv->psr.sink_psr2_support = y_req && alpm; - DRM_DEBUG_KMS("PSR2 %ssupported\n", - dev_priv->psr.sink_psr2_support ? "" : "not "); + drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", + dev_priv->psr.sink_psr2_support ? "" : "not "); if (dev_priv->psr.sink_psr2_support) { dev_priv->psr.colorimetry_support = @@ -380,8 +404,9 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) BUILD_BUG_ON(sizeof(aux_msg) > 20); for (i = 0; i < sizeof(aux_msg); i += 4) - I915_WRITE(EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), - intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); + intel_de_write(dev_priv, + EDP_PSR_AUX_DATA(dev_priv->psr.transcoder, i >> 2), + intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i)); aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); @@ -391,7 +416,8 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) /* Select only valid bits for SRD_AUX_CTL */ aux_ctl &= psr_aux_mask; - I915_WRITE(EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), aux_ctl); + intel_de_write(dev_priv, EDP_PSR_AUX_CTL(dev_priv->psr.transcoder), + aux_ctl); } static void intel_psr_enable_sink(struct intel_dp *intel_dp) @@ -454,22 +480,30 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) return val; } -static void hsw_activate_psr1(struct intel_dp *intel_dp) +static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - u32 max_sleep_time = 0x1f; - u32 val = EDP_PSR_ENABLE; + int idle_frames; /* Let's use 6 as the minimum to cover all known cases including the * off-by-one issue that HW has in some cases. */ - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); - - /* sink_sync_latency of 8 means source has to wait for more than 8 - * frames, we'll go with 9 frames for now - */ + idle_frames = max(6, dev_priv->vbt.psr.idle_frames); idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); - val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; + + if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) + idle_frames = 0xf; + + return idle_frames; +} + +static void hsw_activate_psr1(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 max_sleep_time = 0x1f; + u32 val = EDP_PSR_ENABLE; + + val |= psr_compute_idle_frames(intel_dp) << EDP_PSR_IDLE_FRAME_SHIFT; val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT; if (IS_HASWELL(dev_priv)) @@ -483,9 +517,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 8) val |= EDP_PSR_CRC_ENABLE; - val |= (I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & + val |= (intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK); - I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); + intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), val); } static void hsw_activate_psr2(struct intel_dp *intel_dp) @@ -493,13 +527,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u32 val; - /* Let's use 6 as the minimum to cover all known cases including the - * off-by-one issue that HW has in some cases. - */ - int idle_frames = max(6, dev_priv->vbt.psr.idle_frames); - - idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); - val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; + val = psr_compute_idle_frames(intel_dp) << EDP_PSR2_IDLE_FRAME_SHIFT; val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) @@ -521,9 +549,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. */ - I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), 0); + intel_de_write(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder), 0); - I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); + intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); } static bool @@ -552,10 +580,10 @@ static void psr2_program_idle_frames(struct drm_i915_private *dev_priv, u32 val; idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT; - val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); + val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)); val &= ~EDP_PSR2_IDLE_FRAME_MASK; val |= idle_frames; - I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); + intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder), val); } static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) @@ -566,29 +594,22 @@ static void tgl_psr2_enable_dc3co(struct drm_i915_private *dev_priv) static void tgl_psr2_disable_dc3co(struct drm_i915_private *dev_priv) { - int idle_frames; + struct intel_dp *intel_dp = dev_priv->psr.dp; intel_display_power_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); - /* - * Restore PSR2 idle frame let's use 6 as the minimum to cover all known - * cases including the off-by-one issue that HW has in some cases. - */ - idle_frames = max(6, dev_priv->vbt.psr.idle_frames); - idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1); - psr2_program_idle_frames(dev_priv, idle_frames); + psr2_program_idle_frames(dev_priv, psr_compute_idle_frames(intel_dp)); } -static void tgl_dc5_idle_thread(struct work_struct *work) +static void tgl_dc3co_disable_work(struct work_struct *work) { struct drm_i915_private *dev_priv = - container_of(work, typeof(*dev_priv), psr.idle_work.work); + container_of(work, typeof(*dev_priv), psr.dc3co_work.work); mutex_lock(&dev_priv->psr.lock); /* If delayed work is pending, it is not idle */ - if (delayed_work_pending(&dev_priv->psr.idle_work)) + if (delayed_work_pending(&dev_priv->psr.dc3co_work)) goto unlock; - DRM_DEBUG_KMS("DC5/6 idle thread\n"); tgl_psr2_disable_dc3co(dev_priv); unlock: mutex_unlock(&dev_priv->psr.lock); @@ -599,11 +620,41 @@ static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv) if (!dev_priv->psr.dc3co_enabled) return; - cancel_delayed_work(&dev_priv->psr.idle_work); + cancel_delayed_work(&dev_priv->psr.dc3co_work); /* Before PSR2 exit disallow dc3co*/ tgl_psr2_disable_dc3co(dev_priv); } +static void +tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + u32 exit_scanlines; + + if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) + return; + + /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/ + if (to_intel_crtc(crtc_state->uapi.crtc)->pipe != PIPE_A || + dig_port->base.port != PORT_A) + return; + + /* + * DC3CO Exit time 200us B.Spec 49196 + * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1 + */ + exit_scanlines = + intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; + + if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) + return; + + crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -616,8 +667,9 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { - DRM_DEBUG_KMS("PSR2 not supported in transcoder %s\n", - transcoder_name(crtc_state->cpu_transcoder)); + drm_dbg_kms(&dev_priv->drm, + "PSR2 not supported in transcoder %s\n", + transcoder_name(crtc_state->cpu_transcoder)); return false; } @@ -627,7 +679,8 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, * over PSR2. */ if (crtc_state->dsc.compression_enable) { - DRM_DEBUG_KMS("PSR2 cannot be enabled since DSC is enabled\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR2 cannot be enabled since DSC is enabled\n"); return false; } @@ -646,15 +699,17 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, } if (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v) { - DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", - crtc_hdisplay, crtc_vdisplay, - psr_max_h, psr_max_v); + drm_dbg_kms(&dev_priv->drm, + "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", + crtc_hdisplay, crtc_vdisplay, + psr_max_h, psr_max_v); return false; } if (crtc_state->pipe_bpp > max_bpp) { - DRM_DEBUG_KMS("PSR2 not enabled, pipe bpp %d > max supported %d\n", - crtc_state->pipe_bpp, max_bpp); + drm_dbg_kms(&dev_priv->drm, + "PSR2 not enabled, pipe bpp %d > max supported %d\n", + crtc_state->pipe_bpp, max_bpp); return false; } @@ -665,16 +720,19 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, * x granularity. */ if (crtc_hdisplay % dev_priv->psr.su_x_granularity) { - DRM_DEBUG_KMS("PSR2 not enabled, hdisplay(%d) not multiple of %d\n", - crtc_hdisplay, dev_priv->psr.su_x_granularity); + drm_dbg_kms(&dev_priv->drm, + "PSR2 not enabled, hdisplay(%d) not multiple of %d\n", + crtc_hdisplay, dev_priv->psr.su_x_granularity); return false; } if (crtc_state->crc_enabled) { - DRM_DEBUG_KMS("PSR2 not enabled because it would inhibit pipe CRC calculation\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); return false; } + tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); return true; } @@ -700,31 +758,36 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, * hardcoded to PORT_A */ if (dig_port->base.port != PORT_A) { - DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Port not supported\n"); return; } if (dev_priv->psr.sink_not_reliable) { - DRM_DEBUG_KMS("PSR sink implementation is not reliable\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR sink implementation is not reliable\n"); return; } if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { - DRM_DEBUG_KMS("PSR condition failed: Interlaced mode enabled\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Interlaced mode enabled\n"); return; } psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); if (psr_setup_time < 0) { - DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n", - intel_dp->psr_dpcd[1]); + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Invalid PSR setup time (0x%02x)\n", + intel_dp->psr_dpcd[1]); return; } if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { - DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n", - psr_setup_time); + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: PSR setup time (%d us) too long\n", + psr_setup_time); return; } @@ -737,10 +800,12 @@ static void intel_psr_activate(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) - WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE); - WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); - WARN_ON(dev_priv->psr.active); + drm_WARN_ON(&dev_priv->drm, + intel_de_read(dev_priv, EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE); + drm_WARN_ON(&dev_priv->drm, dev_priv->psr.active); lockdep_assert_held(&dev_priv->psr.lock); /* psr1 and psr2 are mutually exclusive.*/ @@ -768,11 +833,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (dev_priv->psr.psr2_enabled && (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv))) { i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder); - u32 chicken = I915_READ(reg); + u32 chicken = intel_de_read(dev_priv, reg); chicken |= PSR2_VSC_ENABLE_PROG_HEADER | PSR2_ADD_VERTICAL_LINE_COUNT; - I915_WRITE(reg, chicken); + intel_de_write(dev_priv, reg, chicken); } /* @@ -789,9 +854,24 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (INTEL_GEN(dev_priv) < 11) mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; - I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask); + intel_de_write(dev_priv, EDP_PSR_DEBUG(dev_priv->psr.transcoder), + mask); psr_irq_control(dev_priv); + + if (crtc_state->dc3co_exitline) { + u32 val; + + /* + * TODO: if future platforms supports DC3CO in more than one + * transcoder, EXITLINE will need to be unset when disabling PSR + */ + val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); + val &= ~EXITLINE_MASK; + val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; + val |= EXITLINE_ENABLE; + intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); + } } static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, @@ -800,14 +880,16 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, struct intel_dp *intel_dp = dev_priv->psr.dp; u32 val; - WARN_ON(dev_priv->psr.enabled); + drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; - dev_priv->psr.dc3co_exit_delay = intel_get_frame_time_us(crtc_state); dev_priv->psr.transcoder = crtc_state->cpu_transcoder; + /* DC5/DC6 requires at least 6 idle frames */ + val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); + dev_priv->psr.dc3co_exit_delay = val; /* * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR @@ -818,20 +900,22 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, * to avoid any rendering problems. */ if (INTEL_GEN(dev_priv) >= 12) { - val = I915_READ(TRANS_PSR_IIR(dev_priv->psr.transcoder)); + val = intel_de_read(dev_priv, + TRANS_PSR_IIR(dev_priv->psr.transcoder)); val &= EDP_PSR_ERROR(0); } else { - val = I915_READ(EDP_PSR_IIR); + val = intel_de_read(dev_priv, EDP_PSR_IIR); val &= EDP_PSR_ERROR(dev_priv->psr.transcoder); } if (val) { dev_priv->psr.sink_not_reliable = true; - DRM_DEBUG_KMS("PSR interruption error set, not enabling PSR\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR interruption error set, not enabling PSR\n"); return; } - DRM_DEBUG_KMS("Enabling PSR%s\n", - dev_priv->psr.psr2_enabled ? "2" : "1"); + drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", + dev_priv->psr.psr2_enabled ? "2" : "1"); intel_psr_setup_vsc(intel_dp, crtc_state); intel_psr_enable_sink(intel_dp); intel_psr_enable_source(intel_dp, crtc_state); @@ -860,12 +944,12 @@ void intel_psr_enable(struct intel_dp *intel_dp, if (!crtc_state->has_psr) return; - WARN_ON(dev_priv->drrs.dp); + drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); mutex_lock(&dev_priv->psr.lock); - if (!psr_global_enabled(dev_priv->psr.debug)) { - DRM_DEBUG_KMS("PSR disabled by flag\n"); + if (!psr_global_enabled(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); goto unlock; } @@ -881,27 +965,33 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) if (!dev_priv->psr.active) { if (transcoder_has_psr2(dev_priv, dev_priv->psr.transcoder)) { - val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); - WARN_ON(val & EDP_PSR2_ENABLE); + val = intel_de_read(dev_priv, + EDP_PSR2_CTL(dev_priv->psr.transcoder)); + drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); } - val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); - WARN_ON(val & EDP_PSR_ENABLE); + val = intel_de_read(dev_priv, + EDP_PSR_CTL(dev_priv->psr.transcoder)); + drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); return; } if (dev_priv->psr.psr2_enabled) { tgl_disallow_dc3co_on_psr2_exit(dev_priv); - val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)); - WARN_ON(!(val & EDP_PSR2_ENABLE)); + val = intel_de_read(dev_priv, + EDP_PSR2_CTL(dev_priv->psr.transcoder)); + drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); val &= ~EDP_PSR2_ENABLE; - I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val); + intel_de_write(dev_priv, + EDP_PSR2_CTL(dev_priv->psr.transcoder), val); } else { - val = I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)); - WARN_ON(!(val & EDP_PSR_ENABLE)); + val = intel_de_read(dev_priv, + EDP_PSR_CTL(dev_priv->psr.transcoder)); + drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); val &= ~EDP_PSR_ENABLE; - I915_WRITE(EDP_PSR_CTL(dev_priv->psr.transcoder), val); + intel_de_write(dev_priv, + EDP_PSR_CTL(dev_priv->psr.transcoder), val); } dev_priv->psr.active = false; } @@ -917,8 +1007,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) if (!dev_priv->psr.enabled) return; - DRM_DEBUG_KMS("Disabling PSR%s\n", - dev_priv->psr.psr2_enabled ? "2" : "1"); + drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", + dev_priv->psr.psr2_enabled ? "2" : "1"); intel_psr_exit(dev_priv); @@ -933,7 +1023,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) /* Wait till PSR is idle */ if (intel_de_wait_for_clear(dev_priv, psr_status, psr_status_mask, 2000)) - DRM_ERROR("Timed out waiting PSR idle state\n"); + drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); @@ -959,7 +1049,7 @@ void intel_psr_disable(struct intel_dp *intel_dp, if (!old_crtc_state->has_psr) return; - if (WARN_ON(!CAN_PSR(dev_priv))) + if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(dev_priv))) return; mutex_lock(&dev_priv->psr.lock); @@ -968,7 +1058,7 @@ void intel_psr_disable(struct intel_dp *intel_dp, mutex_unlock(&dev_priv->psr.lock); cancel_work_sync(&dev_priv->psr.work); - cancel_delayed_work_sync(&dev_priv->psr.idle_work); + cancel_delayed_work_sync(&dev_priv->psr.dc3co_work); } static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) @@ -983,7 +1073,7 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) * but it makes more sense write to the current active * pipe. */ - I915_WRITE(CURSURFLIVE(dev_priv->psr.pipe), 0); + intel_de_write(dev_priv, CURSURFLIVE(dev_priv->psr.pipe), 0); else /* * A write to CURSURFLIVE do not cause HW tracking to exit PSR @@ -1015,7 +1105,7 @@ void intel_psr_update(struct intel_dp *intel_dp, mutex_lock(&dev_priv->psr.lock); - enable = crtc_state->has_psr && psr_global_enabled(psr->debug); + enable = crtc_state->has_psr && psr_global_enabled(dev_priv); psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { @@ -1103,7 +1193,8 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) err = intel_de_wait_for_clear(dev_priv, reg, mask, 50); if (err) - DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for PSR Idle for re-enable\n"); /* After the unlocked wait, verify that PSR is still wanted! */ mutex_lock(&dev_priv->psr.lock); @@ -1167,7 +1258,7 @@ int intel_psr_debug_set(struct drm_i915_private *dev_priv, u64 val) if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || mode > I915_PSR_DEBUG_FORCE_PSR1) { - DRM_DEBUG_KMS("Invalid debug mask %llx\n", val); + drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); return -EINVAL; } @@ -1279,14 +1370,12 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, * When we will be completely rely on PSR2 S/W tracking in future, * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP * event also therefore tgl_dc3co_flush() require to be changed - * accrodingly in future. + * accordingly in future. */ static void tgl_dc3co_flush(struct drm_i915_private *dev_priv, unsigned int frontbuffer_bits, enum fb_op_origin origin) { - u32 delay; - mutex_lock(&dev_priv->psr.lock); if (!dev_priv->psr.dc3co_enabled) @@ -1304,10 +1393,8 @@ tgl_dc3co_flush(struct drm_i915_private *dev_priv, goto unlock; tgl_psr2_enable_dc3co(dev_priv); - /* DC5/DC6 required idle frames = 6 */ - delay = 6 * dev_priv->psr.dc3co_exit_delay; - mod_delayed_work(system_wq, &dev_priv->psr.idle_work, - usecs_to_jiffies(delay)); + mod_delayed_work(system_wq, &dev_priv->psr.dc3co_work, + dev_priv->psr.dc3co_exit_delay); unlock: mutex_unlock(&dev_priv->psr.lock); @@ -1391,7 +1478,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv) dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link; INIT_WORK(&dev_priv->psr.work, intel_psr_work); - INIT_DELAYED_WORK(&dev_priv->psr.idle_work, tgl_dc5_idle_thread); + INIT_DELAYED_WORK(&dev_priv->psr.dc3co_work, tgl_dc3co_disable_work); mutex_init(&dev_priv->psr.lock); } @@ -1427,14 +1514,15 @@ static void psr_alpm_check(struct intel_dp *intel_dp) r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); if (r != 1) { - DRM_ERROR("Error reading ALPM status\n"); + drm_err(&dev_priv->drm, "Error reading ALPM status\n"); return; } if (val & DP_ALPM_LOCK_TIMEOUT_ERROR) { intel_psr_disable_locked(intel_dp); psr->sink_not_reliable = true; - DRM_DEBUG_KMS("ALPM lock timeout error, disabling PSR\n"); + drm_dbg_kms(&dev_priv->drm, + "ALPM lock timeout error, disabling PSR\n"); /* Clearing error */ drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val); @@ -1450,14 +1538,15 @@ static void psr_capability_changed_check(struct intel_dp *intel_dp) r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); if (r != 1) { - DRM_ERROR("Error reading DP_PSR_ESI\n"); + drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); return; } if (val & DP_PSR_CAPS_CHANGE) { intel_psr_disable_locked(intel_dp); psr->sink_not_reliable = true; - DRM_DEBUG_KMS("Sink PSR capability changed, disabling PSR\n"); + drm_dbg_kms(&dev_priv->drm, + "Sink PSR capability changed, disabling PSR\n"); /* Clearing it */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); @@ -1482,7 +1571,8 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) goto exit; if (psr_get_status_and_error_status(intel_dp, &status, &error_status)) { - DRM_ERROR("Error reading PSR status or error status\n"); + drm_err(&dev_priv->drm, + "Error reading PSR status or error status\n"); goto exit; } @@ -1492,17 +1582,22 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) } if (status == DP_PSR_SINK_INTERNAL_ERROR && !error_status) - DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR sink internal error, disabling PSR\n"); if (error_status & DP_PSR_RFB_STORAGE_ERROR) - DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR RFB storage error, disabling PSR\n"); if (error_status & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR) - DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR VSC SDP uncorrectable error, disabling PSR\n"); if (error_status & DP_PSR_LINK_CRC_ERROR) - DRM_DEBUG_KMS("PSR Link CRC error, disabling PSR\n"); + drm_dbg_kms(&dev_priv->drm, + "PSR Link CRC error, disabling PSR\n"); if (error_status & ~errors) - DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n", - error_status & ~errors); + drm_err(&dev_priv->drm, + "PSR_ERROR_STATUS unhandled errors %x\n", + error_status & ~errors); /* clear status register */ drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); @@ -1542,7 +1637,7 @@ void intel_psr_atomic_check(struct drm_connector *connector, return; intel_connector = to_intel_connector(connector); - dig_port = enc_to_dig_port(intel_connector->encoder); + dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector)); if (dev_priv->psr.dp != &dig_port->dp) return; diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c index 399b1542509f..46beb155d835 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.c +++ b/drivers/gpu/drm/i915/display/intel_quirks.c @@ -14,7 +14,7 @@ static void quirk_ssc_force_disable(struct drm_i915_private *i915) { i915->quirks |= QUIRK_LVDS_SSC_DISABLE; - DRM_INFO("applying lvds SSC disable quirk\n"); + drm_info(&i915->drm, "applying lvds SSC disable quirk\n"); } /* @@ -24,14 +24,14 @@ static void quirk_ssc_force_disable(struct drm_i915_private *i915) static void quirk_invert_brightness(struct drm_i915_private *i915) { i915->quirks |= QUIRK_INVERT_BRIGHTNESS; - DRM_INFO("applying inverted panel brightness quirk\n"); + drm_info(&i915->drm, "applying inverted panel brightness quirk\n"); } /* Some VBT's incorrectly indicate no backlight is present */ static void quirk_backlight_present(struct drm_i915_private *i915) { i915->quirks |= QUIRK_BACKLIGHT_PRESENT; - DRM_INFO("applying backlight present quirk\n"); + drm_info(&i915->drm, "applying backlight present quirk\n"); } /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms @@ -40,7 +40,7 @@ static void quirk_backlight_present(struct drm_i915_private *i915) static void quirk_increase_t12_delay(struct drm_i915_private *i915) { i915->quirks |= QUIRK_INCREASE_T12_DELAY; - DRM_INFO("Applying T12 delay quirk\n"); + drm_info(&i915->drm, "Applying T12 delay quirk\n"); } /* @@ -50,7 +50,7 @@ static void quirk_increase_t12_delay(struct drm_i915_private *i915) static void quirk_increase_ddi_disabled_time(struct drm_i915_private *i915) { i915->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME; - DRM_INFO("Applying Increase DDI Disabled quirk\n"); + drm_info(&i915->drm, "Applying Increase DDI Disabled quirk\n"); } struct intel_quirk { @@ -82,6 +82,16 @@ static const struct intel_dmi_quirk intel_dmi_quirks[] = { DMI_MATCH(DMI_PRODUCT_NAME, ""), }, }, + { + .callback = intel_dmi_reverse_brightness, + .ident = "Thundersoft TST178 tablet", + /* DMI strings are too generic, also match on BIOS date */ + .matches = {DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "Aptio CRB"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "To be filled by O.E.M."), + DMI_EXACT_MATCH(DMI_BIOS_DATE, "04/15/2014"), + }, + }, { } /* terminating entry */ }, .hook = quirk_invert_brightness, diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index e8819fd21e03..637d8fe2f8c2 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -34,7 +34,6 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "intel_atomic.h" @@ -217,23 +216,23 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) int i; if (HAS_PCH_SPLIT(dev_priv)) { - I915_WRITE(intel_sdvo->sdvo_reg, val); - POSTING_READ(intel_sdvo->sdvo_reg); + intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); + intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); /* * HW workaround, need to write this twice for issue * that may result in first write getting masked. */ if (HAS_PCH_IBX(dev_priv)) { - I915_WRITE(intel_sdvo->sdvo_reg, val); - POSTING_READ(intel_sdvo->sdvo_reg); + intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val); + intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg); } return; } if (intel_sdvo->port == PORT_B) - cval = I915_READ(GEN3_SDVOC); + cval = intel_de_read(dev_priv, GEN3_SDVOC); else - bval = I915_READ(GEN3_SDVOB); + bval = intel_de_read(dev_priv, GEN3_SDVOB); /* * Write the registers twice for luck. Sometimes, @@ -241,11 +240,11 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) * The BIOS does this too. Yay, magic */ for (i = 0; i < 2; i++) { - I915_WRITE(GEN3_SDVOB, bval); - POSTING_READ(GEN3_SDVOB); + intel_de_write(dev_priv, GEN3_SDVOB, bval); + intel_de_posting_read(dev_priv, GEN3_SDVOB); - I915_WRITE(GEN3_SDVOC, cval); - POSTING_READ(GEN3_SDVOC); + intel_de_write(dev_priv, GEN3_SDVOC, cval); + intel_de_posting_read(dev_priv, GEN3_SDVOC); } } @@ -414,12 +413,10 @@ static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, { const char *cmd_name; int i, pos = 0; -#define BUF_LEN 256 - char buffer[BUF_LEN]; + char buffer[64]; #define BUF_PRINT(args...) \ - pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) - + pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) for (i = 0; i < args_len; i++) { BUF_PRINT("%02X ", ((u8 *)args)[i]); @@ -433,9 +430,9 @@ static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, BUF_PRINT("(%s)", cmd_name); else BUF_PRINT("(%02X)", cmd); - BUG_ON(pos >= BUF_LEN - 1); + + WARN_ON(pos >= sizeof(buffer) - 1); #undef BUF_PRINT -#undef BUF_LEN DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); } @@ -540,8 +537,7 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ u8 status; int i, pos = 0; -#define BUF_LEN 256 - char buffer[BUF_LEN]; + char buffer[64]; buffer[0] = '\0'; @@ -581,7 +577,7 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, } #define BUF_PRINT(args...) \ - pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) + pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args) cmd_status = sdvo_cmd_status(status); if (cmd_status) @@ -600,9 +596,9 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, goto log_fail; BUF_PRINT(" %02X", ((u8 *)response)[i]); } - BUG_ON(pos >= BUF_LEN - 1); + + WARN_ON(pos >= sizeof(buffer) - 1); #undef BUF_PRINT -#undef BUF_LEN DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); return true; @@ -1267,6 +1263,13 @@ static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) pipe_config->clock_set = true; } +static bool intel_has_hdmi_sink(struct intel_sdvo *sdvo, + const struct drm_connector_state *conn_state) +{ + return sdvo->has_hdmi_monitor && + READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; +} + static int intel_sdvo_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) @@ -1322,12 +1325,15 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder, pipe_config->pixel_multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); - if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI) - pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; + pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo, conn_state); - if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON || - (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio)) - pipe_config->has_audio = true; + if (pipe_config->has_hdmi_sink) { + if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO) + pipe_config->has_audio = intel_sdvo->has_hdmi_audio; + else + pipe_config->has_audio = + intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON; + } if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { /* @@ -1470,7 +1476,8 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, else intel_sdvo_get_dtd_from_mode(&output_dtd, mode); if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) - DRM_INFO("Setting output timings on %s failed\n", + drm_info(&dev_priv->drm, + "Setting output timings on %s failed\n", SDVO_NAME(intel_sdvo)); /* Set the input timing to the screen. Assume always input 0. */ @@ -1494,12 +1501,14 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector)) input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) - DRM_INFO("Setting input timings on %s failed\n", + drm_info(&dev_priv->drm, + "Setting input timings on %s failed\n", SDVO_NAME(intel_sdvo)); switch (crtc_state->pixel_multiplier) { default: - WARN(1, "unknown pixel multiplier specified\n"); + drm_WARN(&dev_priv->drm, 1, + "unknown pixel multiplier specified\n"); /* fall through */ case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; @@ -1518,7 +1527,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, if (INTEL_GEN(dev_priv) < 5) sdvox |= SDVO_BORDER_ENABLE; } else { - sdvox = I915_READ(intel_sdvo->sdvo_reg); + sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); if (intel_sdvo->port == PORT_B) sdvox &= SDVOB_PRESERVE_MASK; else @@ -1564,7 +1573,7 @@ bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv, { u32 val; - val = I915_READ(sdvo_reg); + val = intel_de_read(dev_priv, sdvo_reg); /* asserts want to know the pipe even if the port is disabled */ if (HAS_PCH_CPT(dev_priv)) @@ -1607,7 +1616,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO); - sdvox = I915_READ(intel_sdvo->sdvo_reg); + sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); if (!ret) { @@ -1615,7 +1624,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, * Some sdvo encoders are not spec compliant and don't * implement the mandatory get_timings function. */ - DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); + drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n"); pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; } else { if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) @@ -1667,9 +1676,10 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder, } } - WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, - "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", - pipe_config->pixel_multiplier, encoder_pixel_multiplier); + drm_WARN(dev, + encoder_pixel_multiplier != pipe_config->pixel_multiplier, + "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", + pipe_config->pixel_multiplier, encoder_pixel_multiplier); if (sdvox & HDMI_COLOR_RANGE_16_235) pipe_config->limited_color_range = true; @@ -1734,7 +1744,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder, intel_sdvo_set_encoder_power_state(intel_sdvo, DRM_MODE_DPMS_OFF); - temp = I915_READ(intel_sdvo->sdvo_reg); + temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); temp &= ~SDVO_ENABLE; intel_sdvo_write_sdvox(intel_sdvo, temp); @@ -1791,7 +1801,7 @@ static void intel_enable_sdvo(struct intel_encoder *encoder, int i; bool success; - temp = I915_READ(intel_sdvo->sdvo_reg); + temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg); temp |= SDVO_ENABLE; intel_sdvo_write_sdvox(intel_sdvo, temp); @@ -1806,8 +1816,9 @@ static void intel_enable_sdvo(struct intel_encoder *encoder, * a given it the status is a success, we succeeded. */ if (success && !input1) { - DRM_DEBUG_KMS("First %s output reported failure to " - "sync\n", SDVO_NAME(intel_sdvo)); + drm_dbg_kms(&dev_priv->drm, + "First %s output reported failure to " + "sync\n", SDVO_NAME(intel_sdvo)); } if (0) @@ -2219,8 +2230,8 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) struct drm_i915_private *dev_priv = to_i915(connector->dev); struct drm_display_mode *newmode; - DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", - connector->base.id, connector->name); + drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); /* * Fetch modes from VBT. For SDVO prefer the VBT mode since some @@ -2709,6 +2720,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) * Some SDVO devices have one-shot hotplug interrupts. * Ensure that they get re-enabled when an interrupt happens. */ + intel_connector->polled = DRM_CONNECTOR_POLL_HPD; intel_encoder->hotplug = intel_sdvo_hotplug; intel_sdvo_enable_hotplug(intel_encoder); } else { @@ -3229,9 +3241,9 @@ static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv, enum port port) { if (HAS_PCH_SPLIT(dev_priv)) - WARN_ON(port != PORT_B); + drm_WARN_ON(&dev_priv->drm, port != PORT_B); else - WARN_ON(port != PORT_B && port != PORT_C); + drm_WARN_ON(&dev_priv->drm, port != PORT_B && port != PORT_C); } bool intel_sdvo_init(struct drm_i915_private *dev_priv, @@ -3269,8 +3281,9 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, u8 byte; if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { - DRM_DEBUG_KMS("No SDVO device found on %s\n", - SDVO_NAME(intel_sdvo)); + drm_dbg_kms(&dev_priv->drm, + "No SDVO device found on %s\n", + SDVO_NAME(intel_sdvo)); goto err; } } @@ -3293,8 +3306,9 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, if (intel_sdvo_output_setup(intel_sdvo, intel_sdvo->caps.output_flags) != true) { - DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", - SDVO_NAME(intel_sdvo)); + drm_dbg_kms(&dev_priv->drm, + "SDVO output failed to setup on %s\n", + SDVO_NAME(intel_sdvo)); /* Output_setup can leave behind connectors! */ goto err_output; } @@ -3331,7 +3345,7 @@ bool intel_sdvo_init(struct drm_i915_private *dev_priv, &intel_sdvo->pixel_clock_max)) goto err_output; - DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " + drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " "input 1: %c, input 2: %c, " "output 1: %c, output 2: %c\n", diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.h b/drivers/gpu/drm/i915/display/intel_sdvo.h index a66f224aa17d..72065e4360d5 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.h +++ b/drivers/gpu/drm/i915/display/intel_sdvo.h @@ -8,8 +8,6 @@ #include <linux/types.h> -#include <drm/i915_drm.h> - #include "i915_reg.h" struct drm_i915_private; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index fca77ec1e0dd..deda351719db 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -37,10 +37,10 @@ #include <drm/drm_fourcc.h> #include <drm/drm_plane_helper.h> #include <drm/drm_rect.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "i915_trace.h" +#include "i915_vgpu.h" #include "intel_atomic_plane.h" #include "intel_display_types.h" #include "intel_frontbuffer.h" @@ -104,7 +104,7 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) if (min <= 0 || max <= 0) goto irq_disable; - if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) + if (drm_WARN_ON(&dev_priv->drm, drm_crtc_vblank_get(&crtc->base))) goto irq_disable; /* @@ -113,8 +113,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) * re-entry as well. */ if (intel_psr_wait_for_idle(new_crtc_state, &psr_status)) - DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n", - psr_status); + drm_err(&dev_priv->drm, + "PSR idle timed out 0x%x, atomic update may fail\n", + psr_status); local_irq_disable(); @@ -135,8 +136,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) break; if (!timeout) { - DRM_ERROR("Potential atomic update failure on pipe %c\n", - pipe_name(crtc->pipe)); + drm_err(&dev_priv->drm, + "Potential atomic update failure on pipe %c\n", + pipe_name(crtc->pipe)); break; } @@ -204,7 +206,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) * event outside of the critical section - the spinlock might spin for a * while ... */ if (new_crtc_state->uapi.event) { - WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); + drm_WARN_ON(&dev_priv->drm, + drm_crtc_vblank_get(&crtc->base) != 0); spin_lock(&crtc->base.dev->event_lock); drm_crtc_arm_vblank_event(&crtc->base, @@ -221,17 +224,20 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) if (crtc->debug.start_vbl_count && crtc->debug.start_vbl_count != end_vbl_count) { - DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", - pipe_name(pipe), crtc->debug.start_vbl_count, - end_vbl_count, - ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), - crtc->debug.min_vbl, crtc->debug.max_vbl, - crtc->debug.scanline_start, scanline_end); + drm_err(&dev_priv->drm, + "Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", + pipe_name(pipe), crtc->debug.start_vbl_count, + end_vbl_count, + ktime_us_delta(end_vbl_time, + crtc->debug.start_vbl_time), + crtc->debug.min_vbl, crtc->debug.max_vbl, + crtc->debug.scanline_start, scanline_end); } #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) > VBLANK_EVASION_TIME_US) - DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n", + drm_warn(&dev_priv->drm, + "Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n", pipe_name(pipe), ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), VBLANK_EVASION_TIME_US); @@ -278,6 +284,16 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation); /* + * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS + * abuses hsub/vsub so we can't use them here. But as they + * are limited to 32bpp RGB formats we don't actually need + * to check anything. + */ + if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) + return 0; + + /* * Hardware doesn't handle subpixel coordinates. * Adjust to (macro)pixel boundary, but be careful not to * increase the source viewport size, because that could @@ -291,26 +307,26 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) drm_rect_init(src, src_x << 16, src_y << 16, src_w << 16, src_h << 16); - if (!fb->format->is_yuv) - return 0; - - /* YUV specific checks */ - if (!rotated) { + if (fb->format->format == DRM_FORMAT_RGB565 && rotated) { + hsub = 2; + vsub = 2; + } else { hsub = fb->format->hsub; vsub = fb->format->vsub; - } else { - hsub = vsub = max(fb->format->hsub, fb->format->vsub); } + if (rotated) + hsub = vsub = max(hsub, vsub); + if (src_x % hsub || src_w % hsub) { - DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for %sYUV planes\n", - src_x, src_w, hsub, rotated ? "rotated " : ""); + DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n", + src_x, src_w, hsub, yesno(rotated)); return -EINVAL; } if (src_y % vsub || src_h % vsub) { - DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for %sYUV planes\n", - src_y, src_h, vsub, rotated ? "rotated " : ""); + DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n", + src_y, src_h, vsub, yesno(rotated)); return -EINVAL; } @@ -349,9 +365,8 @@ static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); - unsigned int pixel_rate = crtc_state->pixel_rate; - unsigned int src_w, src_h, dst_w, dst_h; unsigned int num, den; + unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state); skl_plane_ratio(crtc_state, plane_state, &num, &den); @@ -359,17 +374,7 @@ static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) den *= 2; - src_w = drm_rect_width(&plane_state->uapi.src) >> 16; - src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - dst_w = drm_rect_width(&plane_state->uapi.dst); - dst_h = drm_rect_height(&plane_state->uapi.dst); - - /* Downscaling limits the maximum pixel rate */ - dst_w = min(src_w, dst_w); - dst_h = min(src_h, dst_h); - - return DIV64_U64_ROUND_UP(mul_u32_u32(pixel_rate * num, src_w * src_h), - mul_u32_u32(den, dst_w * dst_h)); + return DIV_ROUND_UP(pixel_rate * num, den); } static unsigned int @@ -434,14 +439,16 @@ skl_program_scaler(struct intel_plane *plane, uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); } - I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), - PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); - I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), - PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); - I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), - PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); - I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); - I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); + intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, scaler_id), + PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); + intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, scaler_id), + PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); + intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, scaler_id), + PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); + intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, scaler_id), + (crtc_x << 16) | crtc_y); + intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, scaler_id), + (crtc_w << 16) | crtc_h); } /* Preoffset values for YUV to RGB Conversion */ @@ -547,28 +554,37 @@ icl_program_input_csc(struct intel_plane *plane, else csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) | - GOFF(csc[1])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) | - GOFF(csc[4])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) | - GOFF(csc[7])); - I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8])); - - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), - PREOFF_YUV_TO_RGB_HI); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), + ROFF(csc[0]) | GOFF(csc[1])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), + BOFF(csc[2])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), + ROFF(csc[3]) | GOFF(csc[4])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), + BOFF(csc[5])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), + ROFF(csc[6]) | GOFF(csc[7])); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), + BOFF(csc[8])); + + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), + PREOFF_YUV_TO_RGB_HI); if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + 0); else - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), - PREOFF_YUV_TO_RGB_ME); - I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), - PREOFF_YUV_TO_RGB_LO); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); - I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), + PREOFF_YUV_TO_RGB_ME); + intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), + PREOFF_YUV_TO_RGB_LO); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); + intel_de_write_fw(dev_priv, + PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); } static void @@ -623,44 +639,49 @@ skl_program_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); - I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); + intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id), stride); + intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id), + (src_h << 16) | src_w); if (INTEL_GEN(dev_priv) < 12) aux_dist |= aux_stride; - I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist); + intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id), aux_dist); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), + plane_state->cus_ctl); if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) - I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); + intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), + plane_color_ctl); if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) icl_program_input_csc(plane, crtc_state, plane_state); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk); - I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax); + intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), keymsk); + intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), keymax); - I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id), + (y << 16) | x); if (INTEL_GEN(dev_priv) < 11) - I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), - (plane_state->color_plane[1].y << 16) | - plane_state->color_plane[1].x); + intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), + (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + surf_addr); if (plane_state->scaler_id >= 0) skl_program_scaler(plane, crtc_state, plane_state); @@ -693,12 +714,12 @@ skl_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); if (icl_is_hdr_plane(dev_priv, plane_id)) - I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0); skl_write_plane_wm(plane, crtc_state); - I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); - I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -718,7 +739,7 @@ skl_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; + ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; *pipe = plane->pipe; @@ -774,23 +795,36 @@ chv_update_csc(const struct intel_plane_state *plane_state) if (!fb->format->is_yuv) return; - I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); - - I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); - I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); - I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); - I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); - I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8])); - - I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0)); - I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); - - I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); - I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), + SPCSC_OOFF(0) | SPCSC_IOFF(0)); + + intel_de_write_fw(dev_priv, SPCSCC01(plane_id), + SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); + intel_de_write_fw(dev_priv, SPCSCC23(plane_id), + SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); + intel_de_write_fw(dev_priv, SPCSCC45(plane_id), + SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); + intel_de_write_fw(dev_priv, SPCSCC67(plane_id), + SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); + intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); + + intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), + SPCSC_IMAX(1023) | SPCSC_IMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), + SPCSC_IMAX(512) | SPCSC_IMIN(-512)); + + intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); + intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), + SPCSC_OMAX(1023) | SPCSC_OMIN(0)); } #define SIN_0 0 @@ -829,10 +863,10 @@ vlv_update_clrc(const struct intel_plane_state *plane_state) } /* FIXME these register are single buffered :( */ - I915_WRITE_FW(SPCLRC0(pipe, plane_id), - SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); - I915_WRITE_FW(SPCLRC1(pipe, plane_id), - SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); + intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), + SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); + intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), + SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); } static void @@ -1019,10 +1053,8 @@ static void vlv_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void @@ -1055,32 +1087,37 @@ vlv_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPSTRIDE(pipe, plane_id), - plane_state->color_plane[0].stride); - I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), + (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), + (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) chv_update_csc(plane_state); if (key->flags) { - I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); - I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); - I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); + intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), + key->min_value); + intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), + key->channel_mask); + intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), + key->max_value); } - I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset); - I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x); + intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); + intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl); - I915_WRITE_FW(SPSURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); vlv_update_clrc(plane_state); vlv_update_gamma(plane_state); @@ -1099,8 +1136,8 @@ vlv_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPCNTR(pipe, plane_id), 0); - I915_WRITE_FW(SPSURF(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); + intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1120,7 +1157,7 @@ vlv_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; + ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; *pipe = plane->pipe; @@ -1424,19 +1461,17 @@ static void ivb_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(SPRGAMC(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); i++; - I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]); - I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); i++; } @@ -1476,25 +1511,27 @@ ivb_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, SPRPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, SPRSIZE(pipe), (crtc_h << 16) | crtc_w); if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), sprscale); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); if (key->flags) { - I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value); - I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); } /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET * register */ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPROFFSET(pipe), (y << 16) | x); } else { - I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); - I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), (y << 16) | x); } /* @@ -1502,9 +1539,9 @@ ivb_update_plane(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(SPRCTL(pipe), sprctl); - I915_WRITE_FW(SPRSURF(pipe), - intel_plane_ggtt_offset(plane_state) + sprsurf_offset); + intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); + intel_de_write_fw(dev_priv, SPRSURF(pipe), + intel_plane_ggtt_offset(plane_state) + sprsurf_offset); ivb_update_gamma(plane_state); @@ -1521,11 +1558,11 @@ ivb_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(SPRCTL(pipe), 0); + intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); /* Disable the scaler */ if (IS_IVYBRIDGE(dev_priv)) - I915_WRITE_FW(SPRSCALE(pipe), 0); - I915_WRITE_FW(SPRSURF(pipe), 0); + intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); + intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1544,7 +1581,7 @@ ivb_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE; + ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; *pipe = plane->pipe; @@ -1710,10 +1747,8 @@ static void g4x_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ /* The two end points are implicit (0.0 and 1.0) */ for (i = 1; i < 8 - 1; i++) - I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1), - gamma[i] << 16 | - gamma[i] << 8 | - gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), + gamma[i] << 16 | gamma[i] << 8 | gamma[i]); } static void ilk_sprite_linear_gamma(u16 gamma[17]) @@ -1741,14 +1776,12 @@ static void ilk_update_gamma(const struct intel_plane_state *plane_state) /* FIXME these register are single buffered :( */ for (i = 0; i < 16; i++) - I915_WRITE_FW(DVSGAMC_ILK(pipe, i), - gamma[i] << 20 | - gamma[i] << 10 | - gamma[i]); - - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]); - I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), + gamma[i] << 20 | gamma[i] << 10 | gamma[i]); + + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); + intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); i++; } @@ -1788,28 +1821,30 @@ g4x_update_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride); - I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x); - I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); - I915_WRITE_FW(DVSSCALE(pipe), dvsscale); + intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), + plane_state->color_plane[0].stride); + intel_de_write_fw(dev_priv, DVSPOS(pipe), (crtc_y << 16) | crtc_x); + intel_de_write_fw(dev_priv, DVSSIZE(pipe), (crtc_h << 16) | crtc_w); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); if (key->flags) { - I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value); - I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask); - I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value); + intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); + intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), + key->channel_mask); + intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); } - I915_WRITE_FW(DVSLINOFF(pipe), linear_offset); - I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x); + intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); + intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), (y << 16) | x); /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - I915_WRITE_FW(DVSCNTR(pipe), dvscntr); - I915_WRITE_FW(DVSSURF(pipe), - intel_plane_ggtt_offset(plane_state) + dvssurf_offset); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); + intel_de_write_fw(dev_priv, DVSSURF(pipe), + intel_plane_ggtt_offset(plane_state) + dvssurf_offset); if (IS_G4X(dev_priv)) g4x_update_gamma(plane_state); @@ -1829,10 +1864,10 @@ g4x_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - I915_WRITE_FW(DVSCNTR(pipe), 0); + intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); /* Disable the scaler */ - I915_WRITE_FW(DVSSCALE(pipe), 0); - I915_WRITE_FW(DVSSURF(pipe), 0); + intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); + intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } @@ -1851,7 +1886,7 @@ g4x_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE; + ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; *pipe = plane->pipe; @@ -1999,7 +2034,8 @@ int chv_plane_check_rotation(const struct intel_plane_state *plane_state) if (IS_CHERRYVIEW(dev_priv) && rotation & DRM_MODE_ROTATE_180 && rotation & DRM_MODE_REFLECT_X) { - DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n"); + drm_dbg_kms(&dev_priv->drm, + "Cannot rotate and reflect at the same time\n"); return -EINVAL; } @@ -2040,6 +2076,18 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state, return 0; } +static bool intel_format_is_p01x(u32 format) +{ + switch (format) { + case DRM_FORMAT_P010: + case DRM_FORMAT_P012: + case DRM_FORMAT_P016: + return true; + default: + return false; + } +} + static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) { @@ -2054,21 +2102,24 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && is_ccs_modifier(fb->modifier)) { - DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n", - rotation); + drm_dbg_kms(&dev_priv->drm, + "RC support only with 0/180 degree rotation (%x)\n", + rotation); return -EINVAL; } if (rotation & DRM_MODE_REFLECT_X && fb->modifier == DRM_FORMAT_MOD_LINEAR) { - DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n"); + drm_dbg_kms(&dev_priv->drm, + "horizontal flip is not supported with linear surface formats\n"); return -EINVAL; } if (drm_rotation_90_or_270(rotation)) { if (fb->modifier != I915_FORMAT_MOD_Y_TILED && fb->modifier != I915_FORMAT_MOD_Yf_TILED) { - DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n"); + drm_dbg_kms(&dev_priv->drm, + "Y/Yf tiling required for 90/270!\n"); return -EINVAL; } @@ -2091,9 +2142,10 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, case DRM_FORMAT_Y216: case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: - DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n", - drm_get_format_name(fb->format->format, - &format_name)); + drm_dbg_kms(&dev_priv->drm, + "Unsupported pixel format %s for 90/270!\n", + drm_get_format_name(fb->format->format, + &format_name)); return -EINVAL; default: break; @@ -2109,7 +2161,17 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { - DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); + drm_dbg_kms(&dev_priv->drm, + "Y/Yf tiling not supported in IF-ID mode\n"); + return -EINVAL; + } + + /* Wa_1606054188:tgl */ + if (IS_TIGERLAKE(dev_priv) && + plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE && + intel_format_is_p01x(fb->format->format)) { + drm_dbg_kms(&dev_priv->drm, + "Source color keying not supported with P01x formats\n"); return -EINVAL; } @@ -2136,10 +2198,11 @@ static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_s */ if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { - DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n", - crtc_x + crtc_w < 4 ? "end" : "start", - crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, - 4, pipe_src_w - 4); + drm_dbg_kms(&dev_priv->drm, + "requested plane X %s position %d invalid (valid range %d-%d)\n", + crtc_x + crtc_w < 4 ? "end" : "start", + crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, + 4, pipe_src_w - 4); return -ERANGE; } @@ -2968,7 +3031,6 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, struct intel_plane *plane; enum drm_plane_type plane_type; unsigned int supported_rotations; - unsigned int possible_crtcs; const u64 *modifiers; const u32 *formats; int num_formats; @@ -3023,10 +3085,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane_type = DRM_PLANE_TYPE_OVERLAY; - possible_crtcs = BIT(pipe); - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, - possible_crtcs, plane_funcs, + 0, plane_funcs, formats, num_formats, modifiers, plane_type, "plane %d%c", plane_id + 1, @@ -3077,7 +3137,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, { struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; - unsigned long possible_crtcs; unsigned int supported_rotations; const u64 *modifiers; const u32 *formats; @@ -3162,10 +3221,8 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->id = PLANE_SPRITE0 + sprite; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); - possible_crtcs = BIT(pipe); - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, - possible_crtcs, plane_funcs, + 0, plane_funcs, formats, num_formats, modifiers, DRM_PLANE_TYPE_OVERLAY, "sprite %c", sprite_name(pipe, sprite)); diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 7773169b7331..9b850c11aa78 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -61,7 +61,7 @@ u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port) lane_mask = intel_uncore_read(uncore, PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); - WARN_ON(lane_mask == 0xffffffff); + drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff); lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx); return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); @@ -76,7 +76,7 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) pin_mask = intel_uncore_read(uncore, PORT_TX_DFLEXPA1(dig_port->tc_phy_fia)); - WARN_ON(pin_mask == 0xffffffff); + drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff); return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >> DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); @@ -120,7 +120,8 @@ void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port, struct intel_uncore *uncore = &i915->uncore; u32 val; - WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY); + drm_WARN_ON(&i915->drm, + lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY); val = intel_uncore_read(uncore, PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia)); @@ -181,8 +182,9 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia)); if (val == 0xffffffff) { - DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, nothing connected\n", - dig_port->tc_port_name); + drm_dbg_kms(&i915->drm, + "Port %s: PHY in TCCOLD, nothing connected\n", + dig_port->tc_port_name); return mask; } @@ -195,7 +197,7 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port) mask |= BIT(TC_PORT_LEGACY); /* The sink can be connected only in a single mode. */ - if (!WARN_ON(hweight32(mask) > 1)) + if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1)) tc_port_fixup_legacy_flag(dig_port, mask); return mask; @@ -210,8 +212,9 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port) val = intel_uncore_read(uncore, PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia)); if (val == 0xffffffff) { - DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assuming not complete\n", - dig_port->tc_port_name); + drm_dbg_kms(&i915->drm, + "Port %s: PHY in TCCOLD, assuming not complete\n", + dig_port->tc_port_name); return false; } @@ -228,8 +231,9 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port, val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); if (val == 0xffffffff) { - DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, can't set safe-mode to %s\n", - dig_port->tc_port_name, + drm_dbg_kms(&i915->drm, + "Port %s: PHY in TCCOLD, can't set safe-mode to %s\n", + dig_port->tc_port_name, enableddisabled(enable)); return false; @@ -243,8 +247,9 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val); if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10)) - DRM_DEBUG_KMS("Port %s: PHY complete clear timed out\n", - dig_port->tc_port_name); + drm_dbg_kms(&i915->drm, + "Port %s: PHY complete clear timed out\n", + dig_port->tc_port_name); return true; } @@ -258,8 +263,9 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port) val = intel_uncore_read(uncore, PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia)); if (val == 0xffffffff) { - DRM_DEBUG_KMS("Port %s: PHY in TCCOLD, assume safe mode\n", - dig_port->tc_port_name); + drm_dbg_kms(&i915->drm, + "Port %s: PHY in TCCOLD, assume safe mode\n", + dig_port->tc_port_name); return true; } @@ -409,16 +415,17 @@ static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port, enum tc_port_mode old_tc_mode = dig_port->tc_mode; intel_display_power_flush_work(i915); - WARN_ON(intel_display_power_is_enabled(i915, - intel_aux_power_domain(dig_port))); + drm_WARN_ON(&i915->drm, + intel_display_power_is_enabled(i915, + intel_aux_power_domain(dig_port))); icl_tc_phy_disconnect(dig_port); icl_tc_phy_connect(dig_port, required_lanes); - DRM_DEBUG_KMS("Port %s: TC port mode reset (%s -> %s)\n", - dig_port->tc_port_name, - tc_port_mode_name(old_tc_mode), - tc_port_mode_name(dig_port->tc_mode)); + drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n", + dig_port->tc_port_name, + tc_port_mode_name(old_tc_mode), + tc_port_mode_name(dig_port->tc_mode)); } static void @@ -503,7 +510,7 @@ static void __intel_tc_port_lock(struct intel_digital_port *dig_port, intel_tc_port_needs_reset(dig_port)) intel_tc_port_reset_mode(dig_port, required_lanes); - WARN_ON(dig_port->tc_lock_wakeref); + drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref); dig_port->tc_lock_wakeref = wakeref; } @@ -550,7 +557,7 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) enum port port = dig_port->base.port; enum tc_port tc_port = intel_port_to_tc(i915, port); - if (WARN_ON(tc_port == PORT_TC_NONE)) + if (drm_WARN_ON(&i915->drm, tc_port == PORT_TC_NONE)) return; snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name), diff --git a/drivers/gpu/drm/i915/display/intel_tv.c b/drivers/gpu/drm/i915/display/intel_tv.c index c75e0ceecee6..d2e3a3a323e9 100644 --- a/drivers/gpu/drm/i915/display/intel_tv.c +++ b/drivers/gpu/drm/i915/display/intel_tv.c @@ -33,7 +33,6 @@ #include <drm/drm_atomic_helper.h> #include <drm/drm_crtc.h> #include <drm/drm_edid.h> -#include <drm/i915_drm.h> #include "i915_drv.h" #include "intel_connector.h" @@ -907,7 +906,7 @@ static bool intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - u32 tmp = I915_READ(TV_CTL); + u32 tmp = intel_de_read(dev_priv, TV_CTL); *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT; @@ -926,7 +925,8 @@ intel_enable_tv(struct intel_encoder *encoder, intel_wait_for_vblank(dev_priv, to_intel_crtc(pipe_config->uapi.crtc)->pipe); - I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); + intel_de_write(dev_priv, TV_CTL, + intel_de_read(dev_priv, TV_CTL) | TV_ENC_ENABLE); } static void @@ -937,7 +937,8 @@ intel_disable_tv(struct intel_encoder *encoder, struct drm_device *dev = encoder->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); + intel_de_write(dev_priv, TV_CTL, + intel_de_read(dev_priv, TV_CTL) & ~TV_ENC_ENABLE); } static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state) @@ -1095,11 +1096,11 @@ intel_tv_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); - tv_ctl = I915_READ(TV_CTL); - hctl1 = I915_READ(TV_H_CTL_1); - hctl3 = I915_READ(TV_H_CTL_3); - vctl1 = I915_READ(TV_V_CTL_1); - vctl2 = I915_READ(TV_V_CTL_2); + tv_ctl = intel_de_read(dev_priv, TV_CTL); + hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); + hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); + vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); + vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT; tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT; @@ -1134,17 +1135,17 @@ intel_tv_get_config(struct intel_encoder *encoder, break; } - tmp = I915_READ(TV_WIN_POS); + tmp = intel_de_read(dev_priv, TV_WIN_POS); xpos = tmp >> 16; ypos = tmp & 0xffff; - tmp = I915_READ(TV_WIN_SIZE); + tmp = intel_de_read(dev_priv, TV_WIN_SIZE); xsize = tmp >> 16; ysize = tmp & 0xffff; intel_tv_mode_to_mode(&mode, &tv_mode); - DRM_DEBUG_KMS("TV mode:\n"); + drm_dbg_kms(&dev_priv->drm, "TV mode:\n"); drm_mode_debug_printmodeline(&mode); intel_tv_scale_mode_horiz(&mode, hdisplay, @@ -1200,7 +1201,7 @@ intel_tv_compute_config(struct intel_encoder *encoder, pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; - DRM_DEBUG_KMS("forcing bpc to 8 for TV\n"); + drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n"); pipe_config->pipe_bpp = 8*3; pipe_config->port_clock = tv_mode->clock; @@ -1215,7 +1216,8 @@ intel_tv_compute_config(struct intel_encoder *encoder, extra = adjusted_mode->crtc_vdisplay - vdisplay; if (extra < 0) { - DRM_DEBUG_KMS("No vertical scaling for >1024 pixel wide modes\n"); + drm_dbg_kms(&dev_priv->drm, + "No vertical scaling for >1024 pixel wide modes\n"); return -EINVAL; } @@ -1248,7 +1250,7 @@ intel_tv_compute_config(struct intel_encoder *encoder, tv_conn_state->bypass_vfilter = false; } - DRM_DEBUG_KMS("TV mode:\n"); + drm_dbg_kms(&dev_priv->drm, "TV mode:\n"); drm_mode_debug_printmodeline(adjusted_mode); /* @@ -1380,16 +1382,16 @@ set_tv_mode_timings(struct drm_i915_private *dev_priv, vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) | (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT); - I915_WRITE(TV_H_CTL_1, hctl1); - I915_WRITE(TV_H_CTL_2, hctl2); - I915_WRITE(TV_H_CTL_3, hctl3); - I915_WRITE(TV_V_CTL_1, vctl1); - I915_WRITE(TV_V_CTL_2, vctl2); - I915_WRITE(TV_V_CTL_3, vctl3); - I915_WRITE(TV_V_CTL_4, vctl4); - I915_WRITE(TV_V_CTL_5, vctl5); - I915_WRITE(TV_V_CTL_6, vctl6); - I915_WRITE(TV_V_CTL_7, vctl7); + intel_de_write(dev_priv, TV_H_CTL_1, hctl1); + intel_de_write(dev_priv, TV_H_CTL_2, hctl2); + intel_de_write(dev_priv, TV_H_CTL_3, hctl3); + intel_de_write(dev_priv, TV_V_CTL_1, vctl1); + intel_de_write(dev_priv, TV_V_CTL_2, vctl2); + intel_de_write(dev_priv, TV_V_CTL_3, vctl3); + intel_de_write(dev_priv, TV_V_CTL_4, vctl4); + intel_de_write(dev_priv, TV_V_CTL_5, vctl5); + intel_de_write(dev_priv, TV_V_CTL_6, vctl6); + intel_de_write(dev_priv, TV_V_CTL_7, vctl7); } static void set_color_conversion(struct drm_i915_private *dev_priv, @@ -1398,18 +1400,18 @@ static void set_color_conversion(struct drm_i915_private *dev_priv, if (!color_conversion) return; - I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) | - color_conversion->gy); - I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) | - color_conversion->ay); - I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) | - color_conversion->gu); - I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) | - color_conversion->au); - I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) | - color_conversion->gv); - I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) | - color_conversion->av); + intel_de_write(dev_priv, TV_CSC_Y, + (color_conversion->ry << 16) | color_conversion->gy); + intel_de_write(dev_priv, TV_CSC_Y2, + (color_conversion->by << 16) | color_conversion->ay); + intel_de_write(dev_priv, TV_CSC_U, + (color_conversion->ru << 16) | color_conversion->gu); + intel_de_write(dev_priv, TV_CSC_U2, + (color_conversion->bu << 16) | color_conversion->au); + intel_de_write(dev_priv, TV_CSC_V, + (color_conversion->rv << 16) | color_conversion->gv); + intel_de_write(dev_priv, TV_CSC_V2, + (color_conversion->bv << 16) | color_conversion->av); } static void intel_tv_pre_enable(struct intel_encoder *encoder, @@ -1434,7 +1436,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, if (!tv_mode) return; /* can't happen (mode_prepare prevents this) */ - tv_ctl = I915_READ(TV_CTL); + tv_ctl = intel_de_read(dev_priv, TV_CTL); tv_ctl &= TV_CTL_SAVE; switch (intel_tv->type) { @@ -1511,21 +1513,20 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, set_tv_mode_timings(dev_priv, tv_mode, burst_ena); - I915_WRITE(TV_SC_CTL_1, scctl1); - I915_WRITE(TV_SC_CTL_2, scctl2); - I915_WRITE(TV_SC_CTL_3, scctl3); + intel_de_write(dev_priv, TV_SC_CTL_1, scctl1); + intel_de_write(dev_priv, TV_SC_CTL_2, scctl2); + intel_de_write(dev_priv, TV_SC_CTL_3, scctl3); set_color_conversion(dev_priv, color_conversion); if (INTEL_GEN(dev_priv) >= 4) - I915_WRITE(TV_CLR_KNOBS, 0x00404000); + intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000); else - I915_WRITE(TV_CLR_KNOBS, 0x00606000); + intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000); if (video_levels) - I915_WRITE(TV_CLR_LEVEL, - ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | - (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); + intel_de_write(dev_priv, TV_CLR_LEVEL, + ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); @@ -1533,7 +1534,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, tv_filter_ctl = TV_AUTO_SCALE; if (tv_conn_state->bypass_vfilter) tv_filter_ctl |= TV_V_FILTER_BYPASS; - I915_WRITE(TV_FILTER_CTL_1, tv_filter_ctl); + intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl); xsize = tv_mode->hblank_start - tv_mode->hblank_end; ysize = intel_tv_mode_vdisplay(tv_mode); @@ -1544,20 +1545,25 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, conn_state->tv.margins.right); ysize -= (tv_conn_state->margins.top + tv_conn_state->margins.bottom); - I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos); - I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize); + intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos); + intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize); j = 0; for (i = 0; i < 60; i++) - I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]); + intel_de_write(dev_priv, TV_H_LUMA(i), + tv_mode->filter_table[j++]); for (i = 0; i < 60; i++) - I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]); + intel_de_write(dev_priv, TV_H_CHROMA(i), + tv_mode->filter_table[j++]); for (i = 0; i < 43; i++) - I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]); + intel_de_write(dev_priv, TV_V_LUMA(i), + tv_mode->filter_table[j++]); for (i = 0; i < 43; i++) - I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]); - I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE); - I915_WRITE(TV_CTL, tv_ctl); + intel_de_write(dev_priv, TV_V_CHROMA(i), + tv_mode->filter_table[j++]); + intel_de_write(dev_priv, TV_DAC, + intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE); + intel_de_write(dev_priv, TV_CTL, tv_ctl); } static int @@ -1581,8 +1587,8 @@ intel_tv_detect_type(struct intel_tv *intel_tv, spin_unlock_irq(&dev_priv->irq_lock); } - save_tv_dac = tv_dac = I915_READ(TV_DAC); - save_tv_ctl = tv_ctl = I915_READ(TV_CTL); + save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC); + save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL); /* Poll for TV detection */ tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK); @@ -1608,15 +1614,15 @@ intel_tv_detect_type(struct intel_tv *intel_tv, tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); - I915_WRITE(TV_CTL, tv_ctl); - I915_WRITE(TV_DAC, tv_dac); - POSTING_READ(TV_DAC); + intel_de_write(dev_priv, TV_CTL, tv_ctl); + intel_de_write(dev_priv, TV_DAC, tv_dac); + intel_de_posting_read(dev_priv, TV_DAC); intel_wait_for_vblank(dev_priv, intel_crtc->pipe); type = -1; - tv_dac = I915_READ(TV_DAC); - DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac); + tv_dac = intel_de_read(dev_priv, TV_DAC); + drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac); /* * A B C * 0 1 1 Composite @@ -1624,22 +1630,25 @@ intel_tv_detect_type(struct intel_tv *intel_tv, * 0 0 0 Component */ if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { - DRM_DEBUG_KMS("Detected Composite TV connection\n"); + drm_dbg_kms(&dev_priv->drm, + "Detected Composite TV connection\n"); type = DRM_MODE_CONNECTOR_Composite; } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { - DRM_DEBUG_KMS("Detected S-Video TV connection\n"); + drm_dbg_kms(&dev_priv->drm, + "Detected S-Video TV connection\n"); type = DRM_MODE_CONNECTOR_SVIDEO; } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { - DRM_DEBUG_KMS("Detected Component TV connection\n"); + drm_dbg_kms(&dev_priv->drm, + "Detected Component TV connection\n"); type = DRM_MODE_CONNECTOR_Component; } else { - DRM_DEBUG_KMS("Unrecognised TV connection\n"); + drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n"); type = -1; } - I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); - I915_WRITE(TV_CTL, save_tv_ctl); - POSTING_READ(TV_CTL); + intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); + intel_de_write(dev_priv, TV_CTL, save_tv_ctl); + intel_de_posting_read(dev_priv, TV_CTL); /* For unknown reasons the hw barfs if we don't do this vblank wait. */ intel_wait_for_vblank(dev_priv, intel_crtc->pipe); @@ -1794,7 +1803,7 @@ intel_tv_get_modes(struct drm_connector *connector) */ intel_tv_mode_to_mode(mode, tv_mode); if (count == 0) { - DRM_DEBUG_KMS("TV mode:\n"); + drm_dbg_kms(&dev_priv->drm, "TV mode:\n"); drm_mode_debug_printmodeline(mode); } intel_tv_scale_mode_horiz(mode, input->w, 0, 0); @@ -1870,11 +1879,11 @@ intel_tv_init(struct drm_i915_private *dev_priv) int i, initial_mode = 0; struct drm_connector_state *state; - if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) + if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) return; if (!intel_bios_is_tv_present(dev_priv)) { - DRM_DEBUG_KMS("Integrated TV is not present.\n"); + drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n"); return; } @@ -1882,15 +1891,15 @@ intel_tv_init(struct drm_i915_private *dev_priv) * Sanity check the TV output by checking to see if the * DAC register holds a value */ - save_tv_dac = I915_READ(TV_DAC); + save_tv_dac = intel_de_read(dev_priv, TV_DAC); - I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); - tv_dac_on = I915_READ(TV_DAC); + intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); + tv_dac_on = intel_de_read(dev_priv, TV_DAC); - I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); - tv_dac_off = I915_READ(TV_DAC); + intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); + tv_dac_off = intel_de_read(dev_priv, TV_DAC); - I915_WRITE(TV_DAC, save_tv_dac); + intel_de_write(dev_priv, TV_DAC, save_tv_dac); /* * If the register does not hold the state change enable diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 4d0c23b29248..05c7cbe32eb4 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -111,7 +111,7 @@ enum bdb_block_id { BDB_LVDS_LFP_DATA_PTRS = 41, BDB_LVDS_LFP_DATA = 42, BDB_LVDS_BACKLIGHT = 43, - BDB_LVDS_POWER = 44, + BDB_LFP_POWER = 44, BDB_MIPI_CONFIG = 52, BDB_MIPI_SEQUENCE = 53, BDB_COMPRESSION_PARAMETERS = 56, diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 9e6aaa302e40..95ad87d4ccb3 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -6,8 +6,6 @@ * Manasi Navare <manasi.d.navare@intel.com> */ -#include <drm/i915_drm.h> - #include "i915_drv.h" #include "intel_display_types.h" #include "intel_dsi.h" @@ -374,7 +372,7 @@ static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) return false; /* There's no pipe A DSC engine on ICL */ - WARN_ON(crtc->pipe == PIPE_A); + drm_WARN_ON(&i915->drm, crtc->pipe == PIPE_A); return true; } @@ -518,119 +516,149 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_422_ENABLE; if (vdsc_cfg->vbr_enable) pps_val |= DSC_VBR_ENABLE; - DRM_INFO("PPS0 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_0, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_1 registers */ pps_val = 0; pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); - DRM_INFO("PPS1 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_1, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_2 registers */ pps_val = 0; pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); - DRM_INFO("PPS2 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_2, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_3 registers */ pps_val = 0; pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | DSC_SLICE_WIDTH(vdsc_cfg->slice_width); - DRM_INFO("PPS3 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_3, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_4 registers */ pps_val = 0; pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); - DRM_INFO("PPS4 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_4, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_5 registers */ pps_val = 0; pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); - DRM_INFO("PPS5 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_5, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_6 registers */ @@ -639,80 +667,100 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, DSC_FIRST_LINE_BPG_OFFSET(vdsc_cfg->first_line_bpg_offset) | DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); - DRM_INFO("PPS6 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_6, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_7 registers */ pps_val = 0; pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); - DRM_INFO("PPS7 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_7, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_8 registers */ pps_val = 0; pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); - DRM_INFO("PPS8 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_8, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_9 registers */ pps_val = 0; pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); - DRM_INFO("PPS9 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_9, pps_val); + intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, + pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), + pps_val); } /* Populate PICTURE_PARAMETER_SET_10 registers */ @@ -721,20 +769,25 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) | DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); - DRM_INFO("PPS10 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_10, pps_val); + intel_de_write(dev_priv, + DSCC_PICTURE_PARAMETER_SET_10, pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), + pps_val); } /* Populate Picture parameter set 16 */ @@ -744,20 +797,25 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, vdsc_cfg->slice_width) | DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / vdsc_cfg->slice_height); - DRM_INFO("PPS16 = 0x%08x\n", pps_val); + drm_info(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val); if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); + intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16, + pps_val); /* * If 2 VDSC instances are needed, configure PPS for second * VDSC */ if (crtc_state->dsc.dsc_split) - I915_WRITE(DSCC_PICTURE_PARAMETER_SET_16, pps_val); + intel_de_write(dev_priv, + DSCC_PICTURE_PARAMETER_SET_16, pps_val); } else { - I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); + intel_de_write(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), + pps_val); if (crtc_state->dsc.dsc_split) - I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), - pps_val); + intel_de_write(dev_priv, + ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), + pps_val); } /* Populate the RC_BUF_THRESH registers */ @@ -766,42 +824,50 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, rc_buf_thresh_dword[i / 4] |= (u32)(vdsc_cfg->rc_buf_thresh[i] << BITS_PER_BYTE * (i % 4)); - DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, + drm_info(&dev_priv->drm, " RC_BUF_THRESH%d = 0x%08x\n", i, rc_buf_thresh_dword[i / 4]); } if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); - I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); - I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); - I915_WRITE(DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); + intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0, + rc_buf_thresh_dword[0]); + intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_0_UDW, + rc_buf_thresh_dword[1]); + intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1, + rc_buf_thresh_dword[2]); + intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, + rc_buf_thresh_dword[3]); if (crtc_state->dsc.dsc_split) { - I915_WRITE(DSCC_RC_BUF_THRESH_0, - rc_buf_thresh_dword[0]); - I915_WRITE(DSCC_RC_BUF_THRESH_0_UDW, - rc_buf_thresh_dword[1]); - I915_WRITE(DSCC_RC_BUF_THRESH_1, - rc_buf_thresh_dword[2]); - I915_WRITE(DSCC_RC_BUF_THRESH_1_UDW, - rc_buf_thresh_dword[3]); + intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, + rc_buf_thresh_dword[0]); + intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, + rc_buf_thresh_dword[1]); + intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1, + rc_buf_thresh_dword[2]); + intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_1_UDW, + rc_buf_thresh_dword[3]); } } else { - I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0(pipe), - rc_buf_thresh_dword[0]); - I915_WRITE(ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), - rc_buf_thresh_dword[1]); - I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1(pipe), - rc_buf_thresh_dword[2]); - I915_WRITE(ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), - rc_buf_thresh_dword[3]); + intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); if (crtc_state->dsc.dsc_split) { - I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0(pipe), - rc_buf_thresh_dword[0]); - I915_WRITE(ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), - rc_buf_thresh_dword[1]); - I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1(pipe), - rc_buf_thresh_dword[2]); - I915_WRITE(ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), - rc_buf_thresh_dword[3]); + intel_de_write(dev_priv, + ICL_DSC1_RC_BUF_THRESH_0(pipe), + rc_buf_thresh_dword[0]); + intel_de_write(dev_priv, + ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe), + rc_buf_thresh_dword[1]); + intel_de_write(dev_priv, + ICL_DSC1_RC_BUF_THRESH_1(pipe), + rc_buf_thresh_dword[2]); + intel_de_write(dev_priv, + ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe), + rc_buf_thresh_dword[3]); } } @@ -815,78 +881,94 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, RC_MAX_QP_SHIFT) | (vdsc_cfg->rc_range_params[i].range_min_qp << RC_MIN_QP_SHIFT)) << 16 * (i % 2)); - DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, + drm_info(&dev_priv->drm, " RC_RANGE_PARAM_%d = 0x%08x\n", i, rc_range_params_dword[i / 2]); } if (!is_pipe_dsc(crtc_state)) { - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, - rc_range_params_dword[0]); - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, - rc_range_params_dword[1]); - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1, - rc_range_params_dword[2]); - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_1_UDW, - rc_range_params_dword[3]); - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2, - rc_range_params_dword[4]); - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_2_UDW, - rc_range_params_dword[5]); - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3, - rc_range_params_dword[6]); - I915_WRITE(DSCA_RC_RANGE_PARAMETERS_3_UDW, - rc_range_params_dword[7]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); if (crtc_state->dsc.dsc_split) { - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0, - rc_range_params_dword[0]); - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_0_UDW, - rc_range_params_dword[1]); - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1, - rc_range_params_dword[2]); - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_1_UDW, - rc_range_params_dword[3]); - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2, - rc_range_params_dword[4]); - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_2_UDW, - rc_range_params_dword[5]); - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3, - rc_range_params_dword[6]); - I915_WRITE(DSCC_RC_RANGE_PARAMETERS_3_UDW, - rc_range_params_dword[7]); + intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, + rc_range_params_dword[0]); + intel_de_write(dev_priv, + DSCC_RC_RANGE_PARAMETERS_0_UDW, + rc_range_params_dword[1]); + intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_1, + rc_range_params_dword[2]); + intel_de_write(dev_priv, + DSCC_RC_RANGE_PARAMETERS_1_UDW, + rc_range_params_dword[3]); + intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_2, + rc_range_params_dword[4]); + intel_de_write(dev_priv, + DSCC_RC_RANGE_PARAMETERS_2_UDW, + rc_range_params_dword[5]); + intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_3, + rc_range_params_dword[6]); + intel_de_write(dev_priv, + DSCC_RC_RANGE_PARAMETERS_3_UDW, + rc_range_params_dword[7]); } } else { - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), - rc_range_params_dword[0]); - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), - rc_range_params_dword[1]); - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), - rc_range_params_dword[2]); - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), - rc_range_params_dword[3]); - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), - rc_range_params_dword[4]); - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), - rc_range_params_dword[5]); - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), - rc_range_params_dword[6]); - I915_WRITE(ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), - rc_range_params_dword[7]); + intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + intel_de_write(dev_priv, + ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + intel_de_write(dev_priv, + ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + intel_de_write(dev_priv, + ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + intel_de_write(dev_priv, + ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); if (crtc_state->dsc.dsc_split) { - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), - rc_range_params_dword[0]); - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), - rc_range_params_dword[1]); - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), - rc_range_params_dword[2]); - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), - rc_range_params_dword[3]); - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), - rc_range_params_dword[4]); - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), - rc_range_params_dword[5]); - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), - rc_range_params_dword[6]); - I915_WRITE(ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), - rc_range_params_dword[7]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), + rc_range_params_dword[0]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe), + rc_range_params_dword[1]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe), + rc_range_params_dword[2]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe), + rc_range_params_dword[3]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe), + rc_range_params_dword[4]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe), + rc_range_params_dword[5]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe), + rc_range_params_dword[6]); + intel_de_write(dev_priv, + ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe), + rc_range_params_dword[7]); } } } @@ -912,11 +994,11 @@ void intel_dsc_get_config(struct intel_encoder *encoder, return; if (!is_pipe_dsc(crtc_state)) { - dss_ctl1 = I915_READ(DSS_CTL1); - dss_ctl2 = I915_READ(DSS_CTL2); + dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); + dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); } else { - dss_ctl1 = I915_READ(ICL_PIPE_DSS_CTL1(pipe)); - dss_ctl2 = I915_READ(ICL_PIPE_DSS_CTL2(pipe)); + dss_ctl1 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); + dss_ctl2 = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL2(pipe)); } crtc_state->dsc.compression_enable = dss_ctl2 & LEFT_BRANCH_VDSC_ENABLE; @@ -930,9 +1012,10 @@ void intel_dsc_get_config(struct intel_encoder *encoder, /* PPS1 */ if (!is_pipe_dsc(crtc_state)) - val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); + val = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); else - val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); + val = intel_de_read(dev_priv, + ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); vdsc_cfg->bits_per_pixel = val; crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; out: @@ -1013,8 +1096,8 @@ void intel_dsc_enable(struct intel_encoder *encoder, dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } - I915_WRITE(dss_ctl1_reg, dss_ctl1_val); - I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val); + intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val); } void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) @@ -1035,17 +1118,17 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); } - dss_ctl1_val = I915_READ(dss_ctl1_reg); + dss_ctl1_val = intel_de_read(dev_priv, dss_ctl1_reg); if (dss_ctl1_val & JOINER_ENABLE) dss_ctl1_val &= ~JOINER_ENABLE; - I915_WRITE(dss_ctl1_reg, dss_ctl1_val); + intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1_val); - dss_ctl2_val = I915_READ(dss_ctl2_reg); + dss_ctl2_val = intel_de_read(dev_priv, dss_ctl2_reg); if (dss_ctl2_val & LEFT_BRANCH_VDSC_ENABLE || dss_ctl2_val & RIGHT_BRANCH_VDSC_ENABLE) dss_ctl2_val &= ~(LEFT_BRANCH_VDSC_ENABLE | RIGHT_BRANCH_VDSC_ENABLE); - I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2_val); /* Disable Power wells for VDSC/joining */ intel_display_power_put_unchecked(dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_vga.c b/drivers/gpu/drm/i915/display/intel_vga.c index 2ff7293986d4..be333699c515 100644 --- a/drivers/gpu/drm/i915/display/intel_vga.c +++ b/drivers/gpu/drm/i915/display/intel_vga.c @@ -9,6 +9,7 @@ #include <drm/i915_drm.h> #include "i915_drv.h" +#include "intel_de.h" #include "intel_vga.h" static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915) @@ -36,16 +37,17 @@ void intel_vga_disable(struct drm_i915_private *dev_priv) vga_put(pdev, VGA_RSRC_LEGACY_IO); udelay(300); - I915_WRITE(vga_reg, VGA_DISP_DISABLE); - POSTING_READ(vga_reg); + intel_de_write(dev_priv, vga_reg, VGA_DISP_DISABLE); + intel_de_posting_read(dev_priv, vga_reg); } void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv) { i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv); - if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { - DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); + if (!(intel_de_read(dev_priv, vga_reg) & VGA_DISP_DISABLE)) { + drm_dbg_kms(&dev_priv->drm, + "Something enabled VGA plane, disabling it\n"); intel_vga_disable(dev_priv); } } @@ -98,7 +100,7 @@ intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode) u16 gmch_ctrl; if (pci_read_config_word(i915->bridge_dev, reg, &gmch_ctrl)) { - DRM_ERROR("failed to read control word\n"); + drm_err(&i915->drm, "failed to read control word\n"); return -EIO; } @@ -111,7 +113,7 @@ intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode) gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; if (pci_write_config_word(i915->bridge_dev, reg, gmch_ctrl)) { - DRM_ERROR("failed to write control word\n"); + drm_err(&i915->drm, "failed to write control word\n"); return -EIO; } diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index daf4fc3dab6f..f4c362dc6e15 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -85,7 +85,7 @@ void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port) if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port), mask, 100)) - DRM_ERROR("DPI FIFOs are not empty\n"); + drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); } static void write_data(struct drm_i915_private *dev_priv, @@ -100,7 +100,7 @@ static void write_data(struct drm_i915_private *dev_priv, for (j = 0; j < min_t(u32, len - i, 4); j++) val |= *data++ << 8 * j; - I915_WRITE(reg, val); + intel_de_write(dev_priv, reg, val); } } @@ -111,7 +111,7 @@ static void read_data(struct drm_i915_private *dev_priv, u32 i, j; for (i = 0; i < len; i += 4) { - u32 val = I915_READ(reg); + u32 val = intel_de_read(dev_priv, reg); for (j = 0; j < min_t(u32, len - i, 4); j++) *data++ = val >> 8 * j; @@ -154,29 +154,34 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, if (packet.payload_length) { if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), data_mask, 50)) - DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); + drm_err(&dev_priv->drm, + "Timeout waiting for HS/LP DATA FIFO !full\n"); write_data(dev_priv, data_reg, packet.payload, packet.payload_length); } if (msg->rx_len) { - I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); + intel_de_write(dev_priv, MIPI_INTR_STAT(port), + GEN_READ_DATA_AVAIL); } if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port), ctrl_mask, 50)) { - DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); + drm_err(&dev_priv->drm, + "Timeout waiting for HS/LP CTRL FIFO !full\n"); } - I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); + intel_de_write(dev_priv, ctrl_reg, + header[2] << 16 | header[1] << 8 | header[0]); /* ->rx_len is set only for reads */ if (msg->rx_len) { data_mask = GEN_READ_DATA_AVAIL; if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), data_mask, 50)) - DRM_ERROR("Timeout waiting for read data.\n"); + drm_err(&dev_priv->drm, + "Timeout waiting for read data.\n"); read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); } @@ -223,17 +228,19 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, cmd |= DPI_LP_MODE; /* clear bit */ - I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); + intel_de_write(dev_priv, MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); /* XXX: old code skips write if control unchanged */ - if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) - DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd); + if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) + drm_dbg_kms(&dev_priv->drm, + "Same special packet %02x twice in a row.\n", cmd); - I915_WRITE(MIPI_DPI_CONTROL(port), cmd); + intel_de_write(dev_priv, MIPI_DPI_CONTROL(port), cmd); mask = SPL_PKT_SENT_INTERRUPT; if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port), mask, 100)) - DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); + drm_err(&dev_priv->drm, + "Video mode command 0x%08x send failed.\n", cmd); return 0; } @@ -265,7 +272,7 @@ static int intel_dsi_compute_config(struct intel_encoder *encoder, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int ret; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; if (fixed_mode) { @@ -328,36 +335,37 @@ static bool glk_dsi_enable_io(struct intel_encoder *encoder) * Power ON MIPI IO first and then write into IO reset and LP wake bits */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(MIPI_CTRL(port)); - I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); + intel_de_write(dev_priv, MIPI_CTRL(port), + tmp | GLK_MIPIIO_ENABLE); } /* Put the IO into reset */ - tmp = I915_READ(MIPI_CTRL(PORT_A)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); tmp &= ~GLK_MIPIIO_RESET_RELEASED; - I915_WRITE(MIPI_CTRL(PORT_A), tmp); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); /* Program LP Wake */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(MIPI_CTRL(port)); - if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); + if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) tmp &= ~GLK_LP_WAKE; else tmp |= GLK_LP_WAKE; - I915_WRITE(MIPI_CTRL(port), tmp); + intel_de_write(dev_priv, MIPI_CTRL(port), tmp); } /* Wait for Pwr ACK */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, 20)) - DRM_ERROR("MIPIO port is powergated\n"); + drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); } /* Check for cold boot scenario */ for_each_dsi_port(port, intel_dsi->ports) { cold_boot |= - !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY); + !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); } return cold_boot; @@ -374,48 +382,49 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, 20)) - DRM_ERROR("PHY is not ON\n"); + drm_err(&dev_priv->drm, "PHY is not ON\n"); } /* Get IO out of reset */ - val = I915_READ(MIPI_CTRL(PORT_A)); - I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); + val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), + val | GLK_MIPIIO_RESET_RELEASED); /* Get IO out of Low power state*/ for_each_dsi_port(port, intel_dsi->ports) { - if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { - val = I915_READ(MIPI_DEVICE_READY(port)); + if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= DEVICE_READY; - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); usleep_range(10, 15); } else { /* Enter ULPS */ - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_ENTER | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); /* Wait for ULPS active */ if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 20)) - DRM_ERROR("ULPS not active\n"); + drm_err(&dev_priv->drm, "ULPS not active\n"); /* Exit ULPS */ - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_EXIT | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); /* Enter Normal Mode */ - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); - val = I915_READ(MIPI_CTRL(port)); + val = intel_de_read(dev_priv, MIPI_CTRL(port)); val &= ~GLK_LP_WAKE; - I915_WRITE(MIPI_CTRL(port), val); + intel_de_write(dev_priv, MIPI_CTRL(port), val); } } @@ -423,14 +432,16 @@ static void glk_dsi_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, 20)) - DRM_ERROR("Date lane not in STOP state\n"); + drm_err(&dev_priv->drm, + "Date lane not in STOP state\n"); } /* Wait for AFE LATCH */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT, 20)) - DRM_ERROR("D-PHY not entering LP-11 state\n"); + drm_err(&dev_priv->drm, + "D-PHY not entering LP-11 state\n"); } } @@ -441,23 +452,24 @@ static void bxt_dsi_device_ready(struct intel_encoder *encoder) enum port port; u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); /* Enable MIPI PHY transparent latch */ for_each_dsi_port(port, intel_dsi->ports) { - val = I915_READ(BXT_MIPI_PORT_CTRL(port)); - I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); + val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)); + intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port), + val | LP_OUTPUT_HOLD); usleep_range(2000, 2500); } /* Clear ULPS and set device ready */ for_each_dsi_port(port, intel_dsi->ports) { - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); usleep_range(2000, 2500); val |= DEVICE_READY; - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); } } @@ -468,7 +480,7 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) enum port port; u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); vlv_flisdsi_get(dev_priv); /* program rcomp for compliance, reduce from 50 ohms to 45 ohms @@ -481,21 +493,25 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + ULPS_STATE_ENTER); usleep_range(2500, 3000); /* Enable MIPI PHY transparent latch * Common bit for both MIPI Port A & MIPI Port C * No similar bit in MIPI Port C reg */ - val = I915_READ(MIPI_PORT_CTRL(PORT_A)); - I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); + val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)); + intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A), + val | LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + ULPS_STATE_EXIT); usleep_range(2500, 3000); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY); usleep_range(2500, 3000); } } @@ -521,24 +537,25 @@ static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder) /* Enter ULPS */ for_each_dsi_port(port, intel_dsi->ports) { - val = I915_READ(MIPI_DEVICE_READY(port)); + val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); val &= ~ULPS_STATE_MASK; val |= (ULPS_STATE_ENTER | DEVICE_READY); - I915_WRITE(MIPI_DEVICE_READY(port), val); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), val); } /* Wait for MIPI PHY status bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, 20)) - DRM_ERROR("PHY is not turning OFF\n"); + drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); } /* Wait for Pwr ACK bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, 20)) - DRM_ERROR("MIPI IO Port is not powergated\n"); + drm_err(&dev_priv->drm, + "MIPI IO Port is not powergated\n"); } } @@ -550,22 +567,22 @@ static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder) u32 tmp; /* Put the IO into reset */ - tmp = I915_READ(MIPI_CTRL(PORT_A)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); tmp &= ~GLK_MIPIIO_RESET_RELEASED; - I915_WRITE(MIPI_CTRL(PORT_A), tmp); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), tmp); /* Wait for MIPI PHY status bit to unset */ for_each_dsi_port(port, intel_dsi->ports) { if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, 20)) - DRM_ERROR("PHY is not turning OFF\n"); + drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); } /* Clear MIPI mode */ for_each_dsi_port(port, intel_dsi->ports) { - tmp = I915_READ(MIPI_CTRL(port)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= ~GLK_MIPIIO_ENABLE; - I915_WRITE(MIPI_CTRL(port), tmp); + intel_de_write(dev_priv, MIPI_CTRL(port), tmp); } } @@ -581,23 +598,23 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); enum port port; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); u32 val; - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | - ULPS_STATE_ENTER); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | - ULPS_STATE_EXIT); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY | ULPS_STATE_EXIT); usleep_range(2000, 2500); - I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | - ULPS_STATE_ENTER); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), + DEVICE_READY | ULPS_STATE_ENTER); usleep_range(2000, 2500); /* @@ -607,14 +624,14 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && intel_de_wait_for_clear(dev_priv, port_ctrl, AFE_LATCHOUT, 30)) - DRM_ERROR("DSI LP not going Low\n"); + drm_err(&dev_priv->drm, "DSI LP not going Low\n"); /* Disable MIPI PHY transparent latch */ - val = I915_READ(port_ctrl); - I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); + val = intel_de_read(dev_priv, port_ctrl); + intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD); usleep_range(1000, 1500); - I915_WRITE(MIPI_DEVICE_READY(port), 0x00); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x00); usleep_range(2000, 2500); } } @@ -631,18 +648,20 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, u32 temp; if (IS_GEN9_LP(dev_priv)) { for_each_dsi_port(port, intel_dsi->ports) { - temp = I915_READ(MIPI_CTRL(port)); + temp = intel_de_read(dev_priv, + MIPI_CTRL(port)); temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << BXT_PIXEL_OVERLAP_CNT_SHIFT; - I915_WRITE(MIPI_CTRL(port), temp); + intel_de_write(dev_priv, MIPI_CTRL(port), + temp); } } else { - temp = I915_READ(VLV_CHICKEN_3); + temp = intel_de_read(dev_priv, VLV_CHICKEN_3); temp &= ~PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << PIXEL_OVERLAP_CNT_SHIFT; - I915_WRITE(VLV_CHICKEN_3, temp); + intel_de_write(dev_priv, VLV_CHICKEN_3, temp); } } @@ -651,7 +670,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); u32 temp; - temp = I915_READ(port_ctrl); + temp = intel_de_read(dev_priv, port_ctrl); temp &= ~LANE_CONFIGURATION_MASK; temp &= ~DUAL_LINK_MODE_MASK; @@ -671,8 +690,8 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, temp |= DITHERING_ENABLE; /* assert ip_tg_enable signal */ - I915_WRITE(port_ctrl, temp | DPI_ENABLE); - POSTING_READ(port_ctrl); + intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE); + intel_de_posting_read(dev_priv, port_ctrl); } } @@ -689,9 +708,9 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) u32 temp; /* de-assert ip_tg_enable signal */ - temp = I915_READ(port_ctrl); - I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); - POSTING_READ(port_ctrl); + temp = intel_de_read(dev_priv, port_ctrl); + intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE); + intel_de_posting_read(dev_priv, port_ctrl); } } @@ -753,7 +772,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, u32 val; bool glk_cold_boot = false; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); @@ -771,22 +790,22 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, if (IS_BROXTON(dev_priv)) { /* Add MIPI IO reset programming for modeset */ - val = I915_READ(BXT_P_CR_GT_DISP_PWRON); - I915_WRITE(BXT_P_CR_GT_DISP_PWRON, - val | MIPIO_RST_CTRL); + val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); + intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, + val | MIPIO_RST_CTRL); /* Power up DSI regulator */ - I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); - I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, 0); } if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { u32 val; /* Disable DPOunit clock gating, can stall pipe */ - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); val |= DPOUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } if (!IS_GEMINILAKE(dev_priv)) @@ -820,7 +839,8 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, * recommendation, port should be enabled befor plane & pipe */ if (is_cmd_mode(intel_dsi)) { for_each_dsi_port(port, intel_dsi->ports) - I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); + intel_de_write(dev_priv, + MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON); intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); } else { @@ -838,6 +858,15 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); } +static void bxt_dsi_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) +{ + WARN_ON(crtc_state->has_pch_encoder); + + intel_crtc_vblank_on(crtc_state); +} + /* * DSI port disable has to be done after pipe and plane disable, so we do it in * the post_disable hook. @@ -886,7 +915,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, enum port port; u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); if (IS_GEN9_LP(dev_priv)) { intel_crtc_vblank_off(old_crtc_state); @@ -917,13 +946,14 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, if (IS_BROXTON(dev_priv)) { /* Power down DSI regulator to save power */ - I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); - I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG, STAP_SELECT); + intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL, + HS_IO_CTRL_SELECT); /* Add MIPI IO reset programming for modeset */ - val = I915_READ(BXT_P_CR_GT_DISP_PWRON); - I915_WRITE(BXT_P_CR_GT_DISP_PWRON, - val & ~MIPIO_RST_CTRL); + val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); + intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, + val & ~MIPIO_RST_CTRL); } if (IS_GEN9_LP(dev_priv)) { @@ -933,9 +963,9 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, vlv_dsi_pll_disable(encoder); - val = I915_READ(DSPCLK_GATE_D); + val = intel_de_read(dev_priv, DSPCLK_GATE_D); val &= ~DPOUNIT_CLOCK_GATE_DISABLE; - I915_WRITE(DSPCLK_GATE_D, val); + intel_de_write(dev_priv, DSPCLK_GATE_D, val); } /* Assert reset */ @@ -960,7 +990,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, enum port port; bool active = false; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); wakeref = intel_display_power_get_if_enabled(dev_priv, encoder->power_domain); @@ -979,7 +1009,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); - bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; + bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; /* * Due to some hardware limitations on VLV/CHV, the DPI enable @@ -988,26 +1018,27 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, */ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && port == PORT_C) - enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; + enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE; /* Try command mode if video mode not enabled */ if (!enabled) { - u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port)); + u32 tmp = intel_de_read(dev_priv, + MIPI_DSI_FUNC_PRG(port)); enabled = tmp & CMD_MODE_DATA_WIDTH_MASK; } if (!enabled) continue; - if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) + if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) continue; if (IS_GEN9_LP(dev_priv)) { - u32 tmp = I915_READ(MIPI_CTRL(port)); + u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= BXT_PIPE_SELECT_MASK; tmp >>= BXT_PIPE_SELECT_SHIFT; - if (WARN_ON(tmp > PIPE_C)) + if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) continue; *pipe = tmp; @@ -1051,11 +1082,11 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, * encoder->get_hw_state() returns true. */ for_each_dsi_port(port, intel_dsi->ports) { - if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) + if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE) break; } - fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; + fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK; bpp = mipi_dsi_pixel_format_to_bpp( pixel_format_from_register_bits(fmt)); @@ -1067,21 +1098,24 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, /* In terms of pixels */ adjusted_mode->crtc_hdisplay = - I915_READ(BXT_MIPI_TRANS_HACTIVE(port)); + intel_de_read(dev_priv, + BXT_MIPI_TRANS_HACTIVE(port)); adjusted_mode->crtc_vdisplay = - I915_READ(BXT_MIPI_TRANS_VACTIVE(port)); + intel_de_read(dev_priv, + BXT_MIPI_TRANS_VACTIVE(port)); adjusted_mode->crtc_vtotal = - I915_READ(BXT_MIPI_TRANS_VTOTAL(port)); + intel_de_read(dev_priv, + BXT_MIPI_TRANS_VTOTAL(port)); hactive = adjusted_mode->crtc_hdisplay; - hfp = I915_READ(MIPI_HFP_COUNT(port)); + hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)); /* * Meaningful for video mode non-burst sync pulse mode only, * can be zero for non-burst sync events and burst modes */ - hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port)); - hbp = I915_READ(MIPI_HBP_COUNT(port)); + hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)); + hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)); /* harizontal values are in terms of high speed byte clock */ hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, @@ -1098,9 +1132,9 @@ static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder, } /* vertical values are in terms of lines */ - vfp = I915_READ(MIPI_VFP_COUNT(port)); - vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port)); - vbp = I915_READ(MIPI_VBP_COUNT(port)); + vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)); + vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)); + vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)); adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; @@ -1191,7 +1225,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 pclk; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); @@ -1268,26 +1302,29 @@ static void set_dsi_timings(struct drm_encoder *encoder, * vactive, as they are calculated per channel basis, * whereas these values should be based on resolution. */ - I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), - adjusted_mode->crtc_hdisplay); - I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), - adjusted_mode->crtc_vdisplay); - I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), - adjusted_mode->crtc_vtotal); + intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port), + adjusted_mode->crtc_hdisplay); + intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port), + adjusted_mode->crtc_vdisplay); + intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port), + adjusted_mode->crtc_vtotal); } - I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); - I915_WRITE(MIPI_HFP_COUNT(port), hfp); + intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port), + hactive); + intel_de_write(dev_priv, MIPI_HFP_COUNT(port), hfp); /* meaningful for video mode non-burst sync pulse mode only, * can be zero for non-burst sync events and burst modes */ - I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); - I915_WRITE(MIPI_HBP_COUNT(port), hbp); + intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port), + hsync); + intel_de_write(dev_priv, MIPI_HBP_COUNT(port), hbp); /* vertical values are in terms of lines */ - I915_WRITE(MIPI_VFP_COUNT(port), vfp); - I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); - I915_WRITE(MIPI_VBP_COUNT(port), vbp); + intel_de_write(dev_priv, MIPI_VFP_COUNT(port), vfp); + intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port), + vsync); + intel_de_write(dev_priv, MIPI_VBP_COUNT(port), vbp); } } @@ -1322,7 +1359,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, u32 val, tmp; u16 mode_hdisplay; - DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); + drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(intel_crtc->pipe)); mode_hdisplay = adjusted_mode->crtc_hdisplay; @@ -1338,35 +1375,35 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * escape clock divider, 20MHz, shared for A and C. * device ready must be off when doing this! txclkesc? */ - tmp = I915_READ(MIPI_CTRL(PORT_A)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)); tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(PORT_A), tmp | - ESCAPE_CLOCK_DIVIDER_1); + intel_de_write(dev_priv, MIPI_CTRL(PORT_A), + tmp | ESCAPE_CLOCK_DIVIDER_1); /* read request priority is per pipe */ - tmp = I915_READ(MIPI_CTRL(port)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= ~READ_REQUEST_PRIORITY_MASK; - I915_WRITE(MIPI_CTRL(port), tmp | - READ_REQUEST_PRIORITY_HIGH); + intel_de_write(dev_priv, MIPI_CTRL(port), + tmp | READ_REQUEST_PRIORITY_HIGH); } else if (IS_GEN9_LP(dev_priv)) { enum pipe pipe = intel_crtc->pipe; - tmp = I915_READ(MIPI_CTRL(port)); + tmp = intel_de_read(dev_priv, MIPI_CTRL(port)); tmp &= ~BXT_PIPE_SELECT_MASK; tmp |= BXT_PIPE_SELECT(pipe); - I915_WRITE(MIPI_CTRL(port), tmp); + intel_de_write(dev_priv, MIPI_CTRL(port), tmp); } /* XXX: why here, why like this? handling in irq handler?! */ - I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); - I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); + intel_de_write(dev_priv, MIPI_INTR_STAT(port), 0xffffffff); + intel_de_write(dev_priv, MIPI_INTR_EN(port), 0xffffffff); - I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); + intel_de_write(dev_priv, MIPI_DPHY_PARAM(port), + intel_dsi->dphy_reg); - I915_WRITE(MIPI_DPI_RESOLUTION(port), - adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | - mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); + intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port), + adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); } set_dsi_timings(encoder, adjusted_mode); @@ -1393,7 +1430,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, } for_each_dsi_port(port, intel_dsi->ports) { - I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); + intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); /* timeouts for recovery. one frame IIUC. if counter expires, * EOT and stop state. */ @@ -1414,28 +1451,24 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, if (is_vid_mode(intel_dsi) && intel_dsi->video_mode_format == VIDEO_MODE_BURST) { - I915_WRITE(MIPI_HS_TX_TIMEOUT(port), - txbyteclkhs(adjusted_mode->crtc_htotal, bpp, - intel_dsi->lane_count, - intel_dsi->burst_mode_ratio) + 1); + intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), + txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } else { - I915_WRITE(MIPI_HS_TX_TIMEOUT(port), - txbyteclkhs(adjusted_mode->crtc_vtotal * - adjusted_mode->crtc_htotal, - bpp, intel_dsi->lane_count, - intel_dsi->burst_mode_ratio) + 1); + intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port), + txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1); } - I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); - I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), - intel_dsi->turn_arnd_val); - I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), - intel_dsi->rst_timer_val); + intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port), + intel_dsi->lp_rx_timeout); + intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port), + intel_dsi->turn_arnd_val); + intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port), + intel_dsi->rst_timer_val); /* dphy stuff */ /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(port), - txclkesc(intel_dsi->escape_clk_div, 100)); + intel_de_write(dev_priv, MIPI_INIT_COUNT(port), + txclkesc(intel_dsi->escape_clk_div, 100)); if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { /* @@ -1444,24 +1477,25 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * getting used. So write the other port * if not in dual link mode. */ - I915_WRITE(MIPI_INIT_COUNT(port == - PORT_A ? PORT_C : PORT_A), - intel_dsi->init_count); + intel_de_write(dev_priv, + MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), + intel_dsi->init_count); } /* recovery disables */ - I915_WRITE(MIPI_EOT_DISABLE(port), tmp); + intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), tmp); /* in terms of low power clock */ - I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); + intel_de_write(dev_priv, MIPI_INIT_COUNT(port), + intel_dsi->init_count); /* in terms of txbyteclkhs. actual high to low switch + * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. * * XXX: write MIPI_STOP_STATE_STALL? */ - I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), - intel_dsi->hs_to_lp_count); + intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port), + intel_dsi->hs_to_lp_count); /* XXX: low power clock equivalence in terms of byte clock. * the number of byte clocks occupied in one low power clock. @@ -1469,14 +1503,15 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL * ) / 105.??? */ - I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); + intel_de_write(dev_priv, MIPI_LP_BYTECLK(port), + intel_dsi->lp_byte_clk); if (IS_GEMINILAKE(dev_priv)) { - I915_WRITE(MIPI_TLPX_TIME_COUNT(port), - intel_dsi->lp_byte_clk); + intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port), + intel_dsi->lp_byte_clk); /* Shadow of DPHY reg */ - I915_WRITE(MIPI_CLK_LANE_TIMING(port), - intel_dsi->dphy_reg); + intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port), + intel_dsi->dphy_reg); } /* the bw essential for transmitting 16 long packets containing @@ -1484,21 +1519,18 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, * this register in terms of byte clocks. based on dsi transfer * rate and the number of lanes configured the time taken to * transmit 16 long packets in a dsi stream varies. */ - I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); + intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port), + intel_dsi->bw_timer); - I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), - intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | - intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); + intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port), + intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); if (is_vid_mode(intel_dsi)) /* Some panels might have resolution which is not a * multiple of 64 like 1366 x 768. Enable RANDOM * resolution support for such panels by default */ - I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), - intel_dsi->video_frmt_cfg_bits | - intel_dsi->video_mode_format | - IP_TG_CONFIG | - RANDOM_DPI_DISPLAY_RESOLUTION); + intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port), + intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION); } } @@ -1514,19 +1546,19 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { /* Panel commands can be sent when clock is in LP11 */ - I915_WRITE(MIPI_DEVICE_READY(port), 0x0); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x0); if (IS_GEN9_LP(dev_priv)) bxt_dsi_reset_clocks(encoder, port); else vlv_dsi_reset_clocks(encoder, port); - I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); + intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); - val = I915_READ(MIPI_DSI_FUNC_PRG(port)); + val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)); val &= ~VID_MODE_FORMAT_MASK; - I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); + intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port), val); - I915_WRITE(MIPI_DEVICE_READY(port), 0x1); + intel_de_write(dev_priv, MIPI_DEVICE_READY(port), 0x1); } } @@ -1559,59 +1591,6 @@ static const struct drm_connector_funcs intel_dsi_connector_funcs = { .atomic_duplicate_state = intel_digital_connector_duplicate_state, }; -static enum drm_panel_orientation -vlv_dsi_get_hw_panel_orientation(struct intel_connector *connector) -{ - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - struct intel_encoder *encoder = connector->encoder; - enum intel_display_power_domain power_domain; - enum drm_panel_orientation orientation; - struct intel_plane *plane; - struct intel_crtc *crtc; - intel_wakeref_t wakeref; - enum pipe pipe; - u32 val; - - if (!encoder->get_hw_state(encoder, &pipe)) - return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; - - crtc = intel_get_crtc_for_pipe(dev_priv, pipe); - plane = to_intel_plane(crtc->base.primary); - - power_domain = POWER_DOMAIN_PIPE(pipe); - wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); - if (!wakeref) - return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; - - val = I915_READ(DSPCNTR(plane->i9xx_plane)); - - if (!(val & DISPLAY_PLANE_ENABLE)) - orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; - else if (val & DISPPLANE_ROTATE_180) - orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; - else - orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; - - intel_display_power_put(dev_priv, power_domain, wakeref); - - return orientation; -} - -static enum drm_panel_orientation -vlv_dsi_get_panel_orientation(struct intel_connector *connector) -{ - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); - enum drm_panel_orientation orientation; - - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - orientation = vlv_dsi_get_hw_panel_orientation(connector); - if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN) - return orientation; - } - - return intel_dsi_get_panel_orientation(connector); -} - static void vlv_dsi_add_properties(struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(connector->base.dev); @@ -1628,10 +1607,9 @@ static void vlv_dsi_add_properties(struct intel_connector *connector) connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; - connector->base.display_info.panel_orientation = - vlv_dsi_get_panel_orientation(connector); - drm_connector_init_panel_orientation_property( + drm_connector_set_panel_orientation_with_quirk( &connector->base, + intel_dsi_get_panel_orientation(connector), connector->panel.fixed_mode->hdisplay, connector->panel.fixed_mode->vdisplay); } @@ -1703,7 +1681,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul); if (prepare_cnt > PREPARE_CNT_MAX) { - DRM_DEBUG_KMS("prepare count too high %u\n", prepare_cnt); + drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", + prepare_cnt); prepare_cnt = PREPARE_CNT_MAX; } @@ -1723,7 +1702,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) exit_zero_cnt += 1; if (exit_zero_cnt > EXIT_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("exit zero count too high %u\n", exit_zero_cnt); + drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", + exit_zero_cnt); exit_zero_cnt = EXIT_ZERO_CNT_MAX; } @@ -1733,7 +1713,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) * ui_den, ui_num * mul); if (clk_zero_cnt > CLK_ZERO_CNT_MAX) { - DRM_DEBUG_KMS("clock zero count too high %u\n", clk_zero_cnt); + drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", + clk_zero_cnt); clk_zero_cnt = CLK_ZERO_CNT_MAX; } @@ -1742,7 +1723,8 @@ static void vlv_dphy_param_init(struct intel_dsi *intel_dsi) trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul); if (trail_cnt > TRAIL_CNT_MAX) { - DRM_DEBUG_KMS("trail count too high %u\n", trail_cnt); + drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", + trail_cnt); trail_cnt = TRAIL_CNT_MAX; } @@ -1817,7 +1799,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) enum port port; enum pipe pipe; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); /* There is no detection method for MIPI so rely on VBT */ if (!intel_bios_is_dsi_present(dev_priv, &port)) @@ -1849,6 +1831,8 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) intel_encoder->compute_config = intel_dsi_compute_config; intel_encoder->pre_enable = intel_dsi_pre_enable; + if (IS_GEN9_LP(dev_priv)) + intel_encoder->enable = bxt_dsi_enable; intel_encoder->disable = intel_dsi_disable; intel_encoder->post_disable = intel_dsi_post_disable; intel_encoder->get_hw_state = intel_dsi_get_hw_state; @@ -1894,18 +1878,18 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) } if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { - DRM_DEBUG_KMS("no device found\n"); + drm_dbg_kms(&dev_priv->drm, "no device found\n"); goto err; } /* Use clock read-back from current hw-state for fastboot */ current_mode = intel_encoder_current_mode(intel_encoder); if (current_mode) { - DRM_DEBUG_KMS("Calculated pclk %d GOP %d\n", - intel_dsi->pclk, current_mode->clock); + drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", + intel_dsi->pclk, current_mode->clock); if (intel_fuzzy_clock_check(intel_dsi->pclk, current_mode->clock)) { - DRM_DEBUG_KMS("Using GOP pclk\n"); + drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); intel_dsi->pclk = current_mode->clock; } @@ -1933,7 +1917,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) mutex_unlock(&dev->mode_config.mutex); if (!fixed_mode) { - DRM_DEBUG_KMS("no fixed mode\n"); + drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); goto err_cleanup_connector; } diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c index 6b89e67b120f..d0a514301575 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi_pll.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi_pll.c @@ -64,7 +64,7 @@ static int dsi_calc_mnp(struct drm_i915_private *dev_priv, /* target_dsi_clk is expected in kHz */ if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { - DRM_ERROR("DSI CLK Out of Range\n"); + drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); return -ECHRNG; } @@ -126,7 +126,7 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, ret = dsi_calc_mnp(dev_priv, config, dsi_clk); if (ret) { - DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); + drm_dbg_kms(&dev_priv->drm, "dsi_calc_mnp failed\n"); return ret; } @@ -138,8 +138,8 @@ int vlv_dsi_pll_compute(struct intel_encoder *encoder, config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; - DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", - config->dsi_pll.div, config->dsi_pll.ctrl); + drm_dbg_kms(&dev_priv->drm, "dsi pll div %08x, ctrl %08x\n", + config->dsi_pll.div, config->dsi_pll.ctrl); return 0; } @@ -149,7 +149,7 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); vlv_cck_get(dev_priv); @@ -169,12 +169,12 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder, DSI_PLL_LOCK, 20)) { vlv_cck_put(dev_priv); - DRM_ERROR("DSI PLL lock failed\n"); + drm_err(&dev_priv->drm, "DSI PLL lock failed\n"); return; } vlv_cck_put(dev_priv); - DRM_DEBUG_KMS("DSI PLL locked\n"); + drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); } void vlv_dsi_pll_disable(struct intel_encoder *encoder) @@ -182,7 +182,7 @@ void vlv_dsi_pll_disable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 tmp; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); vlv_cck_get(dev_priv); @@ -201,7 +201,7 @@ bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) u32 mask; mask = BXT_DSI_PLL_DO_ENABLE | BXT_DSI_PLL_LOCKED; - val = I915_READ(BXT_DSI_PLL_ENABLE); + val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); enabled = (val & mask) == mask; if (!enabled) @@ -215,15 +215,17 @@ bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv) * times, and since accessing DSI registers with invalid dividers * causes a system hang. */ - val = I915_READ(BXT_DSI_PLL_CTL); + val = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); if (IS_GEMINILAKE(dev_priv)) { if (!(val & BXT_DSIA_16X_MASK)) { - DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val); + drm_dbg(&dev_priv->drm, + "Invalid PLL divider (%08x)\n", val); enabled = false; } } else { if (!(val & BXT_DSIA_16X_MASK) || !(val & BXT_DSIC_16X_MASK)) { - DRM_DEBUG_DRIVER("Invalid PLL divider (%08x)\n", val); + drm_dbg(&dev_priv->drm, + "Invalid PLL divider (%08x)\n", val); enabled = false; } } @@ -236,11 +238,11 @@ void bxt_dsi_pll_disable(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); - val = I915_READ(BXT_DSI_PLL_ENABLE); + val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); val &= ~BXT_DSI_PLL_DO_ENABLE; - I915_WRITE(BXT_DSI_PLL_ENABLE, val); + intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); /* * PLL lock should deassert within 200us. @@ -248,7 +250,8 @@ void bxt_dsi_pll_disable(struct intel_encoder *encoder) */ if (intel_de_wait_for_clear(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_LOCKED, 1)) - DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); + drm_err(&dev_priv->drm, + "Timeout waiting for PLL lock deassertion\n"); } u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, @@ -263,7 +266,7 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; int i; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); vlv_cck_get(dev_priv); pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); @@ -292,7 +295,7 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, p--; if (!p) { - DRM_ERROR("wrong P1 divisor\n"); + drm_err(&dev_priv->drm, "wrong P1 divisor\n"); return 0; } @@ -302,7 +305,7 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, } if (i == ARRAY_SIZE(lfsr_converts)) { - DRM_ERROR("wrong m_seed programmed\n"); + drm_err(&dev_priv->drm, "wrong m_seed programmed\n"); return 0; } @@ -325,7 +328,7 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); - config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); + config->dsi_pll.ctrl = intel_de_read(dev_priv, BXT_DSI_PLL_CTL); dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; @@ -333,7 +336,7 @@ u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); - DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); + drm_dbg(&dev_priv->drm, "Calculated pclk=%u\n", pclk); return pclk; } @@ -343,11 +346,10 @@ void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); - temp = I915_READ(MIPI_CTRL(port)); + temp = intel_de_read(dev_priv, MIPI_CTRL(port)); temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; - I915_WRITE(MIPI_CTRL(port), temp | - intel_dsi->escape_clk_div << - ESCAPE_CLOCK_DIVIDER_SHIFT); + intel_de_write(dev_priv, MIPI_CTRL(port), + temp | intel_dsi->escape_clk_div << ESCAPE_CLOCK_DIVIDER_SHIFT); } static void glk_dsi_program_esc_clock(struct drm_device *dev, @@ -393,8 +395,10 @@ static void glk_dsi_program_esc_clock(struct drm_device *dev, else txesc2_div = 10; - I915_WRITE(MIPIO_TXESC_CLK_DIV1, (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); - I915_WRITE(MIPIO_TXESC_CLK_DIV2, (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); + intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, + (1 << (txesc1_div - 1)) & GLK_TX_ESC_CLK_DIV1_MASK); + intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, + (1 << (txesc2_div - 1)) & GLK_TX_ESC_CLK_DIV2_MASK); } /* Program BXT Mipi clocks and dividers */ @@ -412,7 +416,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, u32 mipi_8by3_divider; /* Clear old configurations */ - tmp = I915_READ(BXT_MIPI_CLOCK_CTL); + tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); @@ -448,7 +452,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port, tmp |= BXT_MIPI_RX_ESCLK_LOWER_DIVIDER(port, rx_div_lower); tmp |= BXT_MIPI_RX_ESCLK_UPPER_DIVIDER(port, rx_div_upper); - I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); + intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); } int bxt_dsi_pll_compute(struct intel_encoder *encoder, @@ -478,10 +482,11 @@ int bxt_dsi_pll_compute(struct intel_encoder *encoder, } if (dsi_ratio < dsi_ratio_min || dsi_ratio > dsi_ratio_max) { - DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); + drm_err(&dev_priv->drm, + "Cant get a suitable ratio from DSI PLL ratios\n"); return -ECHRNG; } else - DRM_DEBUG_KMS("DSI PLL calculation is Done!!\n"); + drm_dbg_kms(&dev_priv->drm, "DSI PLL calculation is Done!!\n"); /* * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x @@ -507,11 +512,11 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder, enum port port; u32 val; - DRM_DEBUG_KMS("\n"); + drm_dbg_kms(&dev_priv->drm, "\n"); /* Configure PLL vales */ - I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); - POSTING_READ(BXT_DSI_PLL_CTL); + intel_de_write(dev_priv, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); + intel_de_posting_read(dev_priv, BXT_DSI_PLL_CTL); /* Program TX, RX, Dphy clocks */ if (IS_BROXTON(dev_priv)) { @@ -522,18 +527,19 @@ void bxt_dsi_pll_enable(struct intel_encoder *encoder, } /* Enable DSI PLL */ - val = I915_READ(BXT_DSI_PLL_ENABLE); + val = intel_de_read(dev_priv, BXT_DSI_PLL_ENABLE); val |= BXT_DSI_PLL_DO_ENABLE; - I915_WRITE(BXT_DSI_PLL_ENABLE, val); + intel_de_write(dev_priv, BXT_DSI_PLL_ENABLE, val); /* Timeout and fail if PLL not locked */ if (intel_de_wait_for_set(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_LOCKED, 1)) { - DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); + drm_err(&dev_priv->drm, + "Timed out waiting for DSI PLL to lock\n"); return; } - DRM_DEBUG_KMS("DSI PLL locked\n"); + drm_dbg_kms(&dev_priv->drm, "DSI PLL locked\n"); } void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) @@ -544,20 +550,20 @@ void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) /* Clear old configurations */ if (IS_BROXTON(dev_priv)) { - tmp = I915_READ(BXT_MIPI_CLOCK_CTL); + tmp = intel_de_read(dev_priv, BXT_MIPI_CLOCK_CTL); tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); tmp &= ~(BXT_MIPI_RX_ESCLK_UPPER_FIXDIV_MASK(port)); tmp &= ~(BXT_MIPI_8X_BY3_DIVIDER_MASK(port)); tmp &= ~(BXT_MIPI_RX_ESCLK_LOWER_FIXDIV_MASK(port)); - I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); + intel_de_write(dev_priv, BXT_MIPI_CLOCK_CTL, tmp); } else { - tmp = I915_READ(MIPIO_TXESC_CLK_DIV1); + tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV1); tmp &= ~GLK_TX_ESC_CLK_DIV1_MASK; - I915_WRITE(MIPIO_TXESC_CLK_DIV1, tmp); + intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV1, tmp); - tmp = I915_READ(MIPIO_TXESC_CLK_DIV2); + tmp = intel_de_read(dev_priv, MIPIO_TXESC_CLK_DIV2); tmp &= ~GLK_TX_ESC_CLK_DIV2_MASK; - I915_WRITE(MIPIO_TXESC_CLK_DIV2, tmp); + intel_de_write(dev_priv, MIPIO_TXESC_CLK_DIV2, tmp); } - I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); + intel_de_write(dev_priv, MIPI_EOT_DISABLE(port), CLOCKSTOP); } |