diff options
author | Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> | 2020-07-08 03:39:50 +0300 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-07-08 23:13:09 +0300 |
commit | 0b6613c6b91ec5f437495c438ca047af4e47b423 (patch) | |
tree | 9a6f74c48de4cc95ef881fbb16d2b98b16997ae9 /drivers/gpu/drm/i915/gt | |
parent | 9b413f011c2c62f4d7e1a02ac8add4899a4bc79b (diff) | |
download | linux-0b6613c6b91ec5f437495c438ca047af4e47b423.tar.xz |
drm/i915/sseu: Move sseu_info under gt_info
SSEUs are a GT capability, so track them under gt_info.
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200708003952.21831-8-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt')
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_context_sseu.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_gt_types.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_lrc.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_rps.c | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu.c | 19 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_sseu.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 |
10 files changed, 27 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_context_sseu.c b/drivers/gpu/drm/i915/gt/intel_context_sseu.c index 27ae48049239..b9c8163978a3 100644 --- a/drivers/gpu/drm/i915/gt/intel_context_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_context_sseu.c @@ -30,7 +30,7 @@ static int gen8_emit_rpcs_config(struct i915_request *rq, *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = lower_32_bits(offset); *cs++ = upper_32_bits(offset); - *cs++ = intel_sseu_make_rpcs(rq->engine->i915, &sseu); + *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); intel_ring_advance(rq, cs); diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index fca3c2348e5e..dd1a42c4d344 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -709,7 +709,7 @@ static int engine_setup_common(struct intel_engine_cs *engine) /* Use the whole device by default */ engine->sseu = - intel_sseu_from_device_info(&RUNTIME_INFO(engine->i915)->sseu); + intel_sseu_from_device_info(&engine->gt->info.sseu); intel_engine_init_workarounds(engine); intel_engine_init_whitelist(engine); @@ -1075,7 +1075,7 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine, struct intel_instdone *instdone) { struct drm_i915_private *i915 = engine->i915; - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + const struct sseu_dev_info *sseu = &engine->gt->info.sseu; struct intel_uncore *uncore = engine->uncore; u32 mmio_base = engine->mmio_base; int slice; diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 2c20fe693714..e0755f1a904b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -655,4 +655,6 @@ void intel_gt_info_print(const struct intel_gt_info *info, struct drm_printer *p) { drm_printf(p, "available engines: %x\n", info->engine_mask); + + intel_sseu_dump(&info->sseu, p); } diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index bb7551867c00..6d39a4a11bf3 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -116,6 +116,9 @@ struct intel_gt { /* Media engine access to SFC per instance */ u8 vdbox_sfc_access; + + /* Slice/subslice/EU info */ + struct sseu_dev_info sseu; } info; }; diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index e866b8d721ed..9e28b2f9df72 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -3422,7 +3422,7 @@ __execlists_update_reg_state(const struct intel_context *ce, /* RPCS */ if (engine->class == RENDER_CLASS) { regs[CTX_R_PWR_CLK_STATE] = - intel_sseu_make_rpcs(engine->i915, &ce->sseu); + intel_sseu_make_rpcs(engine->gt, &ce->sseu); i915_oa_init_reg_state(ce, engine); } diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 296391deeb94..97ba14ad52e4 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1062,11 +1062,12 @@ static bool gen6_rps_enable(struct intel_rps *rps) static int chv_rps_max_freq(struct intel_rps *rps) { struct drm_i915_private *i915 = rps_to_i915(rps); + struct intel_gt *gt = rps_to_gt(rps); u32 val; val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); - switch (RUNTIME_INFO(i915)->sseu.eu_total) { + switch (gt->info.sseu.eu_total) { case 8: /* (2 * 4) config */ val >>= FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT; diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 14c15cca3371..f1c039e1b5ad 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -128,7 +128,7 @@ static void gen11_compute_sseu_info(struct sseu_dev_info *sseu, static void gen12_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; u32 dss_en; u16 eu_en = 0; @@ -163,7 +163,7 @@ static void gen12_sseu_info_init(struct intel_gt *gt) static void gen11_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; u32 ss_en; u8 eu_en; @@ -192,7 +192,7 @@ static void gen11_sseu_info_init(struct intel_gt *gt) static void gen10_sseu_info_init(struct intel_gt *gt) { struct intel_uncore *uncore = gt->uncore; - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; const u32 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); const int eu_mask = 0xff; u32 subslice_mask, eu_en; @@ -268,7 +268,7 @@ static void gen10_sseu_info_init(struct intel_gt *gt) static void cherryview_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; u32 fuse; u8 subslice_mask = 0; @@ -325,7 +325,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; struct intel_device_info *info = mkwrite_device_info(i915); - struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; u32 fuse2, eu_disable, subslice_mask; const u8 eu_mask = 0xff; @@ -430,7 +430,7 @@ static void gen9_sseu_info_init(struct intel_gt *gt) static void bdw_sseu_info_init(struct intel_gt *gt) { - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; struct intel_uncore *uncore = gt->uncore; int s, ss; u32 fuse2, subslice_mask, eu_disable[3]; /* s_max */ @@ -516,7 +516,7 @@ static void bdw_sseu_info_init(struct intel_gt *gt) static void hsw_sseu_info_init(struct intel_gt *gt) { struct drm_i915_private *i915 = gt->i915; - struct sseu_dev_info *sseu = &RUNTIME_INFO(gt->i915)->sseu; + struct sseu_dev_info *sseu = >->info.sseu; u32 fuse1; u8 subslice_mask = 0; int s, ss; @@ -601,10 +601,11 @@ void intel_sseu_info_init(struct intel_gt *gt) gen12_sseu_info_init(gt); } -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, +u32 intel_sseu_make_rpcs(struct intel_gt *gt, const struct intel_sseu *req_sseu) { - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + struct drm_i915_private *i915 = gt->i915; + const struct sseu_dev_info *sseu = >->info.sseu; bool subslice_pg = sseu->has_subslice_pg; u8 slices, subslices; u32 rpcs = 0; diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.h b/drivers/gpu/drm/i915/gt/intel_sseu.h index f9c007f001e7..23ba6c2ebe70 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.h +++ b/drivers/gpu/drm/i915/gt/intel_sseu.h @@ -98,7 +98,7 @@ void intel_sseu_set_subslices(struct sseu_dev_info *sseu, int slice, void intel_sseu_info_init(struct intel_gt *gt); -u32 intel_sseu_make_rpcs(struct drm_i915_private *i915, +u32 intel_sseu_make_rpcs(struct intel_gt *gt, const struct intel_sseu *req_sseu); void intel_sseu_dump(const struct sseu_dev_info *sseu, struct drm_printer *p); diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 2da366821dda..dbafd923e5a1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -404,7 +404,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine, static void skl_tune_iz_hashing(struct intel_engine_cs *engine, struct i915_wa_list *wal) { - struct drm_i915_private *i915 = engine->i915; + struct intel_gt *gt = engine->gt; u8 vals[3] = { 0, 0, 0 }; unsigned int i; @@ -415,7 +415,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine, * Only consider slices where one, and only one, subslice has 7 * EUs */ - if (!is_power_of_2(RUNTIME_INFO(i915)->sseu.subslice_7eu[i])) + if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) continue; /* @@ -424,7 +424,7 @@ static void skl_tune_iz_hashing(struct intel_engine_cs *engine, * * -> 0 <= ss <= 3; */ - ss = ffs(RUNTIME_INFO(i915)->sseu.subslice_7eu[i]) - 1; + ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; vals[i] = 3 - ss; } @@ -1036,7 +1036,7 @@ cfl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) static void wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) { - const struct sseu_dev_info *sseu = &RUNTIME_INFO(i915)->sseu; + const struct sseu_dev_info *sseu = &i915->gt.info.sseu; unsigned int slice, subslice; u32 l3_en, mcr, mcr_mask; diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index c10ae1660e53..d44061033f23 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -68,7 +68,6 @@ struct __guc_ads_blob { static void __guc_ads_init(struct intel_guc *guc) { struct intel_gt *gt = guc_to_gt(guc); - struct drm_i915_private *dev_priv = gt->i915; struct __guc_ads_blob *blob = guc->ads_blob; const u32 skipped_size = LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE; u32 base; @@ -100,7 +99,7 @@ static void __guc_ads_init(struct intel_guc *guc) } /* System info */ - blob->system_info.slice_enabled = hweight8(RUNTIME_INFO(dev_priv)->sseu.slice_mask); + blob->system_info.slice_enabled = hweight8(gt->info.sseu.slice_mask); blob->system_info.rcs_enabled = 1; blob->system_info.bcs_enabled = 1; |