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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-11-11 17:09:36 +0300 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2020-11-11 18:07:10 +0300 |
| commit | 695dc55b573985569259e18f8e6261a77924342b (patch) | |
| tree | d327f96dfbbe97de93c0a541b9b7937257d12123 /drivers/gpu/drm/i915/i915_debugfs.c | |
| parent | 330b7d33056bb0fa7d7f672d4a98495f200fe9d4 (diff) | |
| download | linux-695dc55b573985569259e18f8e6261a77924342b.tar.xz | |
drm/i915/tgl: Fix Media power gate sequence.
Some media power gates are disabled by default. commit 5d86923060fc
("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
tried to enable it, but it duplicated an existent register.
So, the main PG setup sequences ended up overwriting it.
So, let's now merge this to the main PG setup sequence.
v2: (Chris): s/BIT/REG_BIT, remove useless comment,
remove useless =0, use the right gt,
remove rc6 sequence doubt from commit message.
Fixes: 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: stable@vger.kernel.org#v5.5+
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20201111072859.1186070-1-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_debugfs.c')
0 files changed, 0 insertions, 0 deletions