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author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-21 19:10:09 +0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-09-21 19:10:09 +0400 |
commit | 44040f107e64d689ccd3211ac62c6bc44f3f0775 (patch) | |
tree | f85059028aa570e758c7fb272fd8cf823ab4f119 /drivers/gpu/drm/i915/i915_gem_tiling.c | |
parent | 388dba30471c236a290c4082bce5f2b5cd1a7a06 (diff) | |
parent | 28d520433b6375740990ab99d69b0d0067fd656b (diff) | |
download | linux-44040f107e64d689ccd3211ac62c6bc44f3f0775.tar.xz |
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (133 commits)
drm/vgaarb: add VGA arbitration support to the drm and kms.
drm/radeon: some r420s have a CP race with the DMA engine.
drm/radeon/r600/kms: rv670 is not DCE3
drm/radeon/kms: r420 idle after programming GA_ENHANCE
drm/radeon/kms: more fixes to rv770 suspend/resume path.
drm/radeon/kms: more alignment for rv770.c with r600.c
drm/radeon/kms: rv770 blit init called too late.
drm/radeon/kms: move around new init path code to avoid posting at init
drm/radeon/r600: fix some issues with suspend/resume.
drm/radeon/kms: disable VGA rendering engine before taking over VRAM
drm/radeon/kms: Move radeon_get_clock_info() call out of radeon_clocks_init().
drm/radeon/kms: add initial connector properties
drm/radeon/kms: Use surfaces for scanout / cursor byte swapping on big endian.
drm/radeon/kms: don't fail if we fail to init GPU acceleration
drm/r600/kms: fixup number of loops per blit calculation.
drm/radeon/kms: reprogram format in set base.
drm/radeon: avivo chips have no separate int bit for display
drm/radeon/r600: don't do interrupts
drm: fix _DRM_GEM addmap error message
drm: update crtc x/y when only fb changes
...
Fixed up trivial conflicts in firmware/Makefile due to network driver
(cxgb3) and drm (mga/r128/radeon) firmware being listed next to each
other.
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 80 |
1 files changed, 27 insertions, 53 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index a2d527b22ec4..200e398453ca 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -94,23 +94,15 @@ static int intel_alloc_mchbar_resource(struct drm_device *dev) { - struct pci_dev *bridge_dev; drm_i915_private_t *dev_priv = dev->dev_private; int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp_lo, temp_hi = 0; u64 mchbar_addr; int ret = 0; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - ret = -ENODEV; - goto out; - } - if (IS_I965G(dev)) - pci_read_config_dword(bridge_dev, reg + 4, &temp_hi); - pci_read_config_dword(bridge_dev, reg, &temp_lo); + pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); + pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); mchbar_addr = ((u64)temp_hi << 32) | temp_lo; /* If ACPI doesn't have it, assume we need to allocate it ourselves */ @@ -118,30 +110,28 @@ intel_alloc_mchbar_resource(struct drm_device *dev) if (mchbar_addr && pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) { ret = 0; - goto out_put; + goto out; } #endif /* Get some space for it */ - ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res, + ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res, MCHBAR_SIZE, MCHBAR_SIZE, PCIBIOS_MIN_MEM, 0, pcibios_align_resource, - bridge_dev); + dev_priv->bridge_dev); if (ret) { DRM_DEBUG("failed bus alloc: %d\n", ret); dev_priv->mch_res.start = 0; - goto out_put; + goto out; } if (IS_I965G(dev)) - pci_write_config_dword(bridge_dev, reg + 4, + pci_write_config_dword(dev_priv->bridge_dev, reg + 4, upper_32_bits(dev_priv->mch_res.start)); - pci_write_config_dword(bridge_dev, reg, + pci_write_config_dword(dev_priv->bridge_dev, reg, lower_32_bits(dev_priv->mch_res.start)); -out_put: - pci_dev_put(bridge_dev); out: return ret; } @@ -150,44 +140,36 @@ out: static bool intel_setup_mchbar(struct drm_device *dev) { - struct pci_dev *bridge_dev; + drm_i915_private_t *dev_priv = dev->dev_private; int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp; bool need_disable = false, enabled; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - goto out; - } - if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); enabled = !!(temp & DEVEN_MCHBAR_EN); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); enabled = temp & 1; } /* If it's already enabled, don't have to do anything */ if (enabled) - goto out_put; + goto out; if (intel_alloc_mchbar_resource(dev)) - goto out_put; + goto out; need_disable = true; /* Space is allocated or reserved, so enable it. */ if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_write_config_dword(bridge_dev, DEVEN_REG, + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp | DEVEN_MCHBAR_EN); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); - pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); } -out_put: - pci_dev_put(bridge_dev); out: return need_disable; } @@ -196,25 +178,18 @@ static void intel_teardown_mchbar(struct drm_device *dev, bool disable) { drm_i915_private_t *dev_priv = dev->dev_private; - struct pci_dev *bridge_dev; int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; u32 temp; - bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); - if (!bridge_dev) { - DRM_DEBUG("no bridge dev?!\n"); - return; - } - if (disable) { if (IS_I915G(dev) || IS_I915GM(dev)) { - pci_read_config_dword(bridge_dev, DEVEN_REG, &temp); + pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp); temp &= ~DEVEN_MCHBAR_EN; - pci_write_config_dword(bridge_dev, DEVEN_REG, temp); + pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp); } else { - pci_read_config_dword(bridge_dev, mchbar_reg, &temp); + pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); temp &= ~1; - pci_write_config_dword(bridge_dev, mchbar_reg, temp); + pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp); } } @@ -234,7 +209,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; bool need_disable; - if (!IS_I9XX(dev)) { + if (IS_IGDNG(dev)) { + /* On IGDNG whatever DRAM config, GPU always do + * same swizzling setup. + */ + swizzle_x = I915_BIT_6_SWIZZLE_9_10; + swizzle_y = I915_BIT_6_SWIZZLE_9; + } else if (!IS_I9XX(dev)) { /* As far as we know, the 865 doesn't have these bit 6 * swizzling issues. */ @@ -317,13 +298,6 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) } } - /* FIXME: check with memory config on IGDNG */ - if (IS_IGDNG(dev)) { - DRM_ERROR("disable tiling on IGDNG...\n"); - swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; - swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - } - dev_priv->mm.bit_6_swizzle_x = swizzle_x; dev_priv->mm.bit_6_swizzle_y = swizzle_y; } |