diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-11-11 21:34:13 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-11-16 17:00:34 +0300 |
| commit | da00bdcfb25989afc025274fecbdcbfd9a24d3a1 (patch) | |
| tree | 738604f55efd34572846786847fd1032f5ac57a4 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 750a951fd34808d8822abafccd0dfa479deef0a0 (diff) | |
| download | linux-da00bdcfb25989afc025274fecbdcbfd9a24d3a1.tar.xz | |
drm/i915: Remove the magic AUX_CTL is at DP + foo tricks
Currently we determine the location of the AUX registers in a confusing
way. First we assume the PCH registers are used always, but then we
override it for everything but HSW/BDW to use DP+0x10. Very confusing.
Let's just make it straightforward and simply add a few functions to
pick the right AUX_CTL based on the DP port.
To deal with VLV/CHV we'll include the display_mmio_offset into the
AUX register defines.
v2: Reorder patches (Chris)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1447266856-30249-5-git-send-email-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 54 |
1 files changed, 27 insertions, 27 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 81dd27a601f9..85d8878d043b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4228,33 +4228,33 @@ enum skl_disp_power_wells { * is 20 bytes in each direction, hence the 5 fixed * data registers */ -#define _DPA_AUX_CH_CTL 0x64010 -#define _DPA_AUX_CH_DATA1 0x64014 -#define _DPA_AUX_CH_DATA2 0x64018 -#define _DPA_AUX_CH_DATA3 0x6401c -#define _DPA_AUX_CH_DATA4 0x64020 -#define _DPA_AUX_CH_DATA5 0x64024 - -#define _DPB_AUX_CH_CTL 0x64110 -#define _DPB_AUX_CH_DATA1 0x64114 -#define _DPB_AUX_CH_DATA2 0x64118 -#define _DPB_AUX_CH_DATA3 0x6411c -#define _DPB_AUX_CH_DATA4 0x64120 -#define _DPB_AUX_CH_DATA5 0x64124 - -#define _DPC_AUX_CH_CTL 0x64210 -#define _DPC_AUX_CH_DATA1 0x64214 -#define _DPC_AUX_CH_DATA2 0x64218 -#define _DPC_AUX_CH_DATA3 0x6421c -#define _DPC_AUX_CH_DATA4 0x64220 -#define _DPC_AUX_CH_DATA5 0x64224 - -#define _DPD_AUX_CH_CTL 0x64310 -#define _DPD_AUX_CH_DATA1 0x64314 -#define _DPD_AUX_CH_DATA2 0x64318 -#define _DPD_AUX_CH_DATA3 0x6431c -#define _DPD_AUX_CH_DATA4 0x64320 -#define _DPD_AUX_CH_DATA5 0x64324 +#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64010) +#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014) +#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018) +#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c) +#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020) +#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024) + +#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64110) +#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114) +#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118) +#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c) +#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120) +#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124) + +#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64210) +#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214) +#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218) +#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c) +#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220) +#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224) + +#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset + 0x64310) +#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314) +#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318) +#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c) +#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320) +#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324) #define DP_AUX_CH_CTL(port) _PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL) #define DP_AUX_CH_DATA(port, i) (_PORT(port, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ |