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| author | Uma Shankar <uma.shankar@intel.com> | 2019-03-29 17:29:16 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-03-29 21:28:35 +0300 |
| commit | 502da13a72dad49690f5ac1c4d1a182ab7810eaa (patch) | |
| tree | a59d26eeebd62b84cebb3fe44d24235389d80ba1 /drivers/gpu/drm/i915/intel_color.c | |
| parent | 61eae851c92b0b5b089a3f5da92219500dc99d59 (diff) | |
| download | linux-502da13a72dad49690f5ac1c4d1a182ab7810eaa.tar.xz | |
drm/i915: Program EXT2 GC MAX registers
EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.
v2: Updated the 1.0 programming and aligned as per GLK, also added
GLK along with GEN10+ check, as per Ville's feedback.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1553869756-4546-3-git-send-email-uma.shankar@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_color.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_color.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index c7761591ba7c..f2907cfd116a 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -526,6 +526,17 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16)); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16)); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16)); + + /* + * Program the gc max 2 register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 3.0 to 7.0 + */ + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16)); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16)); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16)); + } } else { for (i = 0; i < lut_size; i++) { u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1); @@ -537,6 +548,17 @@ static void bdw_load_gamma_lut(const struct intel_crtc_state *crtc_state, u32 of I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 0), (1 << 16)); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 1), (1 << 16)); I915_WRITE(PREC_PAL_EXT_GC_MAX(pipe, 2), (1 << 16)); + + /* + * Program the gc max 2 register to clamp values > 1.0. + * ToDo: Extend the ABI to be able to program values + * from 3.0 to 7.0 + */ + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 0), (1 << 16)); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 1), (1 << 16)); + I915_WRITE(PREC_PAL_EXT2_GC_MAX(pipe, 2), (1 << 16)); + } } /* |