summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_dpll_mgr.c
diff options
context:
space:
mode:
authorVille Syrjälä <ville.syrjala@linux.intel.com>2016-05-13 23:41:22 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2016-05-23 21:11:11 +0300
commit14d41b3b0e2ffbed309e68c87031986016d7bcac (patch)
treeb1036bc7aca1a5f0dfd2aa419a199733d4b1ce61 /drivers/gpu/drm/i915/intel_dpll_mgr.c
parentc89e39f32763bbaeba0b66606bda7893a25489ac (diff)
downloadlinux-14d41b3b0e2ffbed309e68c87031986016d7bcac.tar.xz
drm/i915: Move the SKL DPLL0 VCO computation into intel_dp_compute_config()
Shared plls won't get assigned until the .compute_clocks() hook gets called, which happens from the crtc .atomic_check hook. That's too late as the cdclk computation has already happened. So let's move the DPLL0 VCO computation into intel_dp_compute_config() so that it's done when the cdclk computation happens. Also only do it for eDP since we only pick DPLL0 for eDP. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-4-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpll_mgr.c')
-rw-r--r--drivers/gpu/drm/i915/intel_dpll_mgr.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index e99e306e8743..43ba60b3662e 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1194,7 +1194,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
struct intel_shared_dpll *pll;
uint32_t ctrl1, cfgcr1, cfgcr2;
int clock = crtc_state->port_clock;
- uint32_t vco = 8100;
/*
* See comment in intel_dpll_hw_state to understand why we always use 0
@@ -1239,15 +1238,12 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
break;
case 108000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
- vco = 8640;
break;
case 216000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
- vco = 8640;
break;
}
- to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
cfgcr1 = cfgcr2 = 0;
} else {
return NULL;