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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2018-12-13 00:17:38 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2020-10-29 18:32:20 +0300 |
| commit | 96eaeb3dfa40576a7aa195303c538202311cffbc (patch) | |
| tree | 726d74d01730d614f64014fd1e49a9531036a118 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | bd0cef2a797ac59a103c887b7864b6cf7bd5b512 (diff) | |
| download | linux-96eaeb3dfa40576a7aa195303c538202311cffbc.tar.xz | |
drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registers
Remove the hand rolled array of WM0_PIPE register offsets
and use the standard _MMIO_PIPE3() instead.
v2: Take care of gvt too
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181212211738.27770-1-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0ef01a01ef8d..f54375b11964 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3573,11 +3573,11 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, _ilk_disable_lp_wm(dev_priv, dirty); if (dirty & WM_DIRTY_PIPE(PIPE_A)) - I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); + I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]); if (dirty & WM_DIRTY_PIPE(PIPE_B)) - I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); + I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]); if (dirty & WM_DIRTY_PIPE(PIPE_C)) - I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); + I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]); if (dirty & WM_DIRTY_DDB) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -6287,13 +6287,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal; enum pipe pipe = crtc->pipe; - static const i915_reg_t wm0_pipe_reg[] = { - [PIPE_A] = WM0_PIPEA_ILK, - [PIPE_B] = WM0_PIPEB_ILK, - [PIPE_C] = WM0_PIPEC_IVB, - }; - hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); + hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe)); memset(active, 0, sizeof(*active)); |