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authorStanislav Lisovskiy <stanislav.lisovskiy@intel.com>2020-04-15 17:39:04 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2020-04-17 20:41:00 +0300
commit680e1af713d92940e39a313a8592b13a6885a14c (patch)
treed15911e3f9e985df91653213d09251124c54dce2 /drivers/gpu/drm/i915/intel_pm.h
parenta389c49fac556cba82edee7a5724269ec2d28981 (diff)
downloadlinux-680e1af713d92940e39a313a8592b13a6885a14c.tar.xz
drm/i915: Add pre/post plane updates for SAGV
Lets have a unified way to handle SAGV changes, espoecially considering the upcoming Gen12 changes. Current "standard" way of doing this in commit_tail is pre/post plane updates, when everything which has to be forbidden and not supported in new config has to be restricted before update and relaxed after plane update. v2: - Removed unneeded returns(Ville) Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200415143911.10244-5-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.h')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index d60a85421c5a..9a6036ab0f90 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
bool intel_can_enable_sagv(struct intel_atomic_state *state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool skl_wm_level_equals(const struct skl_wm_level *l1,
const struct skl_wm_level *l2);
bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,