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authorRodrigo Vivi <rodrigo.vivi@intel.com>2015-12-12 03:31:31 +0300
committerRodrigo Vivi <rodrigo.vivi@intel.com>2015-12-12 03:32:56 +0300
commit7370c68d5b9a2e853600290e797a4a79fefaf1e7 (patch)
treee2661902161f92c64b5a8a85cb307b9ee87ad8ae /drivers/gpu/drm/i915/intel_psr.c
parent618100f8a84b8a97f7c1a0e03acf0d466102f40f (diff)
downloadlinux-7370c68d5b9a2e853600290e797a4a79fefaf1e7.tar.xz
drm/i915: PSR also doesn't have link_entry_time on SKL.
This bit is also reserved on Skylake. Actually the only platform that supports this is Haswell, so let's fix this logic and apply this link entry time only for the platform that supports it, i.e. Haswell. This also changes the style to let more clear platform differences outside the reg write. We would probably catch this case sooner if separated, or not... Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1449880291-21388-1-git-send-email-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
-rw-r--r--drivers/gpu/drm/i915/intel_psr.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 14cc2cfe5893..9ccff3011523 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -276,10 +276,11 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
*/
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val = 0x0;
- const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
+
+ if (IS_HASWELL(dev))
+ val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
I915_WRITE(EDP_PSR_CTL, val |
- (IS_BROADWELL(dev) ? 0 : link_entry_time) |
max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
EDP_PSR_ENABLE);