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authorImre Deak <imre.deak@intel.com>2016-04-15 22:32:58 +0300
committerImre Deak <imre.deak@intel.com>2016-04-18 20:16:36 +0300
commit5f304c87363401eb85cae304d025e93267353d3a (patch)
tree36fb95f7ca7e304b0d04f24dd20d218b012eac2c /drivers/gpu/drm/i915/intel_runtime_pm.c
parent8a8dae260f5df805fe062875fef272ffccaf727f (diff)
downloadlinux-5f304c87363401eb85cae304d025e93267353d3a.tar.xz
drm/i915/kbl: Reset secondary power well requests left on by DMC/KVMR
The workaround added in commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well requests left on by DMC/KVMR") needs to be applied on Kabylake too as shown by the corresponding timeout errors about power well 1 and MISC IO power well disabling in the latest CI run. CC: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1460748778-4484-1-git-send-email-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 259f66f94854..1242fb5d3301 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -709,7 +709,7 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
}
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
+ if (IS_GEN9(dev_priv))
gen9_sanitize_power_well_requests(dev_priv, power_well);
}