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authorWangyan Wang <wangyan.wang@mediatek.com>2019-04-09 09:53:06 +0300
committerCK Hu <ck.hu@mediatek.com>2019-04-09 12:46:54 +0300
commit321b628e6f5a3af999f75eadd373adbcb8b4cb1f (patch)
treef08e6986ea2112b2e98150e66d6d9465d288e315 /drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
parent0c24613cda163dedfa229afc8eff6072e57fac8d (diff)
downloadlinux-321b628e6f5a3af999f75eadd373adbcb8b4cb1f.tar.xz
drm/mediatek: make implementation of recalc_rate() for MT2701 hdmi phy
Recalculate the rate of this clock, by querying hardware to make implementation of recalc_rate() to match the definition. Signed-off-by: Wangyan Wang <wangyan.wang@mediatek.com> Signed-off-by: CK Hu <ck.hu@mediatek.com>
Diffstat (limited to 'drivers/gpu/drm/mediatek/mtk_hdmi_phy.h')
-rw-r--r--drivers/gpu/drm/mediatek/mtk_hdmi_phy.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
index f39b1fc66612..71430691ffe4 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
@@ -50,8 +50,6 @@ void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate);
-unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate);
extern struct platform_driver mtk_hdmi_phy_driver;
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;