diff options
| author | Rob Clark <robdclark@chromium.org> | 2024-01-17 23:37:18 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2024-02-26 18:29:54 +0300 |
| commit | 54615eda7972d2968c8dbed2196c25816fc0b116 (patch) | |
| tree | 48d8176fdb7c93a60bb4b1e37c7ea82e557e5a98 /drivers/gpu/drm/msm/adreno/a6xx.xml.h | |
| parent | a7165277ff68609a6c4a8b320f801e7af8368fe9 (diff) | |
| download | linux-54615eda7972d2968c8dbed2196c25816fc0b116.tar.xz | |
drm/msm/adreno: Update generated headers
This updates the GPU headers to latest from mesa, using gen_header.py
(which is used to generate headers at bulid time for mesa), rather than
headergen2 (which doesn't have proper support for A6XX vs A7XX register
variants).
Mostly just uninteresting churn, but there are a couple spots in a7xx
paths which update REG_A6XX_foo to REG_A7XX_foo for registers which are
a7xx specific.
Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/574880/
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a6xx.xml.h')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx.xml.h | 5257 |
1 files changed, 4425 insertions, 832 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..92e23bf2458d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -3,28 +3,20 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 243381 bytes, from Sat Feb 24 09:06:40 2024) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024) + +Copyright (C) 2013-2024 by the following authors: +- Rob Clark <robdclark@gmail.com> Rob Clark +- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum a6xx_tile_mode { TILE6_LINEAR = 0, @@ -246,6 +251,85 @@ enum a6xx_shader_id { A6XX_HLSQ_INST_RAM_1 = 115, }; +enum a7xx_statetype_id { + A7XX_TP0_NCTX_REG = 0, + A7XX_TP0_CTX0_3D_CVS_REG = 1, + A7XX_TP0_CTX0_3D_CPS_REG = 2, + A7XX_TP0_CTX1_3D_CVS_REG = 3, + A7XX_TP0_CTX1_3D_CPS_REG = 4, + A7XX_TP0_CTX2_3D_CPS_REG = 5, + A7XX_TP0_CTX3_3D_CPS_REG = 6, + A7XX_TP0_TMO_DATA = 9, + A7XX_TP0_SMO_DATA = 10, + A7XX_TP0_MIPMAP_BASE_DATA = 11, + A7XX_SP_NCTX_REG = 32, + A7XX_SP_CTX0_3D_CVS_REG = 33, + A7XX_SP_CTX0_3D_CPS_REG = 34, + A7XX_SP_CTX1_3D_CVS_REG = 35, + A7XX_SP_CTX1_3D_CPS_REG = 36, + A7XX_SP_CTX2_3D_CPS_REG = 37, + A7XX_SP_CTX3_3D_CPS_REG = 38, + A7XX_SP_INST_DATA = 39, + A7XX_SP_INST_DATA_1 = 40, + A7XX_SP_LB_0_DATA = 41, + A7XX_SP_LB_1_DATA = 42, + A7XX_SP_LB_2_DATA = 43, + A7XX_SP_LB_3_DATA = 44, + A7XX_SP_LB_4_DATA = 45, + A7XX_SP_LB_5_DATA = 46, + A7XX_SP_LB_6_DATA = 47, + A7XX_SP_LB_7_DATA = 48, + A7XX_SP_CB_RAM = 49, + A7XX_SP_LB_13_DATA = 50, + A7XX_SP_LB_14_DATA = 51, + A7XX_SP_INST_TAG = 52, + A7XX_SP_INST_DATA_2 = 53, + A7XX_SP_TMO_TAG = 54, + A7XX_SP_SMO_TAG = 55, + A7XX_SP_STATE_DATA = 56, + A7XX_SP_HWAVE_RAM = 57, + A7XX_SP_L0_INST_BUF = 58, + A7XX_SP_LB_8_DATA = 59, + A7XX_SP_LB_9_DATA = 60, + A7XX_SP_LB_10_DATA = 61, + A7XX_SP_LB_11_DATA = 62, + A7XX_SP_LB_12_DATA = 63, + A7XX_HLSQ_DATAPATH_DSTR_META = 64, + A7XX_HLSQ_L2STC_TAG_RAM = 67, + A7XX_HLSQ_L2STC_INFO_CMD = 68, + A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69, + A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70, + A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71, + A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72, + A7XX_HLSQ_CHUNK_CVS_RAM = 73, + A7XX_HLSQ_CHUNK_CPS_RAM = 74, + A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, + A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, + A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, + A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, + A7XX_HLSQ_CVS_MISC_RAM = 79, + A7XX_HLSQ_CPS_MISC_RAM = 80, + A7XX_HLSQ_CPS_MISC_RAM_1 = 81, + A7XX_HLSQ_INST_RAM = 82, + A7XX_HLSQ_GFX_CVS_CONST_RAM = 83, + A7XX_HLSQ_GFX_CPS_CONST_RAM = 84, + A7XX_HLSQ_CVS_MISC_RAM_TAG = 85, + A7XX_HLSQ_CPS_MISC_RAM_TAG = 86, + A7XX_HLSQ_INST_RAM_TAG = 87, + A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, + A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, + A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90, + A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91, + A7XX_HLSQ_INST_RAM_1 = 92, + A7XX_HLSQ_STPROC_META = 93, + A7XX_HLSQ_BV_BE_META = 94, + A7XX_HLSQ_INST_RAM_2 = 95, + A7XX_HLSQ_DATAPATH_META = 96, + A7XX_HLSQ_FRONTEND_META = 97, + A7XX_HLSQ_INDIRECT_META = 98, + A7XX_HLSQ_BACKEND_META = 99, +}; + enum a6xx_debugbus_id { A6XX_DBGBUS_CP = 1, A6XX_DBGBUS_RBBM = 2, @@ -305,6 +389,140 @@ enum a6xx_debugbus_id { A6XX_DBGBUS_SPTP_5 = 93, }; +enum a7xx_state_location { + A7XX_HLSQ_STATE = 0, + A7XX_HLSQ_DP = 1, + A7XX_SP_TOP = 2, + A7XX_USPTP = 3, +}; + +enum a7xx_pipe { + A7XX_PIPE_NONE = 0, + A7XX_PIPE_BR = 1, + A7XX_PIPE_BV = 2, + A7XX_PIPE_LPAC = 3, +}; + +enum a7xx_cluster { + A7XX_CLUSTER_NONE = 0, + A7XX_CLUSTER_FE = 1, + A7XX_CLUSTER_SP_VS = 2, + A7XX_CLUSTER_PC_VS = 3, + A7XX_CLUSTER_GRAS = 4, + A7XX_CLUSTER_SP_PS = 5, + A7XX_CLUSTER_VPC_PS = 6, + A7XX_CLUSTER_PS = 7, +}; + +enum a7xx_debugbus_id { + A7XX_DBGBUS_CP_0_0 = 1, + A7XX_DBGBUS_CP_0_1 = 2, + A7XX_DBGBUS_RBBM = 3, + A7XX_DBGBUS_GBIF_GX = 5, + A7XX_DBGBUS_GBIF_CX = 6, + A7XX_DBGBUS_HLSQ = 7, + A7XX_DBGBUS_UCHE_0 = 9, + A7XX_DBGBUS_UCHE_1 = 10, + A7XX_DBGBUS_TESS_BR = 13, + A7XX_DBGBUS_TESS_BV = 14, + A7XX_DBGBUS_PC_BR = 17, + A7XX_DBGBUS_PC_BV = 18, + A7XX_DBGBUS_VFDP_BR = 21, + A7XX_DBGBUS_VFDP_BV = 22, + A7XX_DBGBUS_VPC_BR = 25, + A7XX_DBGBUS_VPC_BV = 26, + A7XX_DBGBUS_TSE_BR = 29, + A7XX_DBGBUS_TSE_BV = 30, + A7XX_DBGBUS_RAS_BR = 33, + A7XX_DBGBUS_RAS_BV = 34, + A7XX_DBGBUS_VSC = 37, + A7XX_DBGBUS_COM_0 = 39, + A7XX_DBGBUS_LRZ_BR = 43, + A7XX_DBGBUS_LRZ_BV = 44, + A7XX_DBGBUS_UFC_0 = 47, + A7XX_DBGBUS_UFC_1 = 48, + A7XX_DBGBUS_GMU_GX = 55, + A7XX_DBGBUS_DBGC = 59, + A7XX_DBGBUS_CX = 60, + A7XX_DBGBUS_GMU_CX = 61, + A7XX_DBGBUS_GPC_BR = 62, + A7XX_DBGBUS_GPC_BV = 63, + A7XX_DBGBUS_LARC = 66, + A7XX_DBGBUS_HLSQ_SPTP = 68, + A7XX_DBGBUS_RB_0 = 70, + A7XX_DBGBUS_RB_1 = 71, + A7XX_DBGBUS_RB_2 = 72, + A7XX_DBGBUS_RB_3 = 73, + A7XX_DBGBUS_RB_4 = 74, + A7XX_DBGBUS_RB_5 = 75, + A7XX_DBGBUS_UCHE_WRAPPER = 102, + A7XX_DBGBUS_CCU_0 = 106, + A7XX_DBGBUS_CCU_1 = 107, + A7XX_DBGBUS_CCU_2 = 108, + A7XX_DBGBUS_CCU_3 = 109, + A7XX_DBGBUS_CCU_4 = 110, + A7XX_DBGBUS_CCU_5 = 111, + A7XX_DBGBUS_VFD_BR_0 = 138, + A7XX_DBGBUS_VFD_BR_1 = 139, + A7XX_DBGBUS_VFD_BR_2 = 140, + A7XX_DBGBUS_VFD_BR_3 = 141, + A7XX_DBGBUS_VFD_BR_4 = 142, + A7XX_DBGBUS_VFD_BR_5 = 143, + A7XX_DBGBUS_VFD_BR_6 = 144, + A7XX_DBGBUS_VFD_BR_7 = 145, + A7XX_DBGBUS_VFD_BV_0 = 202, + A7XX_DBGBUS_VFD_BV_1 = 203, + A7XX_DBGBUS_VFD_BV_2 = 204, + A7XX_DBGBUS_VFD_BV_3 = 205, + A7XX_DBGBUS_USP_0 = 234, + A7XX_DBGBUS_USP_1 = 235, + A7XX_DBGBUS_USP_2 = 236, + A7XX_DBGBUS_USP_3 = 237, + A7XX_DBGBUS_USP_4 = 238, + A7XX_DBGBUS_USP_5 = 239, + A7XX_DBGBUS_TP_0 = 266, + A7XX_DBGBUS_TP_1 = 267, + A7XX_DBGBUS_TP_2 = 268, + A7XX_DBGBUS_TP_3 = 269, + A7XX_DBGBUS_TP_4 = 270, + A7XX_DBGBUS_TP_5 = 271, + A7XX_DBGBUS_TP_6 = 272, + A7XX_DBGBUS_TP_7 = 273, + A7XX_DBGBUS_TP_8 = 274, + A7XX_DBGBUS_TP_9 = 275, + A7XX_DBGBUS_TP_10 = 276, + A7XX_DBGBUS_TP_11 = 277, + A7XX_DBGBUS_USPTP_0 = 330, + A7XX_DBGBUS_USPTP_1 = 331, + A7XX_DBGBUS_USPTP_2 = 332, + A7XX_DBGBUS_USPTP_3 = 333, + A7XX_DBGBUS_USPTP_4 = 334, + A7XX_DBGBUS_USPTP_5 = 335, + A7XX_DBGBUS_USPTP_6 = 336, + A7XX_DBGBUS_USPTP_7 = 337, + A7XX_DBGBUS_USPTP_8 = 338, + A7XX_DBGBUS_USPTP_9 = 339, + A7XX_DBGBUS_USPTP_10 = 340, + A7XX_DBGBUS_USPTP_11 = 341, + A7XX_DBGBUS_CCHE_0 = 396, + A7XX_DBGBUS_CCHE_1 = 397, + A7XX_DBGBUS_CCHE_2 = 398, + A7XX_DBGBUS_VPC_DSTR_0 = 408, + A7XX_DBGBUS_VPC_DSTR_1 = 409, + A7XX_DBGBUS_VPC_DSTR_2 = 410, + A7XX_DBGBUS_HLSQ_DP_STR_0 = 411, + A7XX_DBGBUS_HLSQ_DP_STR_1 = 412, + A7XX_DBGBUS_HLSQ_DP_STR_2 = 413, + A7XX_DBGBUS_HLSQ_DP_STR_3 = 414, + A7XX_DBGBUS_HLSQ_DP_STR_4 = 415, + A7XX_DBGBUS_HLSQ_DP_STR_5 = 416, + A7XX_DBGBUS_UFC_DSTR_0 = 443, + A7XX_DBGBUS_UFC_DSTR_1 = 444, + A7XX_DBGBUS_UFC_DSTR_2 = 445, + A7XX_DBGBUS_CGC_SUBCORE = 446, + A7XX_DBGBUS_CGC_CORE = 447, +}; + enum a6xx_cp_perfcounter_select { PERF_CP_ALWAYS_COUNT = 0, PERF_CP_BUSY_GFX_CORE_IDLE = 1, @@ -914,6 +1132,19 @@ enum a6xx_ztest_mode { A6XX_INVALID_ZTEST = 3, }; +enum a6xx_tess_spacing { + TESS_EQUAL = 0, + TESS_FRACTIONAL_ODD = 2, + TESS_FRACTIONAL_EVEN = 3, +}; + +enum a6xx_tess_output { + TESS_POINTS = 0, + TESS_LINES = 1, + TESS_CW_TRIS = 2, + TESS_CCW_TRIS = 3, +}; + enum a6xx_sequenced_thread_dist { DIST_SCREEN_COORD = 0, DIST_ALL_TO_RB0 = 1, @@ -967,17 +1198,25 @@ enum a6xx_rotation { ROTATE_VFLIP = 5, }; -enum a6xx_tess_spacing { - TESS_EQUAL = 0, - TESS_FRACTIONAL_ODD = 2, - TESS_FRACTIONAL_EVEN = 3, +enum a6xx_ccu_cache_size { + CCU_CACHE_SIZE_FULL = 0, + CCU_CACHE_SIZE_HALF = 1, + CCU_CACHE_SIZE_QUARTER = 2, + CCU_CACHE_SIZE_EIGHTH = 3, }; -enum a6xx_tess_output { - TESS_POINTS = 0, - TESS_LINES = 1, - TESS_CW_TRIS = 2, - TESS_CCW_TRIS = 3, +enum a6xx_varying_interp_mode { + INTERP_SMOOTH = 0, + INTERP_FLAT = 1, + INTERP_ZERO = 2, + INTERP_ONE = 3, +}; + +enum a6xx_varying_ps_repl_mode { + PS_REPL_NONE = 0, + PS_REPL_S = 1, + PS_REPL_T = 2, + PS_REPL_ONE_MINUS_T = 3, }; enum a6xx_threadsize { @@ -991,9 +1230,17 @@ enum a6xx_bindless_descriptor_size { }; enum a6xx_isam_mode { + ISAMMODE_CL = 1, ISAMMODE_GL = 2, }; +enum a7xx_cs_yalign { + CS_YALIGN_1 = 8, + CS_YALIGN_2 = 4, + CS_YALIGN_4 = 2, + CS_YALIGN_8 = 1, +}; + enum a6xx_tex_filter { A6XX_TEX_NEAREST = 0, A6XX_TEX_LINEAR = 1, @@ -1069,6 +1316,7 @@ enum a6xx_tex_type { #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 + #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 @@ -1086,6 +1334,7 @@ enum a6xx_tex_type { #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000 + #define REG_A6XX_CP_RB_BASE 0x00000800 #define REG_A6XX_CP_RB_CNTL 0x00000802 @@ -1104,7 +1353,6 @@ enum a6xx_tex_type { #define REG_A6XX_CP_HW_FAULT 0x00000821 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 - #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 #define REG_A6XX_CP_STATUS_1 0x00000825 @@ -1128,25 +1376,29 @@ enum a6xx_tex_type { #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00 #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; } #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 @@ -1154,13 +1406,15 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; } #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 @@ -1176,11 +1430,11 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) #define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002 #define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001 -static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } +#define REG_A6XX_CP_SCRATCH(i0) (0x00000883 + 0x1*(i0)) static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } -static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } +#define REG_A6XX_CP_PROTECT(i0) (0x00000850 + 0x1*(i0)) static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff @@ -1209,9 +1463,9 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab -static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } +#define REG_A6XX_CP_PERFCTR_CP_SEL(i0) (0x000008d0 + 0x1*(i0)) -static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; } +#define REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0) (0x000008e0 + 0x1*(i0)) #define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900 @@ -1405,8 +1659,48 @@ static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 +#define REG_A7XX_CP_APERTURE_CNTL_HOST 0x00000a00 +#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK 0x00003000 +#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT 12 +static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK; +} +#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK 0x00000700 +#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT 8 +static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK; +} +#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK 0x00000030 +#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT 4 +static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(uint32_t val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK; +} + #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 +#define REG_A7XX_CP_APERTURE_CNTL_CD 0x00000a03 +#define A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK 0x00003000 +#define A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT 12 +static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK; +} +#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK 0x00000700 +#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT 8 +static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK; +} +#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK 0x00000030 +#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT 4 +static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CONTEXT(uint32_t val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK; +} + #define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61 #define REG_A7XX_CP_BV_HW_FAULT 0x00000a64 @@ -1472,7 +1766,6 @@ static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) #define REG_A6XX_RBBM_GPR0_CNTL 0x00000018 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 - #define REG_A6XX_RBBM_STATUS 0x00000210 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 @@ -1520,93 +1813,93 @@ static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288 -static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_CP(i0) (0x00000400 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_RBBM(i0) (0x0000041c + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_PC(i0) (0x00000424 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_VFD(i0) (0x00000434 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_HLSQ(i0) (0x00000444 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_VPC(i0) (0x00000450 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_CCU(i0) (0x0000045c + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_TSE(i0) (0x00000466 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_RAS(i0) (0x0000046e + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_UCHE(i0) (0x00000476 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_TP(i0) (0x0000048e + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_SP(i0) (0x000004a6 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_RB(i0) (0x000004d6 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_VSC(i0) (0x000004e6 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_LRZ(i0) (0x000004ea + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_CMP(i0) (0x000004f2 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_CP(i0) (0x00000300 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_RBBM(i0) (0x0000031c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_PC(i0) (0x00000324 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_VFD(i0) (0x00000334 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_HLSQ(i0) (0x00000344 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_VPC(i0) (0x00000350 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_CCU(i0) (0x0000035c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_TSE(i0) (0x00000366 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_RAS(i0) (0x0000036e + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_UCHE(i0) (0x00000376 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_TP(i0) (0x0000038e + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_SP(i0) (0x000003a6 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_RB(i0) (0x000003d6 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_VSC(i0) (0x000003e6 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_LRZ(i0) (0x000003ea + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_CMP(i0) (0x000003f2 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_UFC(i0) (0x000003fa + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_HLSQ(i0) (0x00000410 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_CP(i0) (0x0000041c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_SP(i0) (0x0000042a + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_TP(i0) (0x00000442 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_UFC(i0) (0x0000044e + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_PC(i0) (0x00000460 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_VFD(i0) (0x00000470 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_VPC(i0) (0x00000480 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_TSE(i0) (0x0000048c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_RAS(i0) (0x00000494 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0) (0x0000049c + 0x2*(i0)) #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 @@ -1622,7 +1915,7 @@ static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } +#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0) (0x00000507 + 0x1*(i0)) #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b @@ -1710,9 +2003,7 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 - #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 - #define REG_A7XX_RBBM_INT_2_MASK 0x0000003a #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 @@ -1725,6 +2016,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +2232,37 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 +#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 + +#define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123 + +#define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124 + +#define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125 + +#define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126 + +#define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127 + +#define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128 + +#define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129 + +#define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a + +#define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff @@ -2117,7 +2435,10 @@ static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 -static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } +#define REG_A6XX_VSC_PERFCTR_VSC_SEL(i0) (0x00000cd8 + 0x1*(i0)) + +#define REG_A7XX_VSC_UNKNOWN_0CD8 0x00000cd8 +#define A7XX_VSC_UNKNOWN_0CD8_BINNING 0x00000001 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 @@ -2149,7 +2470,7 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; } -static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } +#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0) (0x00000e1c + 0x1*(i0)) #define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a @@ -2291,13 +2612,15 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { - return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; } #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { - return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; } #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 @@ -2316,7 +2639,7 @@ static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; } -static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } +#define REG_A6XX_VSC_PIPE_CONFIG(i0) (0x00000c10 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff @@ -2356,18 +2679,22 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 -static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } +#define REG_A6XX_VSC_STATE(i0) (0x00000c38 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } -static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } +#define REG_A6XX_VSC_PRIM_STRM_SIZE(i0) (0x00000c58 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } -static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } +#define REG_A6XX_VSC_DRAW_STRM_SIZE(i0) (0x00000c78 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } +#define REG_A7XX_UCHE_UNKNOWN_0E10 0x00000e10 + +#define REG_A7XX_UCHE_UNKNOWN_0E11 0x00000e11 + #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 #define REG_A6XX_GRAS_CL_CNTL 0x00008000 @@ -2437,6 +2764,8 @@ static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) { return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; } +#define A6XX_GRAS_CNTL_UNK10 0x00000400 +#define A6XX_GRAS_CNTL_UNK11 0x00000800 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff @@ -2452,7 +2781,19 @@ static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; } -static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } +#define REG_A7XX_GRAS_UNKNOWN_8007 0x00008007 + +#define REG_A7XX_GRAS_UNKNOWN_8008 0x00008008 + +#define REG_A7XX_GRAS_UNKNOWN_8009 0x00008009 + +#define REG_A7XX_GRAS_UNKNOWN_800A 0x0000800a + +#define REG_A7XX_GRAS_UNKNOWN_800B 0x0000800b + +#define REG_A7XX_GRAS_UNKNOWN_800C 0x0000800c + +#define REG_A6XX_GRAS_CL_VPORT(i0) (0x00008010 + 0x6*(i0)) static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff @@ -2502,7 +2843,7 @@ static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; } -static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } +#define REG_A6XX_GRAS_CL_Z_CLAMP(i0) (0x00008070 + 0x2*(i0)) static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff @@ -2531,12 +2872,7 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; } #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 -#define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 -#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 -static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) -{ - return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; -} +#define A6XX_GRAS_SU_CNTL_UNK12 0x00001000 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) @@ -2549,13 +2885,14 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) { return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; } -#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 -#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 -#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 -#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 -static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) +#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00020000 +#define A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR 0x00040000 +#define A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR 0x00080000 +#define A6XX_GRAS_SU_CNTL_UNK20__MASK 0x00700000 +#define A6XX_GRAS_SU_CNTL_UNK20__SHIFT 20 +static inline uint32_t A6XX_GRAS_SU_CNTL_UNK20(uint32_t val) { - return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; + return ((val) << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK; } #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 @@ -2619,12 +2956,7 @@ static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_dep { return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; } -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 -static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) -{ - return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; -} +#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 0x00000008 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 @@ -2703,13 +3035,15 @@ static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) { - return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; } #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) { - return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; } #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 @@ -2730,12 +3064,7 @@ static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t va { return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; } -#define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000 -#define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27 -static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) -{ - return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK; -} +#define A6XX_GRAS_BIN_CONTROL_UNK27 0x08000000 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 @@ -2744,18 +3073,8 @@ static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples va { return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; } -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 -static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) -{ - return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; -} -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 -static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) -{ - return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; -} +#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2 0x00000004 +#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3 0x00000008 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 @@ -2775,49 +3094,49 @@ static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples v #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; } #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 @@ -2825,54 +3144,56 @@ static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; } +#define REG_A7XX_GRAS_UNKNOWN_80A7 0x000080a7 + #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af -static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } +#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0) (0x000080b0 + 0x2*(i0)) static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff @@ -2902,7 +3223,7 @@ static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; } -static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } +#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0) (0x000080d0 + 0x2*(i0)) static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff @@ -2960,6 +3281,18 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; } +#define REG_A7XX_GRAS_UNKNOWN_80F4 0x000080f4 + +#define REG_A7XX_GRAS_UNKNOWN_80F5 0x000080f5 + +#define REG_A7XX_GRAS_UNKNOWN_80F6 0x000080f6 + +#define REG_A7XX_GRAS_UNKNOWN_80F8 0x000080f8 + +#define REG_A7XX_GRAS_UNKNOWN_80F9 0x000080f9 + +#define REG_A7XX_GRAS_UNKNOWN_80FA 0x000080fa + #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 @@ -2975,6 +3308,12 @@ static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) } #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100 #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200 +#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK 0x00003800 +#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT 11 +static inline uint32_t A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val) +{ + return ((val) << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK; +} #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 @@ -2994,34 +3333,24 @@ static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_forma } #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 -#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff -#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; -} #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; } #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 -#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff -#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; -} #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 @@ -3046,8 +3375,24 @@ static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK; } +#define REG_A7XX_GRAS_UNKNOWN_810B 0x0000810b + #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 +#define REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 0x00008111 +#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK 0xffffffff +#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT 0 +static inline uint32_t A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val) +{ + return ((fui(val)) << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK; +} + +#define REG_A7XX_GRAS_UNKNOWN_8113 0x00008113 + +#define REG_A7XX_GRAS_UNKNOWN_8120 0x00008120 + +#define REG_A7XX_GRAS_UNKNOWN_8121 0x00008121 + #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 @@ -3095,14 +3440,39 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode { return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; } +#define A6XX_GRAS_2D_BLIT_CNTL_UNK30 0x40000000 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 +#define A6XX_GRAS_2D_SRC_TL_X__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_TL_X__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_TL_X(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK; +} #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 +#define A6XX_GRAS_2D_SRC_BR_X__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_BR_X__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_BR_X(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK; +} #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 +#define A6XX_GRAS_2D_SRC_TL_Y__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_TL_Y__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK; +} #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 +#define A6XX_GRAS_2D_SRC_BR_Y__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_BR_Y__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK; +} #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff @@ -3174,24 +3544,26 @@ static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) #define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602 -static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } +#define REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0) (0x00008610 + 0x1*(i0)) -static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } +#define REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0) (0x00008614 + 0x1*(i0)) -static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } +#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0) (0x00008618 + 0x1*(i0)) #define REG_A6XX_RB_BIN_CONTROL 0x00008800 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) { - return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; } #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) { - return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; } #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 @@ -3213,6 +3585,35 @@ static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; } +#define REG_A7XX_RB_BIN_CONTROL 0x00008800 +#define A7XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f +#define A7XX_RB_BIN_CONTROL_BINW__SHIFT 0 +static inline uint32_t A7XX_RB_BIN_CONTROL_BINW(uint32_t val) +{ + assert(!(val & 0x1f)); + return (((val >> 5)) << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK; +} +#define A7XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 +#define A7XX_RB_BIN_CONTROL_BINH__SHIFT 8 +static inline uint32_t A7XX_RB_BIN_CONTROL_BINH(uint32_t val) +{ + assert(!(val & 0xf)); + return (((val >> 4)) << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK; +} +#define A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 +#define A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 +static inline uint32_t A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) +{ + return ((val) << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK; +} +#define A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 +#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 +#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 +static inline uint32_t A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) +{ + return ((val) << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; +} + #define REG_A6XX_RB_RENDER_CNTL 0x00008801 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 @@ -3250,6 +3651,27 @@ static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; } +#define REG_A7XX_RB_RENDER_CNTL 0x00008801 +#define A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 +#define A7XX_RB_RENDER_CNTL_BINNING 0x00000080 +#define A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 +#define A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 +static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) +{ + return ((val) << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK; +} +#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 +#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 +static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) +{ + return ((val) << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; +} +#define A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 +#define A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 + +#define REG_A7XX_GRAS_SU_RENDER_CNTL 0x00008116 +#define A7XX_GRAS_SU_RENDER_CNTL_BINNING 0x00000080 + #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 @@ -3257,18 +3679,8 @@ static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; } -#define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 -#define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 -static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) -{ - return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; -} -#define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 -#define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 -static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) -{ - return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; -} +#define A6XX_RB_RAS_MSAA_CNTL_UNK2 0x00000004 +#define A6XX_RB_RAS_MSAA_CNTL_UNK3 0x00000008 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 @@ -3288,49 +3700,49 @@ static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; } #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 @@ -3338,49 +3750,49 @@ static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; } #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 @@ -3514,7 +3926,7 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dithe { return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; } -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 +#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00003000 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) { @@ -3542,6 +3954,8 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dithe #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 +#define REG_A7XX_RB_UNKNOWN_8812 0x00008812 + #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 @@ -3556,7 +3970,7 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dithe #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e -static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } +#define REG_A6XX_RB_MRT(i0) (0x00008820 + 0x8*(i0)) static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 @@ -3626,12 +4040,7 @@ static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode { return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; } -#define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 -#define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 -static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; -} +#define A6XX_RB_MRT_BUF_INFO_UNK10 0x00000400 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) @@ -3639,37 +4048,49 @@ static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; } +static inline uint32_t REG_A7XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } +#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) +{ + return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; +} +#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 +#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 +static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; +} +#define A7XX_RB_MRT_BUF_INFO_UNK10 0x00000400 +#define A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN 0x00000800 +#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 +#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 +static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; +} + static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } -#define A6XX_RB_MRT_PITCH__MASK 0x0000ffff +#define A6XX_RB_MRT_PITCH__MASK 0xffffffff #define A6XX_RB_MRT_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; } static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } -#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff +#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; } static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } -#define A6XX_RB_MRT_BASE__MASK 0xffffffff -#define A6XX_RB_MRT_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; -} static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } -#define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; -} #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff @@ -3757,6 +4178,9 @@ static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 +#define REG_A6XX_GRAS_SU_DEPTH_CNTL 0x00008114 +#define A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 + #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 @@ -3771,12 +4195,34 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; } +#define REG_A7XX_RB_DEPTH_BUFFER_INFO 0x00008872 +#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 +#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 +static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) +{ + return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; +} +#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 +#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 +static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) +{ + return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; +} +#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK 0x00000060 +#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT 5 +static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK; +} +#define A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN 0x00000080 + #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; } #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 @@ -3784,24 +4230,13 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 -#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; -} #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 -#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; -} #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff @@ -3872,16 +4307,30 @@ static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; } +#define REG_A6XX_GRAS_SU_STENCIL_CNTL 0x00008115 +#define A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE 0x00000001 + #define REG_A6XX_RB_STENCIL_INFO 0x00008881 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 +#define REG_A7XX_RB_STENCIL_INFO 0x00008881 +#define A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 +#define A7XX_RB_STENCIL_INFO_UNK1 0x00000002 +#define A7XX_RB_STENCIL_INFO_TILEMODE__MASK 0x0000000c +#define A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT 2 +static inline uint32_t A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK; +} + #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; } #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 @@ -3889,24 +4338,13 @@ static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 -#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; -} #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 -#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; -} #define REG_A6XX_RB_STENCILREF 0x00008887 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff @@ -3971,6 +4409,8 @@ static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) #define REG_A6XX_RB_LRZ_CNTL 0x00008898 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 +#define REG_A7XX_RB_UNKNOWN_8899 0x00008899 + #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 @@ -4034,13 +4474,15 @@ static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) { - return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; } #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) { - return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; } #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 @@ -4066,12 +4508,6 @@ static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_sample } #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 -#define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; -} #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 @@ -4102,19 +4538,14 @@ static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 #define REG_A6XX_RB_BLIT_DST 0x000088d8 -#define A6XX_RB_BLIT_DST__MASK 0xffffffff -#define A6XX_RB_BLIT_DST__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; -} #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; } #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db @@ -4122,29 +4553,26 @@ static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc -#define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff -#define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; -} #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; } #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df @@ -4179,46 +4607,82 @@ static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK; } -#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 +#define REG_A7XX_RB_UNKNOWN_88E4 0x000088e4 +#define A7XX_RB_UNKNOWN_88E4_UNK0 0x00000001 -#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 -#define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) +#define REG_A7XX_RB_CCU_CNTL2 0x000088e5 +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK 0x00000001 +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT 0 +static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(uint32_t val) +{ + return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK; +} +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK 0x00000004 +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT 2 +static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(uint32_t val) { - return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; + return ((val) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK; +} +#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK 0x00000c00 +#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT 10 +static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK; +} +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK 0x001ff000 +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT 12 +static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK; +} +#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK 0x00600000 +#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT 21 +static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK; +} +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK 0xff800000 +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT 23 +static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK; } +#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 + +#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 + #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; } #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 +#define REG_A7XX_RB_UNKNOWN_88F5 0x000088f5 + #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 -#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; -} #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; } #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 @@ -4230,40 +4694,31 @@ static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; } -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } +#define REG_A6XX_RB_MRT_FLAG_BUFFER(i0) (0x00008903 + 0x3*(i0)) static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } -#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff -#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) -{ - return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; -} static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; } #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 -#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff -#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 -static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) -{ - return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; -} #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 @@ -4320,6 +4775,7 @@ static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode va { return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; } +#define A6XX_RB_2D_BLIT_CNTL_UNK30 0x40000000 #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 @@ -4366,75 +4822,49 @@ static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 #define REG_A6XX_RB_2D_DST 0x00008c18 -#define A6XX_RB_2D_DST__MASK 0xffffffff -#define A6XX_RB_2D_DST__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; -} #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff #define A6XX_RB_2D_DST_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; } #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b -#define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff -#define A6XX_RB_2D_DST_PLANE1__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; -} #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; } #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e -#define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff -#define A6XX_RB_2D_DST_PLANE2__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; -} #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 -#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff -#define A6XX_RB_2D_DST_FLAGS__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; -} #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; } #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 -#define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff -#define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; -} #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; } #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c @@ -4451,7 +4881,10 @@ static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 +#define REG_A7XX_RB_UNKNOWN_8E06 0x00008e06 + #define REG_A6XX_RB_CCU_CNTL 0x00008e07 +#define A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7 @@ -4465,20 +4898,37 @@ static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) { return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK; } +#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK 0x00000c00 +#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT 10 +static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK; +} #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) { - return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; +} +#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK 0x00600000 +#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT 21 +static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK; } -#define A6XX_RB_CCU_CNTL_GMEM 0x00400000 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) { - return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; } +#define REG_A7XX_RB_CCU_CNTL 0x00008e07 +#define A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 +#define A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 + #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 @@ -4503,15 +4953,17 @@ static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; } -static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } +#define REG_A7XX_RB_UNKNOWN_8E09 0x00008e09 + +#define REG_A6XX_RB_PERFCTR_RB_SEL(i0) (0x00008e10 + 0x1*(i0)) -static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } +#define REG_A6XX_RB_PERFCTR_CCU_SEL(i0) (0x00008e18 + 0x1*(i0)) #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 -static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } +#define REG_A6XX_RB_PERFCTR_CMP_SEL(i0) (0x00008e2c + 0x1*(i0)) -static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; } +#define REG_A7XX_RB_PERFCTR_UFC_SEL(i0) (0x00008e30 + 0x1*(i0)) #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b @@ -4520,12 +4972,8 @@ static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 -#define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff -#define A6XX_RB_UNKNOWN_8E51__SHIFT 0 -static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) -{ - return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; -} + +#define REG_A7XX_RB_UNKNOWN_8E79 0x00008e79 #define REG_A6XX_VPC_GS_PARAM 0x00009100 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff @@ -4595,6 +5043,66 @@ static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; } +#define REG_A6XX_VPC_VS_CLIP_CNTL_V2 0x00009311 +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 +static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK; +} +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 +static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; +} +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 +static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; +} + +#define REG_A6XX_VPC_GS_CLIP_CNTL_V2 0x00009312 +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 +static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK; +} +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 +static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; +} +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 +static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; +} + +#define REG_A6XX_VPC_DS_CLIP_CNTL_V2 0x00009313 +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 +static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK; +} +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 +static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; +} +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 +static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; +} + #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 @@ -4608,6 +5116,12 @@ static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) { return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; } +#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK; +} #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff @@ -4622,6 +5136,12 @@ static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) { return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; } +#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK; +} #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff @@ -4636,6 +5156,72 @@ static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) { return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; } +#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK; +} + +#define REG_A6XX_VPC_VS_LAYER_CNTL_V2 0x00009314 +#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff +#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK; +} +#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 +#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK; +} +#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; +} + +#define REG_A6XX_VPC_GS_LAYER_CNTL_V2 0x00009315 +#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff +#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK; +} +#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 +#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK; +} +#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; +} + +#define REG_A6XX_VPC_DS_LAYER_CNTL_V2 0x00009316 +#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff +#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK; +} +#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 +#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK; +} +#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; +} #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 @@ -4649,11 +5235,51 @@ static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; } -static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } +#define REG_A7XX_VPC_PRIMITIVE_CNTL_0 0x00009109 +#define A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 +#define A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 +#define A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 +#define A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 0x00000008 + +#define REG_A7XX_VPC_PRIMITIVE_CNTL_5 0x0000910a +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 +static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) +{ + return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; +} +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 +static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) +{ + return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; +} +#define A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 +static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) +{ + return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; +} +#define A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 0x00040000 + +#define REG_A7XX_VPC_MULTIVIEW_MASK 0x0000910b + +#define REG_A7XX_VPC_MULTIVIEW_CNTL 0x0000910c +#define A7XX_VPC_MULTIVIEW_CNTL_ENABLE 0x00000001 +#define A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 +#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c +#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 +static inline uint32_t A7XX_VPC_MULTIVIEW_CNTL_VIEWS(uint32_t val) +{ + return ((val) << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK; +} + +#define REG_A6XX_VPC_VARYING_INTERP(i0) (0x00009200 + 0x1*(i0)) static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } -static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } +#define REG_A6XX_VPC_VARYING_PS_REPL(i0) (0x00009208 + 0x1*(i0)) static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } @@ -4661,7 +5287,7 @@ static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 -static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } +#define REG_A6XX_VPC_VAR(i0) (0x00009212 + 0x1*(i0)) static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } @@ -4685,7 +5311,8 @@ static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) { - return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; } #define A6XX_VPC_SO_PROG_A_EN 0x00000800 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 @@ -4698,59 +5325,24 @@ static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) { - return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; } #define A6XX_VPC_SO_PROG_B_EN 0x00800000 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 -#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff -#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; -} -static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } +#define REG_A6XX_VPC_SO(i0) (0x0000921a + 0x7*(i0)) static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff -#define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc -#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 -static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) -{ - return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_STRIDE__MASK 0x000003ff -#define A6XX_VPC_SO_BUFFER_STRIDE__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val) -{ - return ((val >> 2) << A6XX_VPC_SO_BUFFER_STRIDE__SHIFT) & A6XX_VPC_SO_BUFFER_STRIDE__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc -#define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 -static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) -{ - return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } -#define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff -#define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; -} #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 @@ -4891,6 +5483,38 @@ static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) #define REG_A6XX_VPC_SO_DISABLE 0x00009306 #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 +#define REG_A7XX_VPC_POLYGON_MODE2 0x00009307 +#define A7XX_VPC_POLYGON_MODE2_MODE__MASK 0x00000003 +#define A7XX_VPC_POLYGON_MODE2_MODE__SHIFT 0 +static inline uint32_t A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val) +{ + return ((val) << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK; +} + +#define REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM 0x00009308 +#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff +#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 +static inline uint32_t A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) +{ + return ((val) << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; +} + +#define REG_A7XX_VPC_ATTR_BUF_BASE_GMEM 0x00009309 +#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK 0xffffffff +#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT 0 +static inline uint32_t A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(uint32_t val) +{ + return ((val) << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK; +} + +#define REG_A7XX_PC_ATTR_BUF_SIZE_GMEM 0x00009b09 +#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff +#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 +static inline uint32_t A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) +{ + return ((val) << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; +} + #define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 @@ -4899,9 +5523,9 @@ static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 -static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } +#define REG_A6XX_VPC_PERFCTR_VPC_SEL(i0) (0x00009604 + 0x1*(i0)) -static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; } +#define REG_A7XX_VPC_PERFCTR_VPC_SEL(i0) (0x0000960b + 0x1*(i0)) #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 @@ -4912,12 +5536,7 @@ static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) { return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; } -#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 -#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 -static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) -{ - return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; -} +#define A6XX_PC_HS_INPUT_SIZE_UNK13 0x00002000 #define REG_A6XX_PC_TESS_CNTL 0x00009802 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 @@ -4939,7 +5558,8 @@ static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) #define REG_A6XX_PC_POWER_CNTL 0x00009805 -#define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 +#define REG_A6XX_PC_PS_CNTL 0x00009806 +#define A6XX_PC_PS_CNTL_PRIMITIVEIDEN 0x00000001 #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 @@ -4992,6 +5612,14 @@ static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; } +#define REG_A7XX_PC_POLYGON_MODE 0x00009809 +#define A7XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 +#define A7XX_PC_POLYGON_MODE_MODE__SHIFT 0 +static inline uint32_t A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) +{ + return ((val) << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK; +} + #define REG_A6XX_PC_RASTER_CNTL 0x00009980 #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 @@ -5001,10 +5629,28 @@ static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) } #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 +#define REG_A7XX_PC_RASTER_CNTL 0x00009107 +#define A7XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 +#define A7XX_PC_RASTER_CNTL_STREAM__SHIFT 0 +static inline uint32_t A7XX_PC_RASTER_CNTL_STREAM(uint32_t val) +{ + return ((val) << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK; +} +#define A7XX_PC_RASTER_CNTL_DISCARD 0x00000004 + +#define REG_A7XX_PC_RASTER_CNTL_V2 0x00009317 +#define A7XX_PC_RASTER_CNTL_V2_STREAM__MASK 0x00000003 +#define A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT 0 +static inline uint32_t A7XX_PC_RASTER_CNTL_V2_STREAM(uint32_t val) +{ + return ((val) << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK; +} +#define A7XX_PC_RASTER_CNTL_V2_DISCARD 0x00000004 + #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 -#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 +#define A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 @@ -5024,6 +5670,7 @@ static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_VS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff @@ -5042,6 +5689,7 @@ static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_GS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff @@ -5060,6 +5708,7 @@ static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_HS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff @@ -5078,6 +5727,7 @@ static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_DS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff @@ -5099,12 +5749,7 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output { return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; } -#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 -#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 -static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; -} +#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18 0x00040000 #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff @@ -5151,12 +5796,8 @@ static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 -#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff -#define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 -static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) -{ - return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; -} + +#define REG_A7XX_PC_TESSFACTOR_ADDR 0x00009810 #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f @@ -5217,27 +5858,17 @@ static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) } #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 -#define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff -#define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 -static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) -{ - return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; -} #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 -#define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff -#define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 -static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) -{ - return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; -} #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 -static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } +#define REG_A7XX_PC_UNKNOWN_9E24 0x00009e24 + +#define REG_A6XX_PC_PERFCTR_PC_SEL(i0) (0x00009e34 + 0x1*(i0)) -static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; } +#define REG_A7XX_PC_PERFCTR_PC_SEL(i0) (0x00009e42 + 0x1*(i0)) #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 @@ -5344,7 +5975,7 @@ static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) } #define REG_A6XX_VFD_CONTROL_6 0x0000a006 -#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 +#define A6XX_VFD_CONTROL_6_PRIMID4PSEN 0x00000001 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 @@ -5372,21 +6003,15 @@ static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f -static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } +#define REG_A6XX_VFD_FETCH(i0) (0x0000a010 + 0x4*(i0)) static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } -#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff -#define A6XX_VFD_FETCH_BASE__SHIFT 0 -static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) -{ - return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; -} static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } -static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } +#define REG_A6XX_VFD_DECODE(i0) (0x0000a090 + 0x2*(i0)) static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f @@ -5419,7 +6044,7 @@ static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } -static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } +#define REG_A6XX_VFD_DEST_CNTL(i0) (0x0000a0d0 + 0x1*(i0)) static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f @@ -5437,15 +6062,15 @@ static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 +#define REG_A7XX_VFD_UNKNOWN_A600 0x0000a600 + #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 -static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } +#define REG_A6XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0)) -static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } +#define REG_A7XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0)) #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 -#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 -#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5471,6 +6096,8 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 +#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 @@ -5488,7 +6115,7 @@ static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; } -static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } +#define REG_A6XX_SP_VS_OUT(i0) (0x0000a803 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff @@ -5516,7 +6143,7 @@ static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } +#define REG_A6XX_SP_VS_VPC_DST(i0) (0x0000a813 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -5547,19 +6174,14 @@ static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c -#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_VS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; -} #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -5569,19 +6191,14 @@ static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f -#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -5619,11 +6236,13 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_VS_VGPR_CONFIG 0x0000a82d + #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 -#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5649,6 +6268,7 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 @@ -5657,19 +6277,14 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 -#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_HS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; -} #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -5679,19 +6294,14 @@ static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 -#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -5729,11 +6339,13 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_HS_VGPR_CONFIG 0x0000a82f + #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 -#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5759,6 +6371,7 @@ static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 @@ -5776,7 +6389,7 @@ static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; } -static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } +#define REG_A6XX_SP_DS_OUT(i0) (0x0000a843 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff @@ -5804,7 +6417,7 @@ static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } +#define REG_A6XX_SP_DS_VPC_DST(i0) (0x0000a853 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -5835,19 +6448,14 @@ static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c -#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_DS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; -} #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -5857,19 +6465,14 @@ static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f -#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -5907,11 +6510,13 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_DS_VGPR_CONFIG 0x0000a868 + #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 -#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5937,6 +6542,7 @@ static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 @@ -5956,7 +6562,7 @@ static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; } -static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } +#define REG_A6XX_SP_GS_OUT(i0) (0x0000a874 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff @@ -5984,7 +6590,7 @@ static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } +#define REG_A6XX_SP_GS_VPC_DST(i0) (0x0000a884 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -6015,19 +6621,14 @@ static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d -#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_GS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; -} #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -6037,19 +6638,14 @@ static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 -#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -6087,89 +6683,29 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_GS_VGPR_CONFIG 0x0000a899 + #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 -#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_VS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 -#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_HS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 -#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_DS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 -#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_GS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 -#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_VS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; -} #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa -#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_HS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; -} #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac -#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_DS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; -} #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae -#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_GS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; -} #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 -#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 -#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 -#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 -#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 -#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -6195,25 +6731,35 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 +#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 +static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; +} +#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 +#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 +#define A6XX_SP_FS_CTRL_REG0_LODPIXMASK 0x00800000 +#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 +#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 +#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 +#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 +#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 +#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 -#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_FS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; -} #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -6223,19 +6769,14 @@ static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 -#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -6339,7 +6880,7 @@ static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; } -static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } +#define REG_A6XX_SP_FS_OUTPUT(i0) (0x0000a98e + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff @@ -6350,7 +6891,7 @@ static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) } #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 -static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } +#define REG_A6XX_SP_FS_MRT(i0) (0x0000a996 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff @@ -6371,16 +6912,22 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; } #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008 -#define A6XX_SP_FS_PREFETCH_CNTL_UNK4 0x00000010 +#define A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD 0x00000010 #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020 -#define A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK 0x00007fc0 -#define A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT 6 -static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val) +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK 0x00007fc0 +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT 6 +static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(uint32_t val) +{ + return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK; +} +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK 0x01ff0000 +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT 16 +static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(uint32_t val) { - return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK; + return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK; } -static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } +#define REG_A6XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f @@ -6423,7 +6970,49 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd va return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; } -static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } +#define REG_A7XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0)) + +static inline uint32_t REG_A7XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } +#define A7XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f +#define A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000380 +#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x00001c00 +#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 10 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_DST__MASK 0x0007e000 +#define A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT 13 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x00780000 +#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 19 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_HALF 0x00800000 +#define A7XX_SP_FS_PREFETCH_CMD_BINDLESS 0x02000000 +#define A7XX_SP_FS_PREFETCH_CMD_CMD__MASK 0x3c000000 +#define A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 26 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK; +} + +#define REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0) (0x0000a9a3 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff @@ -6448,20 +7037,11 @@ static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 -#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 -#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 -#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -6487,6 +7067,16 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 +#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 +static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; +} +#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 +#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 +#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 +#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f @@ -6503,19 +7093,14 @@ static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 -#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_CS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; -} #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -6525,19 +7110,14 @@ static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 -#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -6575,9 +7155,14 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_CS_UNKNOWN_A9BE 0x0000a9be + +#define REG_A7XX_SP_CS_VGPR_CONFIG 0x0000a9c5 + #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 @@ -6620,39 +7205,31 @@ static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) } #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 -#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 -#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_FS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) +#define REG_A7XX_SP_CS_CNTL_1 0x0000a9c3 +#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff +#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 +static inline uint32_t A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) { - return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; + return ((val) << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; } - -#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 -#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_CS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) +#define A7XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000100 +#define A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 8 +static inline uint32_t A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) { - return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; + return ((val) << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK; } +#define A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000200 +#define A7XX_SP_CS_CNTL_1_UNK15 0x00008000 + +#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 + +#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 -#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_FS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; -} #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 -#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_CS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; -} -static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } +#define REG_A6XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0)) static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -6661,23 +7238,92 @@ static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_b { return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } -#define REG_A6XX_SP_CS_IBO 0x0000a9f2 -#define A6XX_SP_CS_IBO__MASK 0xffffffff -#define A6XX_SP_CS_IBO__SHIFT 0 -static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) +#define REG_A7XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0)) + +static inline uint32_t REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 +static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) +{ + return ((val) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; +} +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 +static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } +#define REG_A6XX_SP_CS_IBO 0x0000a9f2 + #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 +#define REG_A7XX_SP_FS_VGPR_CONFIG 0x0000aa01 + +#define REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL 0x0000aa02 +#define A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED 0x00000001 + +#define REG_A7XX_SP_PS_ALIASED_COMPONENTS 0x0000aa03 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK 0x0000000f +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT 0 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT0(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK 0x000000f0 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT 4 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT1(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK 0x00000f00 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT 8 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT2(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK 0x0000f000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT 12 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT3(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK 0x000f0000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT 16 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT4(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK 0x00f00000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT 20 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT5(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK 0x0f000000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT 24 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT6(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK 0xf0000000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT 28 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT7(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK; +} + +#define REG_A6XX_SP_UNKNOWN_AAF2 0x0000aaf2 + #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 @@ -6688,6 +7334,10 @@ static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) } #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 +#define REG_A7XX_SP_UNKNOWN_AB01 0x0000ab01 + +#define REG_A7XX_SP_UNKNOWN_AB02 0x0000ab02 + #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 @@ -6715,7 +7365,7 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 -static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } +#define REG_A6XX_SP_BINDLESS_BASE(i0) (0x0000ab10 + 0x2*(i0)) static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -6724,23 +7374,37 @@ static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bind { return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } -#define REG_A6XX_SP_IBO 0x0000ab1a -#define A6XX_SP_IBO__MASK 0xffffffff -#define A6XX_SP_IBO__SHIFT 0 -static inline uint32_t A6XX_SP_IBO(uint32_t val) +#define REG_A7XX_SP_BINDLESS_BASE(i0) (0x0000ab0a + 0x2*(i0)) + +static inline uint32_t REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab0a + 0x2*i0; } +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 +static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { - return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; + return ((val) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; +} +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 +static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } +#define REG_A6XX_SP_IBO 0x0000ab1a + #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 +#define REG_A7XX_SP_UNKNOWN_AB22 0x0000ab22 + #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 @@ -6759,6 +7423,24 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; } +#define REG_A7XX_SP_2D_DST_FORMAT 0x0000a9bf +#define A7XX_SP_2D_DST_FORMAT_NORM 0x00000001 +#define A7XX_SP_2D_DST_FORMAT_SINT 0x00000002 +#define A7XX_SP_2D_DST_FORMAT_UINT 0x00000004 +#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 +#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 +static inline uint32_t A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) +{ + return ((val) << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; +} +#define A7XX_SP_2D_DST_FORMAT_SRGB 0x00000800 +#define A7XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 +#define A7XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 +static inline uint32_t A7XX_SP_2D_DST_FORMAT_MASK(uint32_t val) +{ + return ((val) << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK; +} + #define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 @@ -6770,6 +7452,14 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 +#define REG_A7XX_SP_UNKNOWN_AE06 0x0000ae06 + +#define REG_A7XX_SP_UNKNOWN_AE08 0x0000ae08 + +#define REG_A7XX_SP_UNKNOWN_AE09 0x0000ae09 + +#define REG_A7XX_SP_UNKNOWN_AE0A 0x0000ae0a + #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 @@ -6778,23 +7468,57 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 -static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } +#define REG_A6XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae10 + 0x1*(i0)) + +#define REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0) (0x0000ae60 + 0x1*(i0)) -static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; } +#define REG_A7XX_SP_UNKNOWN_AE6A 0x0000ae6a + +#define REG_A7XX_SP_UNKNOWN_AE6B 0x0000ae6b + +#define REG_A7XX_SP_UNKNOWN_AE6C 0x0000ae6c #define REG_A7XX_SP_READ_SEL 0x0000ae6d +#define A7XX_SP_READ_SEL_LOCATION__MASK 0x000c0000 +#define A7XX_SP_READ_SEL_LOCATION__SHIFT 18 +static inline uint32_t A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val) +{ + return ((val) << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK; +} +#define A7XX_SP_READ_SEL_PIPE__MASK 0x00030000 +#define A7XX_SP_READ_SEL_PIPE__SHIFT 16 +static inline uint32_t A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val) +{ + return ((val) << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK; +} +#define A7XX_SP_READ_SEL_STATETYPE__MASK 0x0000ff00 +#define A7XX_SP_READ_SEL_STATETYPE__SHIFT 8 +static inline uint32_t A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val) +{ + return ((val) << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK; +} +#define A7XX_SP_READ_SEL_USPTP__MASK 0x000000f0 +#define A7XX_SP_READ_SEL_USPTP__SHIFT 4 +static inline uint32_t A7XX_SP_READ_SEL_USPTP(uint32_t val) +{ + return ((val) << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK; +} +#define A7XX_SP_READ_SEL_SPTP__MASK 0x0000000f +#define A7XX_SP_READ_SEL_SPTP__SHIFT 0 +static inline uint32_t A7XX_SP_READ_SEL_SPTP(uint32_t val) +{ + return ((val) << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK; +} + +#define REG_A7XX_SP_DBG_CNTL 0x0000ae71 -static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; } +#define REG_A7XX_SP_UNKNOWN_AE73 0x0000ae73 + +#define REG_A7XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae80 + 0x1*(i0)) #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 -#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff -#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; -} #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 @@ -6828,12 +7552,6 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 -#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff -#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; -} #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 @@ -6844,49 +7562,49 @@ static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; } #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 @@ -6894,49 +7612,49 @@ static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; } #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 @@ -6967,6 +7685,8 @@ static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; } +#define REG_A7XX_SP_UNKNOWN_B310 0x0000b310 + #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 @@ -7024,12 +7744,6 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) } #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 -#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) -{ - return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; -} #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff @@ -7042,47 +7756,129 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; } -#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 -#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) +#define REG_A7XX_SP_PS_2D_SRC_INFO 0x0000b2c0 +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 +#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) { - return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; + return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; } +#define A7XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 +#define A7XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 +#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 +#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 +#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 + +#define REG_A7XX_SP_PS_2D_SRC_SIZE 0x0000b2c1 +#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff +#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; +} +#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 +#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 +static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; +} + +#define REG_A7XX_SP_PS_2D_SRC 0x0000b2c2 + +#define REG_A7XX_SP_PS_2D_SRC_PITCH 0x0000b2c4 +#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff +#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; +} +#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 +#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 +static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; +} + +#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; } #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 -#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) + +#define REG_A7XX_SP_PS_2D_SRC_PLANE1 0x0000b2c5 + +#define REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b2c7 +#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff +#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) { - return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; } +#define REG_A7XX_SP_PS_2D_SRC_PLANE2 0x0000b2c8 + #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca -#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; -} #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; +} + +#define REG_A7XX_SP_PS_2D_SRC_FLAGS 0x0000b2ca + +#define REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b2cc +#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff +#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return (((val >> 6)) << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; } #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd @@ -7107,6 +7903,44 @@ static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; } +#define REG_A7XX_SP_PS_UNKNOWN_B4CD 0x0000b2cd + +#define REG_A7XX_SP_PS_UNKNOWN_B4CE 0x0000b2ce + +#define REG_A7XX_SP_PS_UNKNOWN_B4CF 0x0000b2cf + +#define REG_A7XX_SP_PS_UNKNOWN_B4D0 0x0000b2d0 + +#define REG_A7XX_SP_PS_2D_WINDOW_OFFSET 0x0000b2d1 +#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK 0x00003fff +#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK; +} +#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK 0x3fff0000 +#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK; +} + +#define REG_A7XX_SP_PS_UNKNOWN_B2D2 0x0000b2d2 + +#define REG_A7XX_SP_WINDOW_OFFSET 0x0000ab21 +#define A7XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff +#define A7XX_SP_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A7XX_SP_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK; +} +#define A7XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 +#define A7XX_SP_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A7XX_SP_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK; +} + #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 @@ -7147,53 +7981,126 @@ static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c -static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c + +#define REG_A6XX_TPL1_PERFCTR_TP_SEL(i0) (0x0000b610 + 0x1*(i0)) #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 -#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 +#define REG_A7XX_HLSQ_VS_CNTL 0x0000a827 +#define A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_VS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 -#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 -#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff -#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 -static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) +#define REG_A7XX_HLSQ_HS_CNTL 0x0000a83f +#define A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) { - return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK; } +#define A7XX_HLSQ_HS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_DS_CNTL 0x0000a867 +#define A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_DS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_GS_CNTL 0x0000a898 +#define A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_GS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_FS_UNKNOWN_A9AA 0x0000a9aa +#define A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE 0x00000001 + +#define REG_A7XX_HLSQ_UNKNOWN_A9AC 0x0000a9ac + +#define REG_A7XX_HLSQ_UNKNOWN_A9AD 0x0000a9ad + +#define REG_A7XX_HLSQ_UNKNOWN_A9AE 0x0000a9ae +#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK 0x000000ff +#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT 0 +static inline uint32_t A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(uint32_t val) +{ + return ((val) << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK; +} +#define A7XX_HLSQ_UNKNOWN_A9AE_UNK8 0x00000100 +#define A7XX_HLSQ_UNKNOWN_A9AE_UNK9 0x00000200 + +#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 + +#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 @@ -7215,8 +8122,12 @@ static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 - -#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 +#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 +#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; +} #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff @@ -7244,32 +8155,6 @@ static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; } -#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 -#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 -#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; -} - #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 @@ -7296,32 +8181,6 @@ static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; } -#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; -} - #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 @@ -7348,6 +8207,106 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; } +#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 +#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff +#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; +} +#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 +#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 +static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; +} + +#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 +#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff +#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; +} +#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_FS_CNTL_0 0x0000a9c6 +#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 +#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 +static inline uint32_t A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; +} +#define A7XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 +#define A7XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc +#define A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 +static inline uint32_t A7XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) +{ + return ((val) << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK; +} + +#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 +#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 +#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; +} + +#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 +#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff +#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; +} +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; +} +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; +} +#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 +#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; +} + +#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; +} +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; +} +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; +} +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; +} + #define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 @@ -7374,20 +8333,6 @@ static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; } -#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 -#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; -} -#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 -#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 -static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; -} - #define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 @@ -7402,14 +8347,16 @@ static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t va return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; } -#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) +#define REG_A7XX_HLSQ_CS_CNTL 0x0000a9cd +#define A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK; } -#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_CS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 @@ -7533,19 +8480,136 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b -#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 +#define REG_A7XX_HLSQ_CS_NDRANGE_0 0x0000a9d4 +#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 +#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; +} +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; +} +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; +} +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; +} -#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 -#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff -#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 -static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) +#define REG_A7XX_HLSQ_CS_NDRANGE_1 0x0000a9d5 +#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_2 0x0000a9d6 +#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_3 0x0000a9d7 +#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_4 0x0000a9d8 +#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_5 0x0000a9d9 +#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_6 0x0000a9da +#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) { - return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; + return ((val) << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; } +#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_X 0x0000a9dc + +#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000a9dd + +#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000a9de + +#define REG_A7XX_HLSQ_CS_CNTL_1 0x0000a9db +#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff +#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; +} +#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 +#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 +static inline uint32_t A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; +} +#define A7XX_HLSQ_CS_CNTL_1_UNK11 0x00000800 +#define A7XX_HLSQ_CS_CNTL_1_UNK22 0x00400000 +#define A7XX_HLSQ_CS_CNTL_1_UNK26 0x04000000 +#define A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK 0x78000000 +#define A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT 27 +static inline uint32_t A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val) +{ + return ((val) << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK; +} + +#define REG_A7XX_HLSQ_CS_LOCAL_SIZE 0x0000a9df +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK 0x00000ffc +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT 2 +static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK; +} +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK 0x003ff000 +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT 12 +static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK; +} +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK 0xffc00000 +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT 22 +static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK; +} + +#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 + +#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 + #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 -static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } +#define REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0) (0x0000b9c0 + 0x2*(i0)) static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -7554,11 +8618,12 @@ static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx { return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 @@ -7625,19 +8690,56 @@ static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; } +#define REG_A7XX_HLSQ_INVALIDATE_CMD 0x0000ab1f +#define A7XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 +#define A7XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 +#define A7XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 +#define A7XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 +#define A7XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 +#define A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x0001fe00 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 +static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) +{ + return ((val) << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; +} +#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x01fe0000 +#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 17 +static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) +{ + return ((val) << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; +} + #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_FS_CNTL 0x0000ab03 +#define A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_FS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0) (0x0000ab40 + 0x1*(i0)) #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 -static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } +#define REG_A6XX_HLSQ_BINDLESS_BASE(i0) (0x0000bb20 + 0x2*(i0)) static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -7646,11 +8748,12 @@ static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bi { return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 @@ -7677,12 +8780,18 @@ static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 -static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } +#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0) (0x0000be10 + 0x1*(i0)) #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 #define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000 +#define REG_A7XX_SP_UNKNOWN_0CE2 0x00000ce2 + +#define REG_A7XX_SP_UNKNOWN_0CE4 0x00000ce4 + +#define REG_A7XX_SP_UNKNOWN_0CE6 0x00000ce6 + #define REG_A6XX_CP_EVENT_START 0x0000d600 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 @@ -7907,17 +9016,19 @@ static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) } #define REG_A6XX_TEX_CONST_3 0x00000003 -#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff +#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x007fffff #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) { - return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; } #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) { - return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; } #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 #define A6XX_TEX_CONST_3_FLAG 0x10000000 @@ -7927,7 +9038,8 @@ static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) { - return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; } #define REG_A6XX_TEX_CONST_5 0x00000005 @@ -7963,7 +9075,8 @@ static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) { - return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; } #define REG_A6XX_TEX_CONST_8 0x00000008 @@ -7979,7 +9092,8 @@ static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; } #define REG_A6XX_TEX_CONST_10 0x0000000a @@ -7987,7 +9101,8 @@ static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; } #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 @@ -8262,4 +9377,2482 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039 +#ifdef __cplusplus +template<chip CHIP> constexpr inline uint16_t CMD_REGS[] = {}; +template<chip CHIP> constexpr inline uint16_t RP_BLIT_REGS[] = {}; +template<> constexpr inline uint16_t CMD_REGS<A6XX>[] = { + 0xc03, + 0xc04, + 0xc30, + 0xc31, + 0xc32, + 0xc33, + 0xc34, + 0xc35, + 0xc36, + 0xc37, + 0xe12, + 0xe17, + 0xe19, + 0x8099, + 0x80af, + 0x810a, + 0x8110, + 0x8600, + 0x880e, + 0x8811, + 0x8818, + 0x8819, + 0x881a, + 0x881b, + 0x881c, + 0x881d, + 0x881e, + 0x8864, + 0x8891, + 0x88f0, + 0x8927, + 0x8928, + 0x8e01, + 0x8e04, + 0x8e07, + 0x9210, + 0x9211, + 0x9218, + 0x9219, + 0x921a, + 0x921b, + 0x921c, + 0x921d, + 0x921e, + 0x921f, + 0x9220, + 0x9221, + 0x9222, + 0x9223, + 0x9224, + 0x9225, + 0x9226, + 0x9227, + 0x9228, + 0x9229, + 0x922a, + 0x922b, + 0x922c, + 0x922d, + 0x922e, + 0x922f, + 0x9230, + 0x9231, + 0x9232, + 0x9233, + 0x9234, + 0x9235, + 0x9236, + 0x9300, + 0x9600, + 0x9601, + 0x9602, + 0x9e08, + 0x9e09, + 0x9e72, + 0xa007, + 0xa009, + 0xa8a0, + 0xa8a1, + 0xa8a2, + 0xa8a3, + 0xa8a4, + 0xa8a5, + 0xa8a6, + 0xa8a7, + 0xa8a8, + 0xa8a9, + 0xa8aa, + 0xa8ab, + 0xa8ac, + 0xa8ad, + 0xa8ae, + 0xa8af, + 0xa9a8, + 0xa9b0, + 0xa9b1, + 0xa9b2, + 0xa9b3, + 0xa9b4, + 0xa9b5, + 0xa9b6, + 0xa9b7, + 0xa9b8, + 0xa9b9, + 0xa9ba, + 0xa9bb, + 0xa9bc, + 0xa9bd, + 0xa9c2, + 0xa9c3, + 0xa9e2, + 0xa9e3, + 0xa9e6, + 0xa9e7, + 0xa9e8, + 0xa9e9, + 0xa9ea, + 0xa9eb, + 0xa9ec, + 0xa9ed, + 0xa9ee, + 0xa9ef, + 0xa9f0, + 0xa9f1, + 0xaaf2, + 0xab1a, + 0xab1b, + 0xab20, + 0xae00, + 0xae03, + 0xae04, + 0xae0f, + 0xb180, + 0xb181, + 0xb182, + 0xb183, + 0xb302, + 0xb303, + 0xb309, + 0xb600, + 0xb602, + 0xb605, + 0xb987, + 0xb9d0, + 0xbb08, + 0xbb11, + 0xbb20, + 0xbb21, + 0xbb22, + 0xbb23, + 0xbb24, + 0xbb25, + 0xbb26, + 0xbb27, + 0xbb28, + 0xbb29, + 0xbe00, + 0xbe01, + 0xbe04, +}; +template<> constexpr inline uint16_t CMD_REGS<A7XX>[] = { + 0xc03, + 0xc04, + 0xc30, + 0xc31, + 0xc32, + 0xc33, + 0xc34, + 0xc35, + 0xc36, + 0xc37, + 0xce2, + 0xce3, + 0xce4, + 0xce5, + 0xce6, + 0xce7, + 0xe10, + 0xe11, + 0xe12, + 0xe17, + 0xe19, + 0x8008, + 0x8009, + 0x800a, + 0x800b, + 0x800c, + 0x8099, + 0x80a7, + 0x80af, + 0x80f4, + 0x80f5, + 0x80f5, + 0x80f6, + 0x80f6, + 0x80f7, + 0x80f8, + 0x80f9, + 0x80f9, + 0x80fa, + 0x80fa, + 0x80fb, + 0x810a, + 0x810b, + 0x8110, + 0x8120, + 0x8121, + 0x8600, + 0x880e, + 0x8811, + 0x8818, + 0x8819, + 0x881a, + 0x881b, + 0x881c, + 0x881d, + 0x881e, + 0x8864, + 0x8891, + 0x8899, + 0x88e5, + 0x88f0, + 0x8927, + 0x8928, + 0x8e01, + 0x8e04, + 0x8e06, + 0x8e07, + 0x8e09, + 0x8e79, + 0x9218, + 0x9219, + 0x921a, + 0x921b, + 0x921c, + 0x921d, + 0x921e, + 0x921f, + 0x9220, + 0x9221, + 0x9222, + 0x9223, + 0x9224, + 0x9225, + 0x9226, + 0x9227, + 0x9228, + 0x9229, + 0x922a, + 0x922b, + 0x922c, + 0x922d, + 0x922e, + 0x922f, + 0x9230, + 0x9231, + 0x9232, + 0x9233, + 0x9234, + 0x9235, + 0x9236, + 0x9300, + 0x9600, + 0x9601, + 0x9602, + 0x9810, + 0x9811, + 0x9e24, + 0x9e72, + 0xa007, + 0xa009, + 0xa600, + 0xa82d, + 0xa82f, + 0xa868, + 0xa899, + 0xa8a0, + 0xa8a1, + 0xa8a2, + 0xa8a3, + 0xa8a4, + 0xa8a5, + 0xa8a6, + 0xa8a7, + 0xa8a8, + 0xa8a9, + 0xa8aa, + 0xa8ab, + 0xa8ac, + 0xa8ad, + 0xa8ae, + 0xa8af, + 0xa9a8, + 0xa9ac, + 0xa9ad, + 0xa9b0, + 0xa9b1, + 0xa9b2, + 0xa9b3, + 0xa9b4, + 0xa9b5, + 0xa9b6, + 0xa9b7, + 0xa9b8, + 0xa9b9, + 0xa9ba, + 0xa9bb, + 0xa9bc, + 0xa9bd, + 0xa9be, + 0xa9c2, + 0xa9c3, + 0xa9c5, + 0xa9cd, + 0xa9df, + 0xa9e2, + 0xa9e3, + 0xa9e6, + 0xa9e7, + 0xa9e8, + 0xa9e9, + 0xa9ea, + 0xa9eb, + 0xa9ec, + 0xa9ed, + 0xa9ee, + 0xa9ef, + 0xa9f0, + 0xa9f1, + 0xa9f2, + 0xa9f3, + 0xa9f4, + 0xa9f5, + 0xa9f6, + 0xa9f7, + 0xaa01, + 0xaa02, + 0xaa03, + 0xaaf2, + 0xab01, + 0xab02, + 0xab1a, + 0xab1b, + 0xab1f, + 0xab20, + 0xab22, + 0xae00, + 0xae03, + 0xae04, + 0xae06, + 0xae08, + 0xae09, + 0xae0a, + 0xae0f, + 0xae6a, + 0xae6b, + 0xae6c, + 0xae73, + 0xb180, + 0xb181, + 0xb182, + 0xb183, + 0xb302, + 0xb303, + 0xb309, + 0xb310, + 0xb600, + 0xb602, + 0xb608, + 0xb609, + 0xb60a, + 0xb60b, + 0xb60c, +}; +template<> constexpr inline uint16_t RP_BLIT_REGS<A6XX>[] = { + 0xc02, + 0xc06, + 0xc10, + 0xc11, + 0xc12, + 0xc13, + 0xc14, + 0xc15, + 0xc16, + 0xc17, + 0xc18, + 0xc19, + 0xc1a, + 0xc1b, + 0xc1c, + 0xc1d, + 0xc1e, + 0xc1f, + 0xc20, + 0xc21, + 0xc22, + 0xc23, + 0xc24, + 0xc25, + 0xc26, + 0xc27, + 0xc28, + 0xc29, + 0xc2a, + 0xc2b, + 0xc2c, + 0xc2d, + 0xc2e, + 0xc2f, + 0xc38, + 0xc39, + 0xc3a, + 0xc3b, + 0xc3c, + 0xc3d, + 0xc3e, + 0xc3f, + 0xc40, + 0xc41, + 0xc42, + 0xc43, + 0xc44, + 0xc45, + 0xc46, + 0xc47, + 0xc48, + 0xc49, + 0xc4a, + 0xc4b, + 0xc4c, + 0xc4d, + 0xc4e, + 0xc4f, + 0xc50, + 0xc51, + 0xc52, + 0xc53, + 0xc54, + 0xc55, + 0xc56, + 0xc57, + 0xc58, + 0xc59, + 0xc5a, + 0xc5b, + 0xc5c, + 0xc5d, + 0xc5e, + 0xc5f, + 0xc60, + 0xc61, + 0xc62, + 0xc63, + 0xc64, + 0xc65, + 0xc66, + 0xc67, + 0xc68, + 0xc69, + 0xc6a, + 0xc6b, + 0xc6c, + 0xc6d, + 0xc6e, + 0xc6f, + 0xc70, + 0xc71, + 0xc72, + 0xc73, + 0xc74, + 0xc75, + 0xc76, + 0xc77, + 0xc78, + 0xc79, + 0xc7a, + 0xc7b, + 0xc7c, + 0xc7d, + 0xc7e, + 0xc7f, + 0xc80, + 0xc81, + 0xc82, + 0xc83, + 0xc84, + 0xc85, + 0xc86, + 0xc87, + 0xc88, + 0xc89, + 0xc8a, + 0xc8b, + 0xc8c, + 0xc8d, + 0xc8e, + 0xc8f, + 0xc90, + 0xc91, + 0xc92, + 0xc93, + 0xc94, + 0xc95, + 0xc96, + 0xc97, + 0x8000, + 0x8001, + 0x8002, + 0x8003, + 0x8004, + 0x8005, + 0x8006, + 0x8010, + 0x8011, + 0x8012, + 0x8013, + 0x8014, + 0x8015, + 0x8016, + 0x8017, + 0x8018, + 0x8019, + 0x801a, + 0x801b, + 0x801c, + 0x801d, + 0x801e, + 0x801f, + 0x8020, + 0x8021, + 0x8022, + 0x8023, + 0x8024, + 0x8025, + 0x8026, + 0x8027, + 0x8028, + 0x8029, + 0x802a, + 0x802b, + 0x802c, + 0x802d, + 0x802e, + 0x802f, + 0x8030, + 0x8031, + 0x8032, + 0x8033, + 0x8034, + 0x8035, + 0x8036, + 0x8037, + 0x8038, + 0x8039, + 0x803a, + 0x803b, + 0x803c, + 0x803d, + 0x803e, + 0x803f, + 0x8040, + 0x8041, + 0x8042, + 0x8043, + 0x8044, + 0x8045, + 0x8046, + 0x8047, + 0x8048, + 0x8049, + 0x804a, + 0x804b, + 0x804c, + 0x804d, + 0x804e, + 0x804f, + 0x8050, + 0x8051, + 0x8052, + 0x8053, + 0x8054, + 0x8055, + 0x8056, + 0x8057, + 0x8058, + 0x8059, + 0x805a, + 0x805b, + 0x805c, + 0x805d, + 0x805e, + 0x805f, + 0x8060, + 0x8061, + 0x8062, + 0x8063, + 0x8064, + 0x8065, + 0x8066, + 0x8067, + 0x8068, + 0x8069, + 0x806a, + 0x806b, + 0x806c, + 0x806d, + 0x806e, + 0x806f, + 0x8070, + 0x8071, + 0x8072, + 0x8073, + 0x8074, + 0x8075, + 0x8076, + 0x8077, + 0x8078, + 0x8079, + 0x807a, + 0x807b, + 0x807c, + 0x807d, + 0x807e, + 0x807f, + 0x8080, + 0x8081, + 0x8082, + 0x8083, + 0x8084, + 0x8085, + 0x8086, + 0x8087, + 0x8088, + 0x8089, + 0x808a, + 0x808b, + 0x808c, + 0x808d, + 0x808e, + 0x808f, + 0x8090, + 0x8091, + 0x8092, + 0x8094, + 0x8095, + 0x8096, + 0x8097, + 0x8098, + 0x809b, + 0x809c, + 0x809d, + 0x80a0, + 0x80a1, + 0x80a2, + 0x80a3, + 0x80a4, + 0x80a5, + 0x80a6, + 0x80b0, + 0x80b1, + 0x80b2, + 0x80b3, + 0x80b4, + 0x80b5, + 0x80b6, + 0x80b7, + 0x80b8, + 0x80b9, + 0x80ba, + 0x80bb, + 0x80bc, + 0x80bd, + 0x80be, + 0x80bf, + 0x80c0, + 0x80c1, + 0x80c2, + 0x80c3, + 0x80c4, + 0x80c5, + 0x80c6, + 0x80c7, + 0x80c8, + 0x80c9, + 0x80ca, + 0x80cb, + 0x80cc, + 0x80cd, + 0x80ce, + 0x80cf, + 0x80d0, + 0x80d1, + 0x80d2, + 0x80d3, + 0x80d4, + 0x80d5, + 0x80d6, + 0x80d7, + 0x80d8, + 0x80d9, + 0x80da, + 0x80db, + 0x80dc, + 0x80dd, + 0x80de, + 0x80df, + 0x80e0, + 0x80e1, + 0x80e2, + 0x80e3, + 0x80e4, + 0x80e5, + 0x80e6, + 0x80e7, + 0x80e8, + 0x80e9, + 0x80ea, + 0x80eb, + 0x80ec, + 0x80ed, + 0x80ee, + 0x80ef, + 0x80f0, + 0x80f1, + 0x8100, + 0x8101, + 0x8102, + 0x8103, + 0x8104, + 0x8105, + 0x8106, + 0x8107, + 0x8109, + 0x8114, + 0x8115, + 0x8400, + 0x8401, + 0x8402, + 0x8403, + 0x8404, + 0x8405, + 0x8406, + 0x840a, + 0x840b, + 0x8800, + 0x8801, + 0x8802, + 0x8803, + 0x8804, + 0x8805, + 0x8806, + 0x8809, + 0x880a, + 0x880b, + 0x880c, + 0x880d, + 0x880f, + 0x8810, + 0x8820, + 0x8821, + 0x8822, + 0x8823, + 0x8824, + 0x8825, + 0x8826, + 0x8827, + 0x8828, + 0x8829, + 0x882a, + 0x882b, + 0x882c, + 0x882d, + 0x882e, + 0x882f, + 0x8830, + 0x8831, + 0x8832, + 0x8833, + 0x8834, + 0x8835, + 0x8836, + 0x8837, + 0x8838, + 0x8839, + 0x883a, + 0x883b, + 0x883c, + 0x883d, + 0x883e, + 0x883f, + 0x8840, + 0x8841, + 0x8842, + 0x8843, + 0x8844, + 0x8845, + 0x8846, + 0x8847, + 0x8848, + 0x8849, + 0x884a, + 0x884b, + 0x884c, + 0x884d, + 0x884e, + 0x884f, + 0x8850, + 0x8851, + 0x8852, + 0x8853, + 0x8854, + 0x8855, + 0x8856, + 0x8857, + 0x8858, + 0x8859, + 0x885a, + 0x885b, + 0x885c, + 0x885d, + 0x885e, + 0x885f, + 0x8860, + 0x8861, + 0x8862, + 0x8863, + 0x8865, + 0x8870, + 0x8871, + 0x8872, + 0x8873, + 0x8874, + 0x8875, + 0x8876, + 0x8877, + 0x8878, + 0x8879, + 0x8880, + 0x8881, + 0x8882, + 0x8883, + 0x8884, + 0x8885, + 0x8886, + 0x8887, + 0x8888, + 0x8889, + 0x8890, + 0x8898, + 0x88c0, + 0x88c1, + 0x88d0, + 0x88d1, + 0x88d2, + 0x88d3, + 0x88d4, + 0x88d5, + 0x88d6, + 0x88d7, + 0x88d8, + 0x88d9, + 0x88da, + 0x88db, + 0x88dc, + 0x88dd, + 0x88de, + 0x88df, + 0x88e0, + 0x88e1, + 0x88e2, + 0x88e3, + 0x8900, + 0x8901, + 0x8902, + 0x8903, + 0x8904, + 0x8905, + 0x8906, + 0x8907, + 0x8908, + 0x8909, + 0x890a, + 0x890b, + 0x890c, + 0x890d, + 0x890e, + 0x890f, + 0x8910, + 0x8911, + 0x8912, + 0x8913, + 0x8914, + 0x8915, + 0x8916, + 0x8917, + 0x8918, + 0x8919, + 0x891a, + 0x8a00, + 0x8a10, + 0x8a20, + 0x8a30, + 0x8c00, + 0x8c01, + 0x8c17, + 0x8c18, + 0x8c19, + 0x8c1a, + 0x8c1b, + 0x8c1c, + 0x8c1d, + 0x8c1e, + 0x8c1f, + 0x8c20, + 0x8c21, + 0x8c22, + 0x8c23, + 0x8c24, + 0x8c25, + 0x8c2c, + 0x8c2d, + 0x8c2e, + 0x8c2f, + 0x9100, + 0x9101, + 0x9102, + 0x9103, + 0x9104, + 0x9105, + 0x9106, + 0x9107, + 0x9108, + 0x9200, + 0x9201, + 0x9202, + 0x9203, + 0x9204, + 0x9205, + 0x9206, + 0x9207, + 0x9208, + 0x9209, + 0x920a, + 0x920b, + 0x920c, + 0x920d, + 0x920e, + 0x920f, + 0x9212, + 0x9213, + 0x9214, + 0x9215, + 0x9216, + 0x9217, + 0x9301, + 0x9302, + 0x9303, + 0x9304, + 0x9305, + 0x9306, + 0x9311, + 0x9312, + 0x9313, + 0x9314, + 0x9315, + 0x9316, + 0x9800, + 0x9801, + 0x9802, + 0x9803, + 0x9804, + 0x9805, + 0x9806, + 0x9808, + 0x9980, + 0x9981, + 0x9b00, + 0x9b01, + 0x9b02, + 0x9b03, + 0x9b04, + 0x9b05, + 0x9b06, + 0x9b07, + 0x9b08, + 0xa000, + 0xa001, + 0xa002, + 0xa003, + 0xa004, + 0xa005, + 0xa006, + 0xa008, + 0xa00e, + 0xa00f, + 0xa010, + 0xa011, + 0xa012, + 0xa013, + 0xa014, + 0xa015, + 0xa016, + 0xa017, + 0xa018, + 0xa019, + 0xa01a, + 0xa01b, + 0xa01c, + 0xa01d, + 0xa01e, + 0xa01f, + 0xa020, + 0xa021, + 0xa022, + 0xa023, + 0xa024, + 0xa025, + 0xa026, + 0xa027, + 0xa028, + 0xa029, + 0xa02a, + 0xa02b, + 0xa02c, + 0xa02d, + 0xa02e, + 0xa02f, + 0xa030, + 0xa031, + 0xa032, + 0xa033, + 0xa034, + 0xa035, + 0xa036, + 0xa037, + 0xa038, + 0xa039, + 0xa03a, + 0xa03b, + 0xa03c, + 0xa03d, + 0xa03e, + 0xa03f, + 0xa040, + 0xa041, + 0xa042, + 0xa043, + 0xa044, + 0xa045, + 0xa046, + 0xa047, + 0xa048, + 0xa049, + 0xa04a, + 0xa04b, + 0xa04c, + 0xa04d, + 0xa04e, + 0xa04f, + 0xa050, + 0xa051, + 0xa052, + 0xa053, + 0xa054, + 0xa055, + 0xa056, + 0xa057, + 0xa058, + 0xa059, + 0xa05a, + 0xa05b, + 0xa05c, + 0xa05d, + 0xa05e, + 0xa05f, + 0xa060, + 0xa061, + 0xa062, + 0xa063, + 0xa064, + 0xa065, + 0xa066, + 0xa067, + 0xa068, + 0xa069, + 0xa06a, + 0xa06b, + 0xa06c, + 0xa06d, + 0xa06e, + 0xa06f, + 0xa070, + 0xa071, + 0xa072, + 0xa073, + 0xa074, + 0xa075, + 0xa076, + 0xa077, + 0xa078, + 0xa079, + 0xa07a, + 0xa07b, + 0xa07c, + 0xa07d, + 0xa07e, + 0xa07f, + 0xa080, + 0xa081, + 0xa082, + 0xa083, + 0xa084, + 0xa085, + 0xa086, + 0xa087, + 0xa088, + 0xa089, + 0xa08a, + 0xa08b, + 0xa08c, + 0xa08d, + 0xa08e, + 0xa08f, + 0xa090, + 0xa091, + 0xa092, + 0xa093, + 0xa094, + 0xa095, + 0xa096, + 0xa097, + 0xa098, + 0xa099, + 0xa09a, + 0xa09b, + 0xa09c, + 0xa09d, + 0xa09e, + 0xa09f, + 0xa0a0, + 0xa0a1, + 0xa0a2, + 0xa0a3, + 0xa0a4, + 0xa0a5, + 0xa0a6, + 0xa0a7, + 0xa0a8, + 0xa0a9, + 0xa0aa, + 0xa0ab, + 0xa0ac, + 0xa0ad, + 0xa0ae, + 0xa0af, + 0xa0b0, + 0xa0b1, + 0xa0b2, + 0xa0b3, + 0xa0b4, + 0xa0b5, + 0xa0b6, + 0xa0b7, + 0xa0b8, + 0xa0b9, + 0xa0ba, + 0xa0bb, + 0xa0bc, + 0xa0bd, + 0xa0be, + 0xa0bf, + 0xa0c0, + 0xa0c1, + 0xa0c2, + 0xa0c3, + 0xa0c4, + 0xa0c5, + 0xa0c6, + 0xa0c7, + 0xa0c8, + 0xa0c9, + 0xa0ca, + 0xa0cb, + 0xa0cc, + 0xa0cd, + 0xa0ce, + 0xa0cf, + 0xa0d0, + 0xa0d1, + 0xa0d2, + 0xa0d3, + 0xa0d4, + 0xa0d5, + 0xa0d6, + 0xa0d7, + 0xa0d8, + 0xa0d9, + 0xa0da, + 0xa0db, + 0xa0dc, + 0xa0dd, + 0xa0de, + 0xa0df, + 0xa0e0, + 0xa0e1, + 0xa0e2, + 0xa0e3, + 0xa0e4, + 0xa0e5, + 0xa0e6, + 0xa0e7, + 0xa0e8, + 0xa0e9, + 0xa0ea, + 0xa0eb, + 0xa0ec, + 0xa0ed, + 0xa0ee, + 0xa0ef, + 0xa0f8, + 0xa800, + 0xa802, + 0xa803, + 0xa804, + 0xa805, + 0xa806, + 0xa807, + 0xa808, + 0xa809, + 0xa80a, + 0xa80b, + 0xa80c, + 0xa80d, + 0xa80e, + 0xa80f, + 0xa810, + 0xa811, + 0xa812, + 0xa813, + 0xa814, + 0xa815, + 0xa816, + 0xa817, + 0xa818, + 0xa819, + 0xa81a, + 0xa81b, + 0xa81c, + 0xa81d, + 0xa81e, + 0xa81f, + 0xa820, + 0xa821, + 0xa822, + 0xa823, + 0xa824, + 0xa825, + 0xa830, + 0xa831, + 0xa832, + 0xa833, + 0xa834, + 0xa835, + 0xa836, + 0xa837, + 0xa838, + 0xa839, + 0xa83a, + 0xa83b, + 0xa83c, + 0xa83d, + 0xa840, + 0xa842, + 0xa843, + 0xa844, + 0xa845, + 0xa846, + 0xa847, + 0xa848, + 0xa849, + 0xa84a, + 0xa84b, + 0xa84c, + 0xa84d, + 0xa84e, + 0xa84f, + 0xa850, + 0xa851, + 0xa852, + 0xa853, + 0xa854, + 0xa855, + 0xa856, + 0xa857, + 0xa858, + 0xa859, + 0xa85a, + 0xa85b, + 0xa85c, + 0xa85d, + 0xa85e, + 0xa85f, + 0xa860, + 0xa861, + 0xa862, + 0xa863, + 0xa864, + 0xa865, + 0xa870, + 0xa871, + 0xa872, + 0xa873, + 0xa874, + 0xa875, + 0xa876, + 0xa877, + 0xa878, + 0xa879, + 0xa87a, + 0xa87b, + 0xa87c, + 0xa87d, + 0xa87e, + 0xa87f, + 0xa880, + 0xa881, + 0xa882, + 0xa883, + 0xa884, + 0xa885, + 0xa886, + 0xa887, + 0xa888, + 0xa889, + 0xa88a, + 0xa88b, + 0xa88c, + 0xa88d, + 0xa88e, + 0xa88f, + 0xa890, + 0xa891, + 0xa892, + 0xa893, + 0xa894, + 0xa895, + 0xa896, + 0xa980, + 0xa982, + 0xa983, + 0xa984, + 0xa985, + 0xa986, + 0xa987, + 0xa988, + 0xa989, + 0xa98a, + 0xa98b, + 0xa98c, + 0xa98d, + 0xa98e, + 0xa98f, + 0xa990, + 0xa991, + 0xa992, + 0xa993, + 0xa994, + 0xa995, + 0xa996, + 0xa997, + 0xa998, + 0xa999, + 0xa99a, + 0xa99b, + 0xa99c, + 0xa99d, + 0xa99e, + 0xa99f, + 0xa9a0, + 0xa9a1, + 0xa9a2, + 0xa9a3, + 0xa9a4, + 0xa9a5, + 0xa9a6, + 0xa9a7, + 0xa9a9, + 0xa9e0, + 0xa9e1, + 0xa9e4, + 0xa9e5, + 0xab00, + 0xab04, + 0xab05, + 0xab10, + 0xab11, + 0xab12, + 0xab13, + 0xab14, + 0xab15, + 0xab16, + 0xab17, + 0xab18, + 0xab19, + 0xacc0, + 0xb300, + 0xb301, + 0xb304, + 0xb305, + 0xb306, + 0xb307, + 0xb4c0, + 0xb4c1, + 0xb4c2, + 0xb4c3, + 0xb4c4, + 0xb4ca, + 0xb4cb, + 0xb4cc, + 0xb4d1, + 0xb800, + 0xb801, + 0xb802, + 0xb803, + 0xb980, + 0xb982, + 0xb983, + 0xb984, + 0xb985, + 0xb986, + 0xb990, + 0xb991, + 0xb992, + 0xb993, + 0xb994, + 0xb995, + 0xb996, + 0xb997, + 0xb998, + 0xb999, + 0xb99a, + 0xb99b, + 0xb9c0, + 0xb9c1, + 0xb9c2, + 0xb9c3, + 0xb9c4, + 0xb9c5, + 0xb9c6, + 0xb9c7, + 0xb9c8, + 0xb9c9, + 0xbb10, +}; +template<> constexpr inline uint16_t RP_BLIT_REGS<A7XX>[] = { + 0xc02, + 0xc06, + 0xc10, + 0xc11, + 0xc12, + 0xc13, + 0xc14, + 0xc15, + 0xc16, + 0xc17, + 0xc18, + 0xc19, + 0xc1a, + 0xc1b, + 0xc1c, + 0xc1d, + 0xc1e, + 0xc1f, + 0xc20, + 0xc21, + 0xc22, + 0xc23, + 0xc24, + 0xc25, + 0xc26, + 0xc27, + 0xc28, + 0xc29, + 0xc2a, + 0xc2b, + 0xc2c, + 0xc2d, + 0xc2e, + 0xc2f, + 0xc38, + 0xc39, + 0xc3a, + 0xc3b, + 0xc3c, + 0xc3d, + 0xc3e, + 0xc3f, + 0xc40, + 0xc41, + 0xc42, + 0xc43, + 0xc44, + 0xc45, + 0xc46, + 0xc47, + 0xc48, + 0xc49, + 0xc4a, + 0xc4b, + 0xc4c, + 0xc4d, + 0xc4e, + 0xc4f, + 0xc50, + 0xc51, + 0xc52, + 0xc53, + 0xc54, + 0xc55, + 0xc56, + 0xc57, + 0x8000, + 0x8001, + 0x8002, + 0x8003, + 0x8004, + 0x8005, + 0x8006, + 0x8007, + 0x8010, + 0x8011, + 0x8012, + 0x8013, + 0x8014, + 0x8015, + 0x8016, + 0x8017, + 0x8018, + 0x8019, + 0x801a, + 0x801b, + 0x801c, + 0x801d, + 0x801e, + 0x801f, + 0x8020, + 0x8021, + 0x8022, + 0x8023, + 0x8024, + 0x8025, + 0x8026, + 0x8027, + 0x8028, + 0x8029, + 0x802a, + 0x802b, + 0x802c, + 0x802d, + 0x802e, + 0x802f, + 0x8030, + 0x8031, + 0x8032, + 0x8033, + 0x8034, + 0x8035, + 0x8036, + 0x8037, + 0x8038, + 0x8039, + 0x803a, + 0x803b, + 0x803c, + 0x803d, + 0x803e, + 0x803f, + 0x8040, + 0x8041, + 0x8042, + 0x8043, + 0x8044, + 0x8045, + 0x8046, + 0x8047, + 0x8048, + 0x8049, + 0x804a, + 0x804b, + 0x804c, + 0x804d, + 0x804e, + 0x804f, + 0x8050, + 0x8051, + 0x8052, + 0x8053, + 0x8054, + 0x8055, + 0x8056, + 0x8057, + 0x8058, + 0x8059, + 0x805a, + 0x805b, + 0x805c, + 0x805d, + 0x805e, + 0x805f, + 0x8060, + 0x8061, + 0x8062, + 0x8063, + 0x8064, + 0x8065, + 0x8066, + 0x8067, + 0x8068, + 0x8069, + 0x806a, + 0x806b, + 0x806c, + 0x806d, + 0x806e, + 0x806f, + 0x8070, + 0x8071, + 0x8072, + 0x8073, + 0x8074, + 0x8075, + 0x8076, + 0x8077, + 0x8078, + 0x8079, + 0x807a, + 0x807b, + 0x807c, + 0x807d, + 0x807e, + 0x807f, + 0x8080, + 0x8081, + 0x8082, + 0x8083, + 0x8084, + 0x8085, + 0x8086, + 0x8087, + 0x8088, + 0x8089, + 0x808a, + 0x808b, + 0x808c, + 0x808d, + 0x808e, + 0x808f, + 0x8090, + 0x8091, + 0x8092, + 0x8094, + 0x8095, + 0x8096, + 0x8097, + 0x8098, + 0x809b, + 0x809c, + 0x809d, + 0x80a0, + 0x80a1, + 0x80a2, + 0x80a3, + 0x80a4, + 0x80a5, + 0x80a6, + 0x80b0, + 0x80b1, + 0x80b2, + 0x80b3, + 0x80b4, + 0x80b5, + 0x80b6, + 0x80b7, + 0x80b8, + 0x80b9, + 0x80ba, + 0x80bb, + 0x80bc, + 0x80bd, + 0x80be, + 0x80bf, + 0x80c0, + 0x80c1, + 0x80c2, + 0x80c3, + 0x80c4, + 0x80c5, + 0x80c6, + 0x80c7, + 0x80c8, + 0x80c9, + 0x80ca, + 0x80cb, + 0x80cc, + 0x80cd, + 0x80ce, + 0x80cf, + 0x80d0, + 0x80d1, + 0x80d2, + 0x80d3, + 0x80d4, + 0x80d5, + 0x80d6, + 0x80d7, + 0x80d8, + 0x80d9, + 0x80da, + 0x80db, + 0x80dc, + 0x80dd, + 0x80de, + 0x80df, + 0x80e0, + 0x80e1, + 0x80e2, + 0x80e3, + 0x80e4, + 0x80e5, + 0x80e6, + 0x80e7, + 0x80e8, + 0x80e9, + 0x80ea, + 0x80eb, + 0x80ec, + 0x80ed, + 0x80ee, + 0x80ef, + 0x80f0, + 0x80f1, + 0x8100, + 0x8101, + 0x8102, + 0x8103, + 0x8104, + 0x8105, + 0x8106, + 0x8107, + 0x8109, + 0x8113, + 0x8114, + 0x8115, + 0x8116, + 0x8400, + 0x8401, + 0x8402, + 0x8403, + 0x8404, + 0x8405, + 0x8406, + 0x840a, + 0x840b, + 0x8800, + 0x8801, + 0x8802, + 0x8803, + 0x8804, + 0x8805, + 0x8806, + 0x8809, + 0x880a, + 0x880b, + 0x880c, + 0x880d, + 0x880f, + 0x8810, + 0x8812, + 0x8820, + 0x8821, + 0x8822, + 0x8823, + 0x8824, + 0x8825, + 0x8826, + 0x8827, + 0x8828, + 0x8829, + 0x882a, + 0x882b, + 0x882c, + 0x882d, + 0x882e, + 0x882f, + 0x8830, + 0x8831, + 0x8832, + 0x8833, + 0x8834, + 0x8835, + 0x8836, + 0x8837, + 0x8838, + 0x8839, + 0x883a, + 0x883b, + 0x883c, + 0x883d, + 0x883e, + 0x883f, + 0x8840, + 0x8841, + 0x8842, + 0x8843, + 0x8844, + 0x8845, + 0x8846, + 0x8847, + 0x8848, + 0x8849, + 0x884a, + 0x884b, + 0x884c, + 0x884d, + 0x884e, + 0x884f, + 0x8850, + 0x8851, + 0x8852, + 0x8853, + 0x8854, + 0x8855, + 0x8856, + 0x8857, + 0x8858, + 0x8859, + 0x885a, + 0x885b, + 0x885c, + 0x885d, + 0x885e, + 0x885f, + 0x8860, + 0x8861, + 0x8862, + 0x8863, + 0x8865, + 0x8870, + 0x8871, + 0x8872, + 0x8873, + 0x8874, + 0x8875, + 0x8876, + 0x8877, + 0x8878, + 0x8879, + 0x8880, + 0x8881, + 0x8882, + 0x8883, + 0x8884, + 0x8885, + 0x8886, + 0x8887, + 0x8888, + 0x8889, + 0x8890, + 0x8898, + 0x88c0, + 0x88c1, + 0x88d0, + 0x88d1, + 0x88d2, + 0x88d3, + 0x88d4, + 0x88d5, + 0x88d6, + 0x88d7, + 0x88d8, + 0x88d9, + 0x88da, + 0x88db, + 0x88dc, + 0x88dd, + 0x88de, + 0x88df, + 0x88e0, + 0x88e1, + 0x88e2, + 0x88e3, + 0x8900, + 0x8901, + 0x8902, + 0x8903, + 0x8904, + 0x8905, + 0x8906, + 0x8907, + 0x8908, + 0x8909, + 0x890a, + 0x890b, + 0x890c, + 0x890d, + 0x890e, + 0x890f, + 0x8910, + 0x8911, + 0x8912, + 0x8913, + 0x8914, + 0x8915, + 0x8916, + 0x8917, + 0x8918, + 0x8919, + 0x891a, + 0x8c00, + 0x8c01, + 0x8c17, + 0x8c18, + 0x8c19, + 0x8c1a, + 0x8c1b, + 0x8c1c, + 0x8c1d, + 0x8c1e, + 0x8c1f, + 0x8c20, + 0x8c21, + 0x8c22, + 0x8c23, + 0x8c24, + 0x8c25, + 0x8c2c, + 0x8c2d, + 0x8c2e, + 0x8c2f, + 0x9101, + 0x9102, + 0x9103, + 0x9104, + 0x9105, + 0x9106, + 0x9107, + 0x9108, + 0x9109, + 0x910a, + 0x910b, + 0x910c, + 0x9200, + 0x9201, + 0x9202, + 0x9203, + 0x9204, + 0x9205, + 0x9206, + 0x9207, + 0x9208, + 0x9209, + 0x920a, + 0x920b, + 0x920c, + 0x920d, + 0x920e, + 0x920f, + 0x9212, + 0x9213, + 0x9214, + 0x9215, + 0x9216, + 0x9217, + 0x9301, + 0x9302, + 0x9303, + 0x9304, + 0x9305, + 0x9306, + 0x9307, + 0x9308, + 0x9309, + 0x9311, + 0x9312, + 0x9313, + 0x9314, + 0x9315, + 0x9316, + 0x9317, + 0x9800, + 0x9801, + 0x9802, + 0x9803, + 0x9804, + 0x9805, + 0x9806, + 0x9808, + 0x9809, + 0x9b00, + 0x9b01, + 0x9b02, + 0x9b03, + 0x9b04, + 0x9b05, + 0x9b07, + 0x9b08, + 0x9b09, + 0xa000, + 0xa001, + 0xa002, + 0xa003, + 0xa004, + 0xa005, + 0xa006, + 0xa008, + 0xa00e, + 0xa00f, + 0xa010, + 0xa011, + 0xa012, + 0xa013, + 0xa014, + 0xa015, + 0xa016, + 0xa017, + 0xa018, + 0xa019, + 0xa01a, + 0xa01b, + 0xa01c, + 0xa01d, + 0xa01e, + 0xa01f, + 0xa020, + 0xa021, + 0xa022, + 0xa023, + 0xa024, + 0xa025, + 0xa026, + 0xa027, + 0xa028, + 0xa029, + 0xa02a, + 0xa02b, + 0xa02c, + 0xa02d, + 0xa02e, + 0xa02f, + 0xa030, + 0xa031, + 0xa032, + 0xa033, + 0xa034, + 0xa035, + 0xa036, + 0xa037, + 0xa038, + 0xa039, + 0xa03a, + 0xa03b, + 0xa03c, + 0xa03d, + 0xa03e, + 0xa03f, + 0xa040, + 0xa041, + 0xa042, + 0xa043, + 0xa044, + 0xa045, + 0xa046, + 0xa047, + 0xa048, + 0xa049, + 0xa04a, + 0xa04b, + 0xa04c, + 0xa04d, + 0xa04e, + 0xa04f, + 0xa050, + 0xa051, + 0xa052, + 0xa053, + 0xa054, + 0xa055, + 0xa056, + 0xa057, + 0xa058, + 0xa059, + 0xa05a, + 0xa05b, + 0xa05c, + 0xa05d, + 0xa05e, + 0xa05f, + 0xa060, + 0xa061, + 0xa062, + 0xa063, + 0xa064, + 0xa065, + 0xa066, + 0xa067, + 0xa068, + 0xa069, + 0xa06a, + 0xa06b, + 0xa06c, + 0xa06d, + 0xa06e, + 0xa06f, + 0xa070, + 0xa071, + 0xa072, + 0xa073, + 0xa074, + 0xa075, + 0xa076, + 0xa077, + 0xa078, + 0xa079, + 0xa07a, + 0xa07b, + 0xa07c, + 0xa07d, + 0xa07e, + 0xa07f, + 0xa080, + 0xa081, + 0xa082, + 0xa083, + 0xa084, + 0xa085, + 0xa086, + 0xa087, + 0xa088, + 0xa089, + 0xa08a, + 0xa08b, + 0xa08c, + 0xa08d, + 0xa08e, + 0xa08f, + 0xa090, + 0xa091, + 0xa092, + 0xa093, + 0xa094, + 0xa095, + 0xa096, + 0xa097, + 0xa098, + 0xa099, + 0xa09a, + 0xa09b, + 0xa09c, + 0xa09d, + 0xa09e, + 0xa09f, + 0xa0a0, + 0xa0a1, + 0xa0a2, + 0xa0a3, + 0xa0a4, + 0xa0a5, + 0xa0a6, + 0xa0a7, + 0xa0a8, + 0xa0a9, + 0xa0aa, + 0xa0ab, + 0xa0ac, + 0xa0ad, + 0xa0ae, + 0xa0af, + 0xa0b0, + 0xa0b1, + 0xa0b2, + 0xa0b3, + 0xa0b4, + 0xa0b5, + 0xa0b6, + 0xa0b7, + 0xa0b8, + 0xa0b9, + 0xa0ba, + 0xa0bb, + 0xa0bc, + 0xa0bd, + 0xa0be, + 0xa0bf, + 0xa0c0, + 0xa0c1, + 0xa0c2, + 0xa0c3, + 0xa0c4, + 0xa0c5, + 0xa0c6, + 0xa0c7, + 0xa0c8, + 0xa0c9, + 0xa0ca, + 0xa0cb, + 0xa0cc, + 0xa0cd, + 0xa0ce, + 0xa0cf, + 0xa0d0, + 0xa0d1, + 0xa0d2, + 0xa0d3, + 0xa0d4, + 0xa0d5, + 0xa0d6, + 0xa0d7, + 0xa0d8, + 0xa0d9, + 0xa0da, + 0xa0db, + 0xa0dc, + 0xa0dd, + 0xa0de, + 0xa0df, + 0xa0e0, + 0xa0e1, + 0xa0e2, + 0xa0e3, + 0xa0e4, + 0xa0e5, + 0xa0e6, + 0xa0e7, + 0xa0e8, + 0xa0e9, + 0xa0ea, + 0xa0eb, + 0xa0ec, + 0xa0ed, + 0xa0ee, + 0xa0ef, + 0xa0f8, + 0xa800, + 0xa802, + 0xa803, + 0xa804, + 0xa805, + 0xa806, + 0xa807, + 0xa808, + 0xa809, + 0xa80a, + 0xa80b, + 0xa80c, + 0xa80d, + 0xa80e, + 0xa80f, + 0xa810, + 0xa811, + 0xa812, + 0xa813, + 0xa814, + 0xa815, + 0xa816, + 0xa817, + 0xa818, + 0xa819, + 0xa81a, + 0xa81b, + 0xa81c, + 0xa81d, + 0xa81e, + 0xa81f, + 0xa820, + 0xa821, + 0xa822, + 0xa823, + 0xa824, + 0xa825, + 0xa827, + 0xa830, + 0xa831, + 0xa832, + 0xa833, + 0xa834, + 0xa835, + 0xa836, + 0xa837, + 0xa838, + 0xa839, + 0xa83a, + 0xa83b, + 0xa83c, + 0xa83d, + 0xa83f, + 0xa840, + 0xa842, + 0xa843, + 0xa844, + 0xa845, + 0xa846, + 0xa847, + 0xa848, + 0xa849, + 0xa84a, + 0xa84b, + 0xa84c, + 0xa84d, + 0xa84e, + 0xa84f, + 0xa850, + 0xa851, + 0xa852, + 0xa853, + 0xa854, + 0xa855, + 0xa856, + 0xa857, + 0xa858, + 0xa859, + 0xa85a, + 0xa85b, + 0xa85c, + 0xa85d, + 0xa85e, + 0xa85f, + 0xa860, + 0xa861, + 0xa862, + 0xa863, + 0xa864, + 0xa865, + 0xa867, + 0xa870, + 0xa871, + 0xa872, + 0xa873, + 0xa874, + 0xa875, + 0xa876, + 0xa877, + 0xa878, + 0xa879, + 0xa87a, + 0xa87b, + 0xa87c, + 0xa87d, + 0xa87e, + 0xa87f, + 0xa880, + 0xa881, + 0xa882, + 0xa883, + 0xa884, + 0xa885, + 0xa886, + 0xa887, + 0xa888, + 0xa889, + 0xa88a, + 0xa88b, + 0xa88c, + 0xa88d, + 0xa88e, + 0xa88f, + 0xa890, + 0xa891, + 0xa892, + 0xa893, + 0xa894, + 0xa895, + 0xa896, + 0xa898, + 0xa980, + 0xa982, + 0xa983, + 0xa984, + 0xa985, + 0xa986, + 0xa987, + 0xa988, + 0xa989, + 0xa98a, + 0xa98b, + 0xa98c, + 0xa98d, + 0xa98e, + 0xa98f, + 0xa990, + 0xa991, + 0xa992, + 0xa993, + 0xa994, + 0xa995, + 0xa996, + 0xa997, + 0xa998, + 0xa999, + 0xa99a, + 0xa99b, + 0xa99c, + 0xa99d, + 0xa99e, + 0xa99f, + 0xa9a0, + 0xa9a1, + 0xa9a2, + 0xa9a3, + 0xa9a4, + 0xa9a5, + 0xa9a6, + 0xa9a7, + 0xa9a9, + 0xa9aa, + 0xa9ae, + 0xa9bf, + 0xa9c6, + 0xa9c7, + 0xa9c8, + 0xa9c9, + 0xa9ca, + 0xa9cb, + 0xa9d4, + 0xa9d5, + 0xa9d6, + 0xa9d7, + 0xa9d8, + 0xa9d9, + 0xa9da, + 0xa9db, + 0xa9dc, + 0xa9dd, + 0xa9de, + 0xa9e0, + 0xa9e1, + 0xa9e4, + 0xa9e5, + 0xab00, + 0xab03, + 0xab04, + 0xab05, + 0xab0a, + 0xab0b, + 0xab0c, + 0xab0d, + 0xab0e, + 0xab0f, + 0xab10, + 0xab11, + 0xab12, + 0xab13, + 0xab14, + 0xab15, + 0xab16, + 0xab17, + 0xab18, + 0xab19, + 0xab21, + 0xb2c0, + 0xb2c2, + 0xb2c3, + 0xb2ca, + 0xb2cb, + 0xb2cc, + 0xb2d2, + 0xb300, + 0xb301, + 0xb304, + 0xb305, + 0xb306, + 0xb307, +}; +#endif + #endif /* A6XX_XML */ |