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| author | Rob Clark <robdclark@chromium.org> | 2021-04-07 21:04:47 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-04-07 21:04:47 +0300 |
| commit | 9ecccaf9771d3f3bb68ef69d34965b1aad874bd6 (patch) | |
| tree | bb0a01c015b2f2b2a82866a892d6a57310c8973e /drivers/gpu/drm/msm/adreno/a6xx_gmu.c | |
| parent | 1e28eed17697bcf343c6743f0028cc3b5dd88bf0 (diff) | |
| parent | 12aca1ce9ee33af3751aec5e55a5900747cbdd4b (diff) | |
| download | linux-9ecccaf9771d3f3bb68ef69d34965b1aad874bd6.tar.xz | |
Merge tag 'drm-msm-fixes-2021-04-02' into msm-next
Pull in fixes from previous cycle
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a6xx_gmu.c')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 71c917f909af..91cf46f84025 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -339,7 +339,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) else bit = a6xx_gmu_oob_bits[state].ack_new; - gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit); + gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit); } /* Enable CPU control of SPTP power power collapse */ |