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author | Dave Airlie <airlied@redhat.com> | 2024-05-10 03:22:58 +0300 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2024-05-10 03:22:59 +0300 |
commit | c815e4e79bc3e0175a944c59ebd14fbb6d986c27 (patch) | |
tree | 3952f3c5be20e9d151373f47b897599af305a943 /drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | |
parent | f03eee5fc922158654405318a02db9982c0ddf07 (diff) | |
parent | b587f413ca47530b41aadc6f6bda6fc76153f77f (diff) | |
download | linux-c815e4e79bc3e0175a944c59ebd14fbb6d986c27.tar.xz |
Merge tag 'drm-msm-next-2024-05-07' of https://gitlab.freedesktop.org/drm/msm into drm-next
Updates for v6.10
Core:
- Switched to generating register header files during build process
instead of shipping pre-generated headers
- Merged DPU and MDP4 format databases.
DP:
- Stop using compat string to distinguish DP and eDP cases
- Added support for X Elite platform (X1E80100)
- Reworked DP aux/audio support
- Added SM6350 DP to the bindings (no driver changes, using SM8350
as a fallback compat)
GPU:
- a7xx perfcntr reg fixes
- MAINTAINERS updates
- a750 devcoredump support
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGtpw6dNR9JBikFTQ=TCpt-9FeFW+SGjXWv+Jv3emm0Pbg@mail.gmail.com
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c')
-rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 83 |
1 files changed, 57 insertions, 26 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index a847a0f7a73c..0a7717a4fc2f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -13,15 +13,18 @@ */ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-variable" +#pragma GCC diagnostic ignored "-Wunused-const-variable" #include "adreno_gen7_0_0_snapshot.h" #include "adreno_gen7_2_0_snapshot.h" +#include "adreno_gen7_9_0_snapshot.h" #pragma GCC diagnostic pop struct a6xx_gpu_state_obj { const void *handle; u32 *data; + u32 count; /* optional, used when count potentially read from hw */ }; struct a6xx_gpu_state { @@ -192,10 +195,10 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset, } #define cxdbg_write(ptr, offset, val) \ - msm_writel((val), (ptr) + ((offset) << 2)) + writel((val), (ptr) + ((offset) << 2)) #define cxdbg_read(ptr, offset) \ - msm_readl((ptr) + ((offset) << 2)) + readl((ptr) + ((offset) << 2)) /* read a value from the CX debug bus */ static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset, @@ -384,21 +387,29 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); - int debugbus_blocks_count, total_debugbus_blocks; - const u32 *debugbus_blocks; + int debugbus_blocks_count, gbif_debugbus_blocks_count, total_debugbus_blocks; + const u32 *debugbus_blocks, *gbif_debugbus_blocks; int i; if (adreno_is_a730(adreno_gpu)) { debugbus_blocks = gen7_0_0_debugbus_blocks; debugbus_blocks_count = ARRAY_SIZE(gen7_0_0_debugbus_blocks); - } else { - BUG_ON(!adreno_is_a740_family(adreno_gpu)); + gbif_debugbus_blocks = a7xx_gbif_debugbus_blocks; + gbif_debugbus_blocks_count = ARRAY_SIZE(a7xx_gbif_debugbus_blocks); + } else if (adreno_is_a740_family(adreno_gpu)) { debugbus_blocks = gen7_2_0_debugbus_blocks; debugbus_blocks_count = ARRAY_SIZE(gen7_2_0_debugbus_blocks); + gbif_debugbus_blocks = a7xx_gbif_debugbus_blocks; + gbif_debugbus_blocks_count = ARRAY_SIZE(a7xx_gbif_debugbus_blocks); + } else { + BUG_ON(!adreno_is_a750(adreno_gpu)); + debugbus_blocks = gen7_9_0_debugbus_blocks; + debugbus_blocks_count = ARRAY_SIZE(gen7_9_0_debugbus_blocks); + gbif_debugbus_blocks = gen7_9_0_gbif_debugbus_blocks; + gbif_debugbus_blocks_count = ARRAY_SIZE(gen7_9_0_gbif_debugbus_blocks); } - total_debugbus_blocks = debugbus_blocks_count + - ARRAY_SIZE(a7xx_gbif_debugbus_blocks); + total_debugbus_blocks = debugbus_blocks_count + gbif_debugbus_blocks_count; a6xx_state->debugbus = state_kcalloc(a6xx_state, total_debugbus_blocks, sizeof(*a6xx_state->debugbus)); @@ -410,9 +421,9 @@ static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu, &a6xx_state->debugbus[i]); } - for (i = 0; i < ARRAY_SIZE(a7xx_gbif_debugbus_blocks); i++) { + for (i = 0; i < gbif_debugbus_blocks_count; i++) { a6xx_get_debugbus_block(gpu, - a6xx_state, &a7xx_gbif_debugbus_blocks[i], + a6xx_state, &a7xx_debugbus_blocks[gbif_debugbus_blocks[i]], &a6xx_state->debugbus[i + debugbus_blocks_count]); } } @@ -813,10 +824,13 @@ static void a7xx_get_clusters(struct msm_gpu *gpu, if (adreno_is_a730(adreno_gpu)) { clusters = gen7_0_0_clusters; clusters_size = ARRAY_SIZE(gen7_0_0_clusters); - } else { - BUG_ON(!adreno_is_a740_family(adreno_gpu)); + } else if (adreno_is_a740_family(adreno_gpu)) { clusters = gen7_2_0_clusters; clusters_size = ARRAY_SIZE(gen7_2_0_clusters); + } else { + BUG_ON(!adreno_is_a750(adreno_gpu)); + clusters = gen7_9_0_clusters; + clusters_size = ARRAY_SIZE(gen7_9_0_clusters); } a6xx_state->clusters = state_kcalloc(a6xx_state, @@ -948,10 +962,13 @@ static void a7xx_get_shaders(struct msm_gpu *gpu, if (adreno_is_a730(adreno_gpu)) { shader_blocks = gen7_0_0_shader_blocks; num_shader_blocks = ARRAY_SIZE(gen7_0_0_shader_blocks); - } else { - BUG_ON(!adreno_is_a740_family(adreno_gpu)); + } else if (adreno_is_a740_family(adreno_gpu)) { shader_blocks = gen7_2_0_shader_blocks; num_shader_blocks = ARRAY_SIZE(gen7_2_0_shader_blocks); + } else { + BUG_ON(!adreno_is_a750(adreno_gpu)); + shader_blocks = gen7_9_0_shader_blocks; + num_shader_blocks = ARRAY_SIZE(gen7_9_0_shader_blocks); } a6xx_state->shaders = state_kcalloc(a6xx_state, @@ -1337,10 +1354,13 @@ static void a7xx_get_registers(struct msm_gpu *gpu, if (adreno_is_a730(adreno_gpu)) { reglist = gen7_0_0_reg_list; pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers; - } else { - BUG_ON(!adreno_is_a740_family(adreno_gpu)); + } else if (adreno_is_a740_family(adreno_gpu)) { reglist = gen7_2_0_reg_list; pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers; + } else { + BUG_ON(!adreno_is_a750(adreno_gpu)); + reglist = gen7_9_0_reg_list; + pre_crashdumper_regs = gen7_9_0_pre_crashdumper_gpu_registers; } count = A7XX_PRE_CRASHDUMPER_SIZE + A7XX_POST_CRASHDUMPER_SIZE; @@ -1388,7 +1408,8 @@ static void a7xx_get_post_crashdumper_registers(struct msm_gpu *gpu, struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); const u32 *regs; - BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu))); + BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu) || + adreno_is_a750(adreno_gpu))); regs = gen7_0_0_post_crashdumper_registers; a7xx_get_ahb_gpu_registers(gpu, @@ -1417,16 +1438,18 @@ static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu) /* Read a block of data from an indexed register pair */ static void a6xx_get_indexed_regs(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, - struct a6xx_indexed_registers *indexed, + const struct a6xx_indexed_registers *indexed, struct a6xx_gpu_state_obj *obj) { + u32 count = indexed->count; int i; obj->handle = (const void *) indexed; if (indexed->count_fn) - indexed->count = indexed->count_fn(gpu); + count = indexed->count_fn(gpu); - obj->data = state_kcalloc(a6xx_state, indexed->count, sizeof(u32)); + obj->data = state_kcalloc(a6xx_state, count, sizeof(u32)); + obj->count = count; if (!obj->data) return; @@ -1434,7 +1457,7 @@ static void a6xx_get_indexed_regs(struct msm_gpu *gpu, gpu_write(gpu, indexed->addr, 0); /* Read the data - each read increments the internal address by 1 */ - for (i = 0; i < indexed->count; i++) + for (i = 0; i < count; i++) obj->data[i] = gpu_read(gpu, indexed->data); } @@ -1491,10 +1514,18 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + const struct a6xx_indexed_registers *indexed_regs; int i, indexed_count, mempool_count; - BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu))); - indexed_count = ARRAY_SIZE(a7xx_indexed_reglist); + if (adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu)) { + indexed_regs = a7xx_indexed_reglist; + indexed_count = ARRAY_SIZE(a7xx_indexed_reglist); + } else { + BUG_ON(!adreno_is_a750(adreno_gpu)); + indexed_regs = gen7_9_0_cp_indexed_reg_list; + indexed_count = ARRAY_SIZE(gen7_9_0_cp_indexed_reg_list); + } + mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed); a6xx_state->indexed_regs = state_kcalloc(a6xx_state, @@ -1507,7 +1538,7 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu, /* First read the common regs */ for (i = 0; i < indexed_count; i++) - a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_indexed_reglist[i], + a6xx_get_indexed_regs(gpu, a6xx_state, &indexed_regs[i], &a6xx_state->indexed_regs[i]); gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, 0, BIT(2)); @@ -1862,9 +1893,9 @@ static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj, return; print_name(p, " - regs-name: ", indexed->name); - drm_printf(p, " dwords: %d\n", indexed->count); + drm_printf(p, " dwords: %d\n", obj->count); - print_ascii85(p, indexed->count << 2, obj->data); + print_ascii85(p, obj->count << 2, obj->data); } static void a6xx_show_debugbus_block(const struct a6xx_debugbus_block *block, |