diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-03-31 04:14:50 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2023-03-31 20:32:24 +0300 |
| commit | 63899a73190c280644448b0115dc7a1dc0cdb8da (patch) | |
| tree | ba1c1d261f8dba4227beebe261a7bf6746f0b473 /drivers/gpu/drm/msm/adreno | |
| parent | 9a06cd9a0fd7e418545b0ee4ae208163d7708037 (diff) | |
| download | linux-63899a73190c280644448b0115dc7a1dc0cdb8da.tar.xz | |
drm/msm/a6xx: Add support for A650 speed binning
Add support for matching QFPROM fuse values to get the correct speed bin
on A650 (SM8250) GPUs.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530043/
Link: https://lore.kernel.org/r/20230331-topic-konahana_speedbin-v3-2-2dede22dd7f7@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 54f444ba4857..9fb214f150dd 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1847,6 +1847,21 @@ static u32 a640_get_speed_bin(u32 fuse) return UINT_MAX; } +static u32 a650_get_speed_bin(u32 fuse) +{ + if (fuse == 0) + return 0; + else if (fuse == 1) + return 1; + /* Yep, 2 and 3 are swapped! :/ */ + else if (fuse == 2) + return 3; + else if (fuse == 3) + return 2; + + return UINT_MAX; +} + static u32 adreno_7c3_get_speed_bin(u32 fuse) { if (fuse == 0) @@ -1875,6 +1890,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse) if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev)) val = a640_get_speed_bin(fuse); + if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev)) + val = a650_get_speed_bin(fuse); + if (val == UINT_MAX) { DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", |