diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2021-05-25 16:13:16 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-06-23 17:33:56 +0300 |
| commit | c1d12c19efd91b9cda5472bc4ec48854e67c24a8 (patch) | |
| tree | 761db0240dcc253203d3307f91eab942effff7d3 /drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | |
| parent | 310317719ef1735da2fa2e36375889ff90fd89c8 (diff) | |
| download | linux-c1d12c19efd91b9cda5472bc4ec48854e67c24a8.tar.xz | |
drm/msm/mdp5: provide dynamic bandwidth management
Instead of using static bandwidth setup, manage bandwidth dynamically,
depending on the amount of allocated planes, their format and
resolution.
Co-developed-with: James Willcox <jwillcox@squareup.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reported-by: kernel test robot <lkp@intel.com>
Link: https://lore.kernel.org/r/20210525131316.3117809-8-dmitry.baryshkov@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h')
| -rw-r--r-- | drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h index ac269a6802df..918ce1e1bbbd 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h @@ -17,6 +17,7 @@ #include "mdp5_ctl.h" #include "mdp5_smp.h" +struct icc_path; struct mdp5_kms { struct mdp_kms base; @@ -68,6 +69,10 @@ struct mdp5_kms { struct mdp_irq error_handler; int enable_count; + + int num_paths; + struct icc_path *paths[2]; + struct icc_path *path_rot; }; #define to_mdp5_kms(x) container_of(x, struct mdp5_kms, base) @@ -100,6 +105,8 @@ struct mdp5_plane_state { /* assigned by crtc blender */ enum mdp_mixer_stage_id stage; + + u64 plane_bw; }; #define to_mdp5_plane_state(x) \ container_of(x, struct mdp5_plane_state, base) @@ -130,6 +137,9 @@ struct mdp5_crtc_state { * writing CTL[n].START until encoder->enable() */ bool defer_start; + + u64 new_crtc_bw; + u64 old_crtc_bw; }; #define to_mdp5_crtc_state(x) \ container_of(x, struct mdp5_crtc_state, base) @@ -292,6 +302,8 @@ void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode); int mdp5_encoder_get_linecount(struct drm_encoder *encoder); u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder); +void mdp5_kms_set_bandwidth(struct mdp5_kms *mdp5_kms); + #ifdef CONFIG_DRM_MSM_DSI void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |