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author | Chandan Uddaraju <chandanu@codeaurora.org> | 2020-08-28 00:16:56 +0300 |
---|---|---|
committer | Rob Clark <robdclark@chromium.org> | 2020-09-15 20:54:34 +0300 |
commit | 14975cff5b1d076d067ccebf1046be7d2e4fcfbc (patch) | |
tree | 1d7d1fd5bc27960d2b0cdfcf8e55dcb05bf50f5e /drivers/gpu/drm/msm/dp/dp_display.c | |
parent | c943b4948b5848fc0e07f875edbd35a973879e22 (diff) | |
download | linux-14975cff5b1d076d067ccebf1046be7d2e4fcfbc.tar.xz |
drm/msm/dp: add support for DP PLL driver
Add the needed DP PLL specific files to support
display port interface on msm targets.
The DP driver calls the DP PLL driver registration.
The DP driver sets the link and pixel clock sources.
Changes in v2:
-- Update copyright markings on all relevant files.
-- Use DRM_DEBUG_DP for debug msgs.
Changes in v4:
-- Update the DP link clock provider names
Changes in V5:
-- Addressed comments from Stephen Boyd, Rob clark.
Changes in V6:
-- Remove PLL as separate driver and include PLL as DP module
-- Remove redundant clock parsing from PLL module and make DP as
clock provider
-- Map USB3 DPCOM and PHY IO using hardcoded register address and
move mapping form parser to PLL module
-- Access DP PHY modules from same base address using offsets instead of
deriving base address of individual module from device tree.
-- Remove dp_pll_10nm_util.c and include its functionality in
dp_pll_10nm.c
-- Introduce new data structures private to PLL module
Changes in v7:
-- Remove DRM_MSM_DP_PLL config from Makefile and Kconfig
-- Remove set_parent from determin_rate API
-- Remove phy_pll_vco_div_clk from parent list
-- Remove flag CLK_DIVIDER_ONE_BASED
-- Remove redundant cell-index property parsing
Changes in v8:
-- Unregister hardware clocks during driver cleanup
Changes in v9:
-- Remove redundant Kconfig option DRM_MSM_DP_10NM_PLL
Changes in v10:
-- Limit 10nm PLL function scope
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dp/dp_display.c')
-rw-r--r-- | drivers/gpu/drm/msm/dp/dp_display.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index ff381807e350..c8851f4bbf72 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -22,6 +22,7 @@ #include "dp_ctrl.h" #include "dp_display.h" #include "dp_drm.h" +#include "dp_pll.h" static struct msm_dp *g_dp_display; #define HPD_STRING_SIZE 30 @@ -42,6 +43,7 @@ struct dp_display_private { struct dp_usbpd *usbpd; struct dp_parser *parser; + struct msm_dp_pll *pll; struct dp_power *power; struct dp_catalog *catalog; struct drm_dp_aux *aux; @@ -232,7 +234,6 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) edid = dp->panel->edid; dp->audio_supported = drm_detect_monitor_audio(edid); - dp_panel_handle_sink_request(dp->panel); dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; @@ -410,6 +411,7 @@ static void dp_display_deinit_sub_modules(struct dp_display_private *dp) dp_ctrl_put(dp->ctrl); dp_panel_put(dp->panel); dp_aux_put(dp->aux); + dp_pll_put(dp->pll); } static int dp_init_sub_modules(struct dp_display_private *dp) @@ -420,6 +422,9 @@ static int dp_init_sub_modules(struct dp_display_private *dp) struct dp_panel_in panel_in = { .dev = dev, }; + struct dp_pll_in pll_in = { + .pdev = dp->pdev, + }; /* Callback APIs used for cable status change event */ cb->configure = dp_display_usbpd_configure_cb; @@ -450,6 +455,17 @@ static int dp_init_sub_modules(struct dp_display_private *dp) goto error; } + pll_in.parser = dp->parser; + dp->pll = dp_pll_get(&pll_in); + if (IS_ERR_OR_NULL(dp->pll)) { + rc = -EINVAL; + DRM_ERROR("failed to initialize pll, rc = %d\n", rc); + dp->pll = NULL; + goto error; + } + + dp->parser->pll = dp->pll; + dp->power = dp_power_get(dp->parser); if (IS_ERR(dp->power)) { rc = PTR_ERR(dp->power); |