diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-05-01 22:56:20 +0300 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-05-07 02:10:35 +0300 |
| commit | b9b19980a14fc3c37cd3936ef84a5a47aa891965 (patch) | |
| tree | 028e3d81c179c682c5c3d5576db898f5ad5b7b20 /drivers/gpu/drm/msm | |
| parent | 54199009958fab50af7ea308b435438f307214eb (diff) | |
| download | linux-b9b19980a14fc3c37cd3936ef84a5a47aa891965.tar.xz | |
drm/msm/dsi: pll_7nm: remove unsupported dividers for DSI pixel clock
Remove dividers that are not recommended for DSI DPHY mode when setting
up the clock tree for the DSI pixel clock.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Patchwork: https://patchwork.freedesktop.org/patch/484333/
Link: https://lore.kernel.org/r/20220501195620.4135080-1-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 6e506feb111f..66ed1919a1db 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -586,7 +586,7 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provided_clocks) { char clk_name[32], parent[32], vco_name[32]; - char parent2[32], parent3[32], parent4[32]; + char parent2[32]; struct clk_init_data vco_init = { .parent_data = &(const struct clk_parent_data) { .fw_name = "ref", @@ -687,15 +687,13 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_7nm->phy->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_7nm->phy->id); snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_7nm->phy->id); - snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_7nm->phy->id); - snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_7nm->phy->id); hw = devm_clk_hw_register_mux(dev, clk_name, ((const char *[]){ - parent, parent2, parent3, parent4 - }), 4, 0, pll_7nm->phy->base + + parent, parent2, + }), 2, 0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, - 0, 2, 0, NULL); + 0, 1, 0, NULL); if (IS_ERR(hw)) { ret = PTR_ERR(hw); goto fail; |