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| author | Ben Skeggs <bskeggs@redhat.com> | 2018-05-08 13:39:46 +0300 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2018-05-18 08:01:21 +0300 |
| commit | a7cf01809bf23b95413d8047bd91cdc3cedd1ca1 (patch) | |
| tree | 92a72d7f2fe690c30a6b423350d09a671eabfca3 /drivers/gpu/drm/nouveau/nouveau_abi16.c | |
| parent | cc36205085bb6e3a4eed1edbe413fd2235cadb27 (diff) | |
| download | linux-a7cf01809bf23b95413d8047bd91cdc3cedd1ca1.tar.xz | |
drm/nouveau/fifo/gk104-: require explicit runlist selection for channel allocation
We didn't used to be aware that runlist/engine IDs weren't the same thing,
or that there was such variability in configuration between GPUs.
By exposing this information to a client, and giving it explicit control
of which runlist it's allocating a channel on, we're able to make better
choices.
The immediate effect of this is that on GPUs where CE0 is the "GRCE", we
will now be allocating a copy engine running asynchronously to GR for BO
migrations - as intended.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_abi16.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_abi16.c | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index ece650a0c5f9..ea2472770b21 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -23,6 +23,7 @@ #include <nvif/client.h> #include <nvif/driver.h> +#include <nvif/fifo.h> #include <nvif/ioctl.h> #include <nvif/class.h> #include <nvif/cl0002.h> @@ -256,6 +257,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv); struct nouveau_abi16_chan *chan; struct nvif_device *device; + u64 engine; int ret; if (unlikely(!abi16)) @@ -268,25 +270,26 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) /* hack to allow channel engine type specification on kepler */ if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { - if (init->fb_ctxdma_handle != ~0) - init->fb_ctxdma_handle = NVA06F_V0_ENGINE_GR; - else { - init->fb_ctxdma_handle = 0; -#define _(A,B) if (init->tt_ctxdma_handle & (A)) init->fb_ctxdma_handle |= (B) - _(0x01, NVA06F_V0_ENGINE_GR); - _(0x02, NVA06F_V0_ENGINE_MSPDEC); - _(0x04, NVA06F_V0_ENGINE_MSPPP); - _(0x08, NVA06F_V0_ENGINE_MSVLD); - _(0x10, NVA06F_V0_ENGINE_CE0); - _(0x20, NVA06F_V0_ENGINE_CE1); - _(0x40, NVA06F_V0_ENGINE_MSENC); -#undef _ + if (init->fb_ctxdma_handle == ~0) { + switch (init->tt_ctxdma_handle) { + case 0x01: engine = NV_DEVICE_INFO_ENGINE_GR ; break; + case 0x02: engine = NV_DEVICE_INFO_ENGINE_MSPDEC; break; + case 0x04: engine = NV_DEVICE_INFO_ENGINE_MSPPP ; break; + case 0x08: engine = NV_DEVICE_INFO_ENGINE_MSVLD ; break; + case 0x30: engine = NV_DEVICE_INFO_ENGINE_CE ; break; + default: + return nouveau_abi16_put(abi16, -ENOSYS); + } + } else { + engine = NV_DEVICE_INFO_ENGINE_GR; } - /* allow flips to be executed if this is a graphics channel */ + if (engine != NV_DEVICE_INFO_ENGINE_CE) + engine = nvif_fifo_runlist(device, engine); + else + engine = nvif_fifo_runlist_ce(device); + init->fb_ctxdma_handle = engine; init->tt_ctxdma_handle = 0; - if (init->fb_ctxdma_handle == NVA06F_V0_ENGINE_GR) - init->tt_ctxdma_handle = 1; } if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) |