diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2012-06-30 03:44:04 +0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-26 01:50:27 +0400 |
| commit | bc8273fe97019e0cd1cdc893c6b40c0add7e8de3 (patch) | |
| tree | 3577c7f234850042036e6dc977df5ba41b6cd92a /drivers/gpu/drm/radeon/cikd.h | |
| parent | 02c813274114976cb104a32407a21c10c89b0465 (diff) | |
| download | linux-bc8273fe97019e0cd1cdc893c6b40c0add7e8de3.tar.xz | |
drm/radeon: add support mc ucode loading on CIK (v2)
Load the GDDR5 ucode and train the links.
v2: update ucode
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cikd.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/cikd.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 0dab9c545003..2300ae0f09da 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h @@ -139,6 +139,8 @@ #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) #define MC_VM_FB_OFFSET 0x2068 +#define MC_SHARED_BLACKOUT_CNTL 0x20ac + #define MC_ARB_RAMCFG 0x2760 #define NOOFBANK_SHIFT 0 #define NOOFBANK_MASK 0x00000003 @@ -153,6 +155,20 @@ #define NOOFGROUPS_SHIFT 12 #define NOOFGROUPS_MASK 0x00001000 +#define MC_SEQ_SUP_CNTL 0x28c8 +#define RUN_MASK (1 << 0) +#define MC_SEQ_SUP_PGM 0x28cc + +#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 +#define TRAIN_DONE_D0 (1 << 30) +#define TRAIN_DONE_D1 (1 << 31) + +#define MC_IO_PAD_CNTL_D0 0x29d0 +#define MEM_FALL_OUT_CMD (1 << 8) + +#define MC_SEQ_IO_DEBUG_INDEX 0x2a44 +#define MC_SEQ_IO_DEBUG_DATA 0x2a48 + #define HDP_HOST_PATH_CNTL 0x2C00 #define HDP_NONSURFACE_BASE 0x2C04 #define HDP_NONSURFACE_INFO 0x2C08 |