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authorAlex Deucher <alexander.deucher@amd.com>2013-09-21 22:05:48 +0400
committerAlex Deucher <alexander.deucher@amd.com>2013-09-23 18:29:52 +0400
commit225b769d3ee96fd55ec19ea5ed3cb72bfff32ce5 (patch)
tree2f7dc1b8bfa5f0c6ec70616233859afd89507383 /drivers/gpu/drm/radeon/ni_dpm.c
parent1f28fb9271b5bd8a232d11e8e3b9a25e47aefac4 (diff)
downloadlinux-225b769d3ee96fd55ec19ea5ed3cb72bfff32ce5.tar.xz
drm/radeon/dpm/ni: filter clocks based on voltage/clk dep tables
filter out mclk and sclk levels higher than listed in the clk voltage dependency tables. Supporting these clocks will require additional driver tweaking that isn't supported yet. See bug: https://bugs.freedesktop.org/show_bug.cgi?id=68235 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/ni_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/ni_dpm.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index 6c398a456d78..f26339028154 100644
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -787,6 +787,7 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
bool disable_mclk_switching;
u32 mclk, sclk;
u16 vddc, vddci;
+ u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
int i;
if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
@@ -813,6 +814,29 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
}
}
+ /* limit clocks to max supported clocks based on voltage dependency tables */
+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
+ &max_sclk_vddc);
+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
+ &max_mclk_vddci);
+ btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
+ &max_mclk_vddc);
+
+ for (i = 0; i < ps->performance_level_count; i++) {
+ if (max_sclk_vddc) {
+ if (ps->performance_levels[i].sclk > max_sclk_vddc)
+ ps->performance_levels[i].sclk = max_sclk_vddc;
+ }
+ if (max_mclk_vddci) {
+ if (ps->performance_levels[i].mclk > max_mclk_vddci)
+ ps->performance_levels[i].mclk = max_mclk_vddci;
+ }
+ if (max_mclk_vddc) {
+ if (ps->performance_levels[i].mclk > max_mclk_vddc)
+ ps->performance_levels[i].mclk = max_mclk_vddc;
+ }
+ }
+
/* XXX validate the min clocks required for display */
if (disable_mclk_switching) {