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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-12 23:56:02 +0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-07-15 17:37:10 +0400 |
| commit | 1c01103cb90197900beb534911de558d7a43d0b3 (patch) | |
| tree | 55a3b1e0bd4ea45f884577d91eaba293567ee95d /drivers/gpu/drm/radeon/radeon.h | |
| parent | 6c4f978b357bc779c703fda1f200e9179623d3e9 (diff) | |
| download | linux-1c01103cb90197900beb534911de558d7a43d0b3.tar.xz | |
drm/radeon: align VM PTBs (Page Table Blocks) to 32K
Covers requirements of all current asics.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 82e8e36064e3..001081757895 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -784,6 +784,11 @@ struct radeon_mec { /* number of entries in page table */ #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) +/* PTBs (Page Table Blocks) need to be aligned to 32K */ +#define RADEON_VM_PTB_ALIGN_SIZE 32768 +#define RADEON_VM_PTB_ALIGN_MASK (RADEON_VM_PTB_ALIGN_SIZE - 1) +#define RADEON_VM_PTB_ALIGN(a) (((a) + RADEON_VM_PTB_ALIGN_MASK) & ~RADEON_VM_PTB_ALIGN_MASK) + struct radeon_vm { struct list_head list; struct list_head va; |