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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-07-23 17:41:05 +0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-08-31 00:30:08 +0400 |
| commit | 22c775ce80ed921fe9490f3cc2ca66dcda44f572 (patch) | |
| tree | 5c330689c876b94c34857feefdac1b2cbb27cbc3 /drivers/gpu/drm/radeon/radeon.h | |
| parent | 1fd11777c2f0e6b6b37432b984bf40e3c6072f23 (diff) | |
| download | linux-22c775ce80ed921fe9490f3cc2ca66dcda44f572.tar.xz | |
drm/radeon: implement clock and power gating for CIK (v3)
Only the APUs support power gating.
v2: disable cgcg for now
v3: workaround hw issue in mgcg
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index b9706e83e827..5941ada063d1 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -152,6 +152,14 @@ extern int radeon_aspm; #define RADEON_RESET_MC (1 << 10) #define RADEON_RESET_DISPLAY (1 << 11) +/* CG block flags */ +#define RADEON_CG_BLOCK_GFX (1 << 0) +#define RADEON_CG_BLOCK_MC (1 << 1) +#define RADEON_CG_BLOCK_SDMA (1 << 2) +#define RADEON_CG_BLOCK_UVD (1 << 3) +#define RADEON_CG_BLOCK_VCE (1 << 4) +#define RADEON_CG_BLOCK_HDP (1 << 5) + /* max cursor sizes (in pixels) */ #define CURSOR_WIDTH 64 #define CURSOR_HEIGHT 64 @@ -861,6 +869,12 @@ struct radeon_rlc { uint64_t clear_state_gpu_addr; volatile uint32_t *cs_ptr; const struct cs_section_def *cs_data; + u32 clear_state_size; + /* for cp tables */ + struct radeon_bo *cp_table_obj; + uint64_t cp_table_gpu_addr; + volatile uint32_t *cp_table_ptr; + u32 cp_table_size; }; int radeon_ib_get(struct radeon_device *rdev, int ring, |