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authorLyude <lyude@redhat.com>2017-05-20 02:48:37 +0300
committerAlex Deucher <alexander.deucher@amd.com>2017-05-25 01:33:57 +0300
commit4cd096dde950c878e044211f1e7bac384b1588f5 (patch)
tree1d9dcc100949e4ce2899eaff4d10cdeda22cb68b /drivers/gpu/drm/radeon/radeon.h
parente30a52232cbb6f883056aec06abf00cd917c83e8 (diff)
downloadlinux-4cd096dde950c878e044211f1e7bac384b1588f5.tar.xz
drm/radeon: Cleanup display interrupt handling for evergreen, si
The current code here is really, really bad. A huge amount of it looks to be copy pasted, it has some weird hatred of arrays and code sharing, switch cases everywhere for things that really don't need them, and it makes the file seem immensely more complex then it actually is. This is a pain for maintanence, and is vulnerable to more weird irq handling bugs. So, let's start cleaning this up a bit. Modify all of the IRQ handlers for evergreen/si so that they just use for loops. As well, we add a helper function radeon_irq_kms_set_irq_n_enabled(), whose purpose is just to update the state of registers that enable/disable interrupts while printing any changes to the set of enabled interrupts to the kernel log. Note in this commit, since vblank/vline irq acking is intertwined with page flip irq acking, we can't cut out all of the copy paste in evergreen/si_irq_ack() just yet. Changes since v1: - Preserve order we write back all registers Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Lyude <lyude@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 0a0341528471..104f41e52596 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -771,12 +771,7 @@ struct r600_irq_stat_regs {
};
struct evergreen_irq_stat_regs {
- u32 disp_int;
- u32 disp_int_cont;
- u32 disp_int_cont2;
- u32 disp_int_cont3;
- u32 disp_int_cont4;
- u32 disp_int_cont5;
+ u32 disp_int[6];
u32 d1grph_int;
u32 d2grph_int;
u32 d3grph_int;
@@ -2980,6 +2975,12 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
uint32_t *vline_start_end,
uint32_t *vline_status);
+/* interrupt control register helpers */
+void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev,
+ u32 reg, u32 mask,
+ bool enable, const char *name,
+ unsigned n);
+
#include "radeon_object.h"
#endif