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authorDave Airlie <airlied@redhat.com>2016-03-22 02:38:18 +0300
committerAlex Deucher <alexander.deucher@amd.com>2016-03-22 23:04:22 +0300
commitb36f7d26a7fdc0b07b1217368ee09bb8560269f8 (patch)
tree3064c0e7a6463d9496ec3eec2994edf125419091 /drivers/gpu/drm/radeon/radeon_dp_mst.c
parentae20f12d2de6629ee6f679ccf22f9b7b209c464d (diff)
downloadlinux-b36f7d26a7fdc0b07b1217368ee09bb8560269f8.tar.xz
drm/radeon/mst: fix regression in lane/link handling.
The function this used changed in 092c96a8ab9d1bd60ada2ed385cc364ce084180e drm/radeon: fix dp link rate selection (v2) However for MST we should just always train to the max link/rate. Though we probably need to limit this for future hw, in theory radeon won't support it. This fixes my 30" monitor with MST enabled. Cc: stable@vger.kernel.org # v4.4 Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_dp_mst.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_dp_mst.c12
1 files changed, 2 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c
index df7a1719c841..9d210bbcab50 100644
--- a/drivers/gpu/drm/radeon/radeon_dp_mst.c
+++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c
@@ -525,17 +525,9 @@ static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
drm_mode_set_crtcinfo(adjusted_mode, 0);
{
struct radeon_connector_atom_dig *dig_connector;
- int ret;
-
dig_connector = mst_enc->connector->con_priv;
- ret = radeon_dp_get_dp_link_config(&mst_enc->connector->base,
- dig_connector->dpcd, adjusted_mode->clock,
- &dig_connector->dp_lane_count,
- &dig_connector->dp_clock);
- if (ret) {
- dig_connector->dp_lane_count = 0;
- dig_connector->dp_clock = 0;
- }
+ dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
+ dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
dig_connector->dp_lane_count, dig_connector->dp_clock);
}