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authorAlex Deucher <alexander.deucher@amd.com>2013-07-03 23:07:28 +0400
committerAlex Deucher <alexander.deucher@amd.com>2013-07-04 01:37:30 +0400
commit2b90eddcd7091dd631ead1d79e28e79ad589bb8d (patch)
treebe3caf45a587f65844650fb792f3a09267f656a2 /drivers/gpu/drm/radeon/sumo_dpm.c
parent0124853eb1eda5e193e4753bd5d5ac77085027b2 (diff)
downloadlinux-2b90eddcd7091dd631ead1d79e28e79ad589bb8d.tar.xz
drm/radeon/sumo: disable PG when changing UVD clocks
Causes hangs for some people. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/sumo_dpm.c')
-rw-r--r--drivers/gpu/drm/radeon/sumo_dpm.c21
1 files changed, 19 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c
index bf187a5b3d58..b13448f13ee8 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -811,6 +811,23 @@ static void sumo_program_bootup_state(struct radeon_device *rdev)
sumo_power_level_enable(rdev, i, false);
}
+static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
+ struct radeon_ps *new_rps,
+ struct radeon_ps *old_rps)
+{
+ struct sumo_power_info *pi = sumo_get_pi(rdev);
+
+ if (pi->enable_gfx_power_gating) {
+ sumo_gfx_powergating_enable(rdev, false);
+ }
+
+ radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
+
+ if (pi->enable_gfx_power_gating) {
+ sumo_gfx_powergating_enable(rdev, true);
+ }
+}
+
static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
struct radeon_ps *new_rps,
struct radeon_ps *old_rps)
@@ -826,7 +843,7 @@ static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
current_ps->levels[current_ps->num_levels - 1].sclk)
return;
- radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
+ sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
}
static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
@@ -844,7 +861,7 @@ static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
current_ps->levels[current_ps->num_levels - 1].sclk)
return;
- radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
+ sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
}
void sumo_take_smu_control(struct radeon_device *rdev, bool enable)