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authorThierry Reding <treding@nvidia.com>2018-02-05 16:07:57 +0300
committerThierry Reding <treding@nvidia.com>2019-10-28 13:18:45 +0300
commit6c651b13e436030f996bcfb2f76833af94e44531 (patch)
tree4f59b6ab85934648b9171052e85346436f6189dc /drivers/gpu/drm/tegra/dp.h
parentdb199502fa8b62afddde5379d94cac0439202111 (diff)
downloadlinux-6c651b13e436030f996bcfb2f76833af94e44531.tar.xz
drm/tegra: dp: Read channel coding capability from sink
Parse from the sink capabilities whether or not it supports ANSI 8B/10B channel coding as specified in ANSI X3.230-1994, clause 11. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dp.h')
-rw-r--r--drivers/gpu/drm/tegra/dp.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/dp.h b/drivers/gpu/drm/tegra/dp.h
index 999078812943..984dac21568e 100644
--- a/drivers/gpu/drm/tegra/dp.h
+++ b/drivers/gpu/drm/tegra/dp.h
@@ -35,6 +35,13 @@ struct drm_dp_link_caps {
* AUX CH handshake not required for link training
*/
bool fast_training;
+
+ /**
+ * @channel_coding:
+ *
+ * ANSI 8B/10B channel coding capability
+ */
+ bool channel_coding;
};
void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,