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author | Akeem G Abodunrin <akeem.g.abodunrin@intel.com> | 2020-01-08 20:34:16 +0300 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-01-14 22:08:40 +0300 |
commit | 53b9bd37af59d1def99b20707536105857eb9bd0 (patch) | |
tree | 289713d19f679baa78da23704feef6b2bba5e022 /drivers/gpu/drm/v3d | |
parent | f58642c1bc7946c315d8617d61916f754d90583f (diff) | |
download | linux-53b9bd37af59d1def99b20707536105857eb9bd0.tar.xz |
drm/i915/gen9: Clear residual context state on context switch
commit bc8a76a152c5f9ef3b48104154a65a68a8b76946 upstream.
Intel ID: PSIRT-TA-201910-001
CVEID: CVE-2019-14615
Intel GPU Hardware prior to Gen11 does not clear EU state
during a context switch. This can result in information
leakage between contexts.
For Gen8 and Gen9, hardware provides a mechanism for
fast cleardown of the EU state, by issuing a PIPE_CONTROL
with bit 27 set. We can use this in a context batch buffer
to explicitly cleardown the state on every context switch.
As this workaround is already in place for gen8, we can borrow
the code verbatim for Gen9.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Kumar Valsan Prathap <prathap.kumar.valsan@intel.com>
Cc: Chris Wilson <chris.p.wilson@intel.com>
Cc: Balestrieri Francesco <francesco.balestrieri@intel.com>
Cc: Bloomfield Jon <jon.bloomfield@intel.com>
Cc: Dutt Sudeep <sudeep.dutt@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/gpu/drm/v3d')
0 files changed, 0 insertions, 0 deletions