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| author | Hoegeun Kwon <hoegeun.kwon@samsung.com> | 2020-09-03 11:01:47 +0300 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2020-09-07 19:14:54 +0300 |
| commit | 373874298cac99dc5b32f831f9aff5e64f75de85 (patch) | |
| tree | 845ef80299c9ac1e257fde5e6a3bf31849478637 /drivers/gpu/drm/vc4 | |
| parent | 81d830137bdb462ca0bef91ba1f187d7be5d0081 (diff) | |
| download | linux-373874298cac99dc5b32f831f9aff5e64f75de85.tar.xz | |
drm/vc4: hdmi: Add pixel BVB clock control
The BCM2711 has another clock that needs to be ramped up depending on the
pixel rate: the pixel BVB clock. Add the code to adjust that clock when
changing the mode.
[Maxime: Changed the commit log, used clk_set_min_rate]
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20200901040759.29992-3-hoegeun.kwon@samsung.com
Link: https://patchwork.freedesktop.org/patch/msgid/d757ddd6549da140f178563e5fd2bf1d129913fd.1599120059.git-series.maxime@cerno.tech
Diffstat (limited to 'drivers/gpu/drm/vc4')
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_hdmi.c | 23 | ||||
| -rw-r--r-- | drivers/gpu/drm/vc4/vc4_hdmi.h | 1 |
2 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index ab7abb409de2..c24510ba7f8f 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -54,6 +54,7 @@ #include "vc4_regs.h" #define CEC_CLOCK_FREQ 40000 +#define VC4_HSM_MID_CLOCK 149985000 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) { @@ -344,6 +345,7 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder) HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); + clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); clk_disable_unprepare(vc4_hdmi->hsm_clock); clk_disable_unprepare(vc4_hdmi->pixel_clock); @@ -516,6 +518,27 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder) return; } + /* + * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup + * at 300MHz. + */ + ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, + (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); + if (ret) { + DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); + clk_disable_unprepare(vc4_hdmi->hsm_clock); + clk_disable_unprepare(vc4_hdmi->pixel_clock); + return; + } + + ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); + if (ret) { + DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); + clk_disable_unprepare(vc4_hdmi->hsm_clock); + clk_disable_unprepare(vc4_hdmi->pixel_clock); + return; + } + if (vc4_hdmi->variant->reset) vc4_hdmi->variant->reset(vc4_hdmi); diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h index 34138e0dd4a6..59639b405b7f 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h @@ -119,6 +119,7 @@ struct vc4_hdmi { struct clk *pixel_clock; struct clk *hsm_clock; struct clk *audio_clock; + struct clk *pixel_bvb_clock; struct debugfs_regset32 hdmi_regset; struct debugfs_regset32 hd_regset; |