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| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-04-28 01:32:49 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-20 02:32:21 +0300 |
| commit | 5f230a144a33d9a33448063a23d65c53b6d84cea (patch) | |
| tree | 5d1c6fad6fe896b174cdb3f7ac8eb95ee4e611ba /drivers/gpu/drm/xe/regs/xe_regs.h | |
| parent | d9b79ad275e7a98c566b3ac4b32950142d6bf9ad (diff) | |
| download | linux-5f230a144a33d9a33448063a23d65c53b6d84cea.tar.xz | |
drm/xe: Use REG_FIELD/REG_BIT for all regs/*.h
Convert the macro declarations to the equivalent GENMASK and
and bitfield prep for all registers.
v2 (Matt Roper):
- Fix wrong conversion of RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK
- Reorder fields of XEHP_SLICE_UNIT_LEVEL_CLKGATE for consistency
- Simplify CTC_SOURCE_* by only defining CTC_SOURCE_DIVIDE_LOGIC
as REG_BIT(0)
v3: Also remove DOP_CLOCK_GATE_ENABLE that is unused and wrongly defined
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://lore.kernel.org/r/20230427223256.1432787-4-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/regs/xe_regs.h')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_regs.h | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 50fc3c469086..9d18430fd225 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -37,10 +37,10 @@ #define XEHPC_BCS7_RING_BASE 0x3ec000 #define XEHPC_BCS8_RING_BASE 0x3ee000 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) -#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8) -#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4) +#define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) +#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4) #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) -#define GT_RENDER_USER_INTERRUPT (1 << 0) +#define GT_RENDER_USER_INTERRUPT REG_BIT(0) #define FF_THREAD_MODE _MMIO(0x20a0) #define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) @@ -86,10 +86,8 @@ #define DG1_MSTR_TILE(t) REG_BIT(t) #define TIMESTAMP_OVERRIDE _MMIO(0x44074) -#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT 0 -#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK 0x3ff -#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT 12 -#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK (0xf << 12) +#define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12) +#define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0) #define GGC _MMIO(0x108040) #define GMS_MASK REG_GENMASK(15, 8) |